CN1744324A - Cell structure for reducing programming current of phase change memory - Google Patents

Abstract

The disclosed unit structure includes substrate of IC, lower pole, alloy phase change layer in chalcogenide, heating layer, upper pole, and layer of insulating medium. The lower pole is setup on substrate, and the upper pole is setup on alloy phase change layer. The alloy phase change layer and the heating layer are inside small hole. Being connected to the lower pole, the heating layer is setup between the low pole and the alloy phase change layer. The invention adds the heating layer of semiconductor, which does not generate phase change, in storage unit. Possessing higher resistance and lower thermal conductivity, the heating layer can lower programmed current, and can generate enough Joule heat to make material of phase change reach melting point. The invention reaches purpose of programming storage cell by using lower current.

Description

Cell structure for reducing programming current of phase change memory

technical field

The invention relates to a device in the technical field of microelectronics, in particular to a unit structure for reducing the programming current of a phase-change memory.

Background technique

The basic principle of phase-change memory technology is to use phase-change materials as storage media. The resistivity of phase-change materials is very different in crystalline and amorphous states. Using programmed electric pulses can make phase-change memory cells in crystalline and amorphous states. Reversible transition between amorphous states. Moreover, the state of the storage unit is non-volatile, that is, when it is set to any state, even if the power is cut off, the storage unit still maintains the resistance value of the state, unless the state of the storage unit is reset. Typical phase change materials are chalcogenide alloy thin films, and a particularly suitable material is GeSbTe alloy. The memory cell includes a pore defined by a dielectric material in which a phase change material is deposited, the phase change material being connected to an electrode on one end of the pore. Electrode contacts allow current to flow through the channel to generate Joule heating to program the cell, or to read the resistive state of the cell. The current phase change memory uses W or TiW alloy as the electrode material, and the resistivity of W is very low (5.39×10 ^-8 Ω.m), and the thermal conductivity is very high (178W/mK), which is not conducive to the phase change. Change medium for heating. When the phase-change material is in the crystalline state, the resistance of the memory cell is very low. To generate enough Joule heat to make the phase-change material reach the melting point, the programming current density must be increased, which will affect the stability and reliability of the device.

After searching the prior art documents, it was found that in 2003, Samsung proposed to use TiN/W as the electrode material ("Writing current reduction for high-density phase-change RAM" ( reduce the write current of high-density phase change memory), YNHwang, SHLee, et al.IEDM, 2003, pp893), and TiN has a higher resistivity (2×10 ^-7 ~ 1×10 ^-5 Ω.m). In 2005, Xia Jilin, Institute of Microsystem and Information Technology, Chinese Academy of Sciences, etc. proposed a patent for adding a transition layer between the electrode and the phase change material (Chinese patent: an improvement and improvement of the cell structure for reducing the writing current of the phase change memory method, patent publication number CN1564337A, publication date: January 12, 2005), the proposed transition layer is Pt, Ti, TiN. When the resistance of the metal transition layer is lower than the crystalline resistance of the phase change medium, it cannot generate large Joule heat and cannot play the role of auxiliary heating. Therefore, by adopting a more suitable material for the heating layer, when the phase change medium is in a low-resistance state, the Joule heat generated by the heating layer can be used to make the phase change material reach the melting point, which can reduce the programming current more effectively, thereby improving the stability and reliability of the device. reliability.

Contents of the invention

The purpose of the present invention is to overcome the deficiencies of the prior art, to provide a cell structure that reduces the programming current of the phase-change memory, so that a semiconductor heating layer that does not undergo phase change is added in the memory cell, and the heating layer has a higher The resistance and lower thermal conductivity can reduce the programming current while generating enough Joule heat to make the phase change material reach the melting point, so as to achieve the purpose of using lower current to program the memory cell.

The present invention is achieved through the following technical solutions. The present invention includes: an integrated circuit substrate, a lower electrode, a chalcogenide alloy phase change layer, a heating layer, an upper electrode, and an insulating medium layer, and the lower electrode is arranged on the integrated circuit substrate , the upper electrode is arranged on the chalcogenide alloy phase change layer, the chalcogenide alloy phase change layer and the heating layer are arranged in the small hole of the insulating medium layer, and the heating layer is arranged between the lower electrode and the chalcogenide alloy phase change layer, The heating layer is connected with the lower electrode.

Another form of the present invention is: an integrated circuit substrate, a lower electrode, a chalcogenide alloy phase change layer, a heating layer, an upper electrode, and an insulating medium layer. The lower electrode is arranged on the integrated circuit substrate, and the upper electrode is arranged on On the chalcogenide alloy phase change layer, the chalcogenide alloy phase change layer and the heating layer are arranged in the small holes of the insulating medium layer, and the heating layer is arranged in the middle of the chalcogenide alloy phase change layer.

The area of the lower electrode is limited by the small holes in the insulating medium layer.

The area of the lower electrode is smaller than that of the upper electrode to obtain a larger current density.

The heating layer is a semiconductor with a resistivity between 10 ^-6 and 10 ² Ω.m.

The heating layer has a thickness of 3-40nm.

The pulse current passes through one end electrode, the lower electrode flows into the storage unit, the current flows out from the other end electrode after passing through the heating layer and the chalcogenide alloy phase change layer, and the programmed electric pulse can make the chalcogenide alloy phase change layer in the crystalline state (low Resistance state) and the reversible transition between the amorphous state (high resistance state). The insulating dielectric layer defines memory cell dimensions and prevents diffusion and thermal crosstalk between memory cells. When a small pulse current flows into the memory cell for the Set (crystallization) process, the chalcogenide alloy phase change layer is in a high-resistance state, and the incoming pulse current causes the chalcogenide alloy phase change layer to generate Joule heat and make the The crystallization of the chalcogenide alloy phase change layer is transformed into a low-resistance state by heating. When a large pulse current flows into the memory cell for Reset (amorphization) process, the chalcogenide alloy phase change layer is in a low-resistance state, and the Joule heat generated is very little. If only relying on the chalcogenide alloy phase change layer Self-heating to reach the melting point requires a large current. After the heating layer is added, when the pulse current passes, the generated Joule heat will be concentrated in the area of the heating layer with higher resistance, and the Joule heat generated by the heating layer can heat the adjacent chalcogenide alloy phase change layer. Since the resistance of the heating layer is larger than that of the chalcogenide alloy phase change layer in the crystalline state, a small current pulse can heat the chalcogenide alloy phase change layer to the melting point, realizing the chalcogenide alloy phase change layer Amorphization, so as to achieve the purpose of effectively reducing the programming current.

The beneficial effects of the present invention are: when the phase-change medium in the memory changes from the low-resistance state to the high-resistance state (i.e. the Reset process), because the resistance of the phase-change medium is low, if relying entirely on the phase-change medium itself to generate heat, it will take a large current. After the heating layer is added in the memory cell structure, the Joule heat generated by the current will be concentrated in the area of the heating layer with higher resistance. Using the Joule heat generated by the heating layer to assist the phase change material to reach the melting point can reduce the programming current more effectively. Since the memory programming current is provided by a peripheral MOSFET (Oxide Field Effect Transistor) circuit, reducing the programming current can achieve the purpose of reducing the memory peripheral circuit area, reducing device power consumption, and improving device stability.

Description of drawings

Fig. 1 is a schematic structural diagram of Embodiment 1 of the present invention.

Fig. 2 is a schematic structural diagram of Embodiment 2 of the present invention.

Detailed ways

Example 1

As shown in Figure 1, the present invention includes: an integrated circuit substrate 1, a lower electrode 2, a chalcogenide alloy phase change layer 3, a heating layer 4, an upper electrode 5, and an insulating medium layer 6, and an integrated circuit substrate 1 is provided with There is a lower electrode 2, the upper electrode 5 is arranged on the chalcogenide alloy phase change layer 3, the chalcogenide alloy phase change layer 3 and the heating layer 4 are arranged in the small hole of the insulating medium layer 6, and the heating layer 4 is arranged on the lower electrode 2 Between the chalcogenide alloy phase change layer 3 , the heating layer 4 is connected to the lower electrode 2 .

The area of the lower electrode 2 is limited by the small holes in the insulating medium layer 6 .

The area of the lower electrode 2 is smaller than the area of the upper electrode 5 to obtain greater current density.

The heating layer 4 is a semiconductor with a resistivity between 10 ^-5 -10 ² Ω.m.

The heating layer 4 has a thickness of 3-40nm.

Example 2

As shown in Figure 2, the present invention includes: an integrated circuit substrate 1, a lower electrode 2, a chalcogenide alloy phase change layer 3, a heating layer 4, an upper electrode 5, and an insulating medium layer 6, and an integrated circuit substrate 1 is provided with There is a lower electrode 2, an upper electrode 5 is arranged on the chalcogenide alloy phase change layer 3, the chalcogenide alloy phase change layer 3 and the heating layer 4 are arranged in the small hole of the insulating medium layer 6, and the heating layer 4 is arranged on the chalcogenide alloy phase change layer 3. In the middle of the compound alloy phase change layer 3 .

The area of the lower electrode 2 is limited by the small holes in the insulating medium layer 6 .

The area of the lower electrode 2 is smaller than the area of the upper electrode 5 to obtain greater current density.

The heating layer 4 is a semiconductor with a resistivity between 10 ^-5 -10 ² Ω.m.

The heating layer 4 has a thickness of 3-40nm.

Claims (6)

1. cellular construction that reduces the phase transition storage program current, comprise: integrated circuit substrate (1), bottom electrode (2), chalcogenide alloy phase change layer (3), top electrode (5), insulating medium layer (6), it is characterized in that, also comprise: zone of heating (4), on integrated circuit substrate (1), be provided with bottom electrode (2), top electrode (5) is located on the chalcogenide alloy phase change layer (3), chalcogenide alloy phase change layer (3) and zone of heating (4) are located in the aperture of insulating medium layer (6), zone of heating (4) is located between bottom electrode (2) and the chalcogenide alloy phase change layer (3), and zone of heating (4) is connected with bottom electrode (2).

2. cellular construction that reduces the phase transition storage program current, comprise: integrated circuit substrate (1), bottom electrode (2), chalcogenide alloy phase change layer (3), top electrode (5), insulating medium layer (6), it is characterized in that, also comprise: zone of heating (4), on integrated circuit substrate (1), be provided with bottom electrode (2), top electrode (5) is located on the chalcogenide alloy phase change layer (3), chalcogenide alloy phase change layer (3) and zone of heating (4) are located in the aperture of insulating medium layer (6), and zone of heating (4) is located in the middle of the chalcogenide alloy phase change layer (3).

3. the cellular construction of reduction phase transition storage program current according to claim 1 and 2 is characterized in that, the area of described bottom electrode (2) is limited by the aperture of insulating medium layer (6).

4. the cellular construction of reduction phase transition storage program current according to claim 3 is characterized in that, the area of described bottom electrode (2) is less than the area of top electrode (5).

5. the cellular construction of reduction phase transition storage program current according to claim 1 and 2 is characterized in that, described zone of heating (4) is a semiconductor, and resistivity is 10 ^-5～10 ²Between the Ω .m.

6. according to the cellular construction of claim 1 or 2 or 5 described reduction phase transition storage program currents, it is characterized in that described zone of heating (4), its thickness are 3-40nm.

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