CN1741709A - 电路板及电路板制造方法 - Google Patents
电路板及电路板制造方法 Download PDFInfo
- Publication number
- CN1741709A CN1741709A CNA2005100915957A CN200510091595A CN1741709A CN 1741709 A CN1741709 A CN 1741709A CN A2005100915957 A CNA2005100915957 A CN A2005100915957A CN 200510091595 A CN200510091595 A CN 200510091595A CN 1741709 A CN1741709 A CN 1741709A
- Authority
- CN
- China
- Prior art keywords
- supply line
- dielectric layer
- power supply
- circuit board
- signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 5
- 239000002966 varnish Substances 0.000 claims description 32
- 238000000034 method Methods 0.000 claims description 3
- 238000002844 melting Methods 0.000 description 8
- 230000008018 melting Effects 0.000 description 8
- 230000001902 propagating effect Effects 0.000 description 7
- 239000000463 material Substances 0.000 description 5
- 238000010438 heat treatment Methods 0.000 description 4
- 238000009413 insulation Methods 0.000 description 4
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 3
- 229910052802 copper Inorganic materials 0.000 description 3
- 239000010949 copper Substances 0.000 description 3
- 230000005540 biological transmission Effects 0.000 description 2
- 230000008878 coupling Effects 0.000 description 2
- 238000010168 coupling process Methods 0.000 description 2
- 238000005859 coupling reaction Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 239000000155 melt Substances 0.000 description 2
- 238000011084 recovery Methods 0.000 description 2
- 230000009977 dual effect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 230000003121 nonmonotonic effect Effects 0.000 description 1
- 238000006116 polymerization reaction Methods 0.000 description 1
- 230000011664 signaling Effects 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4611—Manufacturing multilayer circuits by laminating two or more circuit boards
- H05K3/4641—Manufacturing multilayer circuits by laminating two or more circuit boards having integrally laminated metal sheets or special power cores
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/02—Fillers; Particles; Fibers; Reinforcement materials
- H05K2201/0275—Fibers and reinforcement materials
- H05K2201/0281—Conductive fibers
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/02—Fillers; Particles; Fibers; Reinforcement materials
- H05K2201/0275—Fibers and reinforcement materials
- H05K2201/029—Woven fibrous reinforcement or textile
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
- H05K2201/0929—Conductive planes
- H05K2201/09309—Core having two or more power planes; Capacitive laminate of two power planes
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Structure Of Printed Boards (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
Abstract
Description
Claims (13)
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US10/928,616 US7271472B2 (en) | 2004-08-27 | 2004-08-27 | Circuit board and method for producing a circuit board |
| DE10/92861.6 | 2004-08-27 | ||
| US10/928616 | 2004-08-27 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1741709A true CN1741709A (zh) | 2006-03-01 |
| CN100525579C CN100525579C (zh) | 2009-08-05 |
Family
ID=35941900
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB2005100915957A Expired - Fee Related CN100525579C (zh) | 2004-08-27 | 2005-08-26 | 电路板及电路板制造方法 |
Country Status (3)
| Country | Link |
|---|---|
| US (1) | US7271472B2 (zh) |
| CN (1) | CN100525579C (zh) |
| DE (1) | DE102005037392A1 (zh) |
Families Citing this family (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20090008139A1 (en) * | 2007-07-03 | 2009-01-08 | Sony Ericsson Mobile Communications Ab | Multilayer pwb and a method for producing the multilayer pwb |
| US20090094564A1 (en) * | 2007-10-03 | 2009-04-09 | Budell Timothy W | Method for rapid return path tracing |
| US7882469B2 (en) | 2007-11-27 | 2011-02-01 | International Business Machines Corporation | Automatic verification of adequate conductive return-current paths |
| US8698391B2 (en) | 2009-04-29 | 2014-04-15 | Global Oled Technology Llc | Chiplet display with oriented chiplets and busses |
| TWI502387B (zh) | 2012-08-06 | 2015-10-01 | Wistron Corp | 串擾分析方法 |
| US9015644B2 (en) | 2012-08-06 | 2015-04-21 | Wistron Corp. | Crosstalk analysis method |
Family Cites Families (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5912597A (en) * | 1994-03-31 | 1999-06-15 | Canon Kabushiki Kaisha | Printed circuit board |
| JP3307597B2 (ja) * | 1998-09-30 | 2002-07-24 | 株式会社 アドテック | 印刷配線装置 |
| US6184477B1 (en) * | 1998-12-02 | 2001-02-06 | Kyocera Corporation | Multi-layer circuit substrate having orthogonal grid ground and power planes |
| US6483714B1 (en) * | 1999-02-24 | 2002-11-19 | Kyocera Corporation | Multilayered wiring board |
| US7033883B2 (en) * | 2004-06-04 | 2006-04-25 | Faraday Technology Corp. | Placement method for decoupling capacitors |
-
2004
- 2004-08-27 US US10/928,616 patent/US7271472B2/en not_active Expired - Fee Related
-
2005
- 2005-08-08 DE DE102005037392A patent/DE102005037392A1/de not_active Withdrawn
- 2005-08-26 CN CNB2005100915957A patent/CN100525579C/zh not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| US7271472B2 (en) | 2007-09-18 |
| CN100525579C (zh) | 2009-08-05 |
| US20060043547A1 (en) | 2006-03-02 |
| DE102005037392A1 (de) | 2006-03-30 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| CI01 | Publication of corrected invention patent application |
Correction item: Priority Correct: [32]2004.08.27[33]KR[31]10/2861.6 False: [32]2004.08.27[33]DE[31]10/2861.6 Number: 9 Volume: 22 |
|
| CI02 | Correction of invention patent application |
Correction item: Priority Correct: [32]2004.08.27[33]US[31]10/92861.6 False: [32]2004.08.27[33]DE[31]10/92861.6 Number: 9 Volume: 22 |
|
| COR | Change of bibliographic data |
Free format text: CORRECT: PRIORITY; FROM: ¢32!2004.8.27¢33!DE ¢31!10/92861.6 TO: ¢32!2004.8.27¢33!US ¢31!10/92861.6 |
|
| ERR | Gazette correction |
Free format text: CORRECT: PRIORITY; FROM: ¢32!2004.8.27¢33!DE ¢31!10/92861.6 TO: ¢32!2004.8.27¢33!US ¢31!10/92861.6 |
|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| C41 | Transfer of patent application or patent right or utility model | ||
| C56 | Change in the name or address of the patentee | ||
| CP01 | Change in the name or title of a patent holder |
Address after: Munich, Germany Patentee after: Infineon Technologies AG Address before: Munich, Germany Patentee before: INFINEON TECHNOLOGIES AG |
|
| TR01 | Transfer of patent right |
Effective date of registration: 20121022 Address after: Munich, Germany Patentee after: QIMONDA AG Address before: Munich, Germany Patentee before: Infineon Technologies AG |
|
| C41 | Transfer of patent application or patent right or utility model | ||
| TR01 | Transfer of patent right |
Effective date of registration: 20151223 Address after: German Berg, Laura Ibiza Patentee after: Infineon Technologies AG Address before: Munich, Germany Patentee before: QIMONDA AG |
|
| CF01 | Termination of patent right due to non-payment of annual fee | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20090805 Termination date: 20170826 |