CN1639875A - Power semiconductor device - Google Patents

Abstract

A power semiconductor device includes: an undoped GaN channel layer (1), an n-type Al _0.2 Ga _0.8 N barrier layer (2) formed on the channel layer (1), a p-type Al _0.1 Ga _0.9 N semiconductor layer (3) selectively formed on the barrier layer (2), a drain electrode (4) located on one side of the semiconductor layer (3) and formed on the barrier layer (2), an insulating film (7) formed between at least the semiconductor layer (3) and the drain electrode (4) on the barrier layer (2) adjacent to the semiconductor layer (3), and a field plate electrode (8) formed on the insulating film (7).

Description

power semiconductor device

technical field

The invention relates to a power semiconductor device for power control. In particular, the present invention relates to a lateral type power FET, a Schottky barrier diode (SBD), etc. using a nitride semiconductor.

Background technique

Power semiconductor devices such as switching devices and diodes are used in power control circuits such as switch mode power supplies and inverter circuits. Power semiconductor devices require the following characteristics, namely, high breakdown voltage and low on-resistance. In power semiconductor components there is a trade-off between breakdown voltage and on-resistance which is determined by the component material. According to advanced technologies in recent years, low on-resistance ends the limitation of the main device material, that is, silicon is realized in power semiconductor devices. In order to further reduce the on-resistance, the device material must be changed. Wide bandgap semiconductors such as GaN and AlGaN nitride semiconductors or silicon carbide (SiC) are used as switching device materials. Therefore, the trade-off relationship determined by the above-mentioned materials can be improved, and low on-resistance is realized. HEMTs (High Electron Mobility Transistors) using nitride semiconductors such as GaN and AlGaN have been disclosed in the following documents. This document is "p-Capped GaN-AlGaN-GaN High Electron Mobility Transistors (HEMT)" by R. Coffie et al., IEEE ELECTRON DEVICE LETTERS, VOL.23, No.10, OCTOBER2002, pp. 598-590.

In recent years, research on power semiconductor devices using wide bandgap semiconductors has been continuously conducted. In nitride semiconductors such as GaN, low on-resistance can be achieved. However, it has not been designed in consideration of avalanche withstand capability, which is a unique characteristic of power devices. This is because GaN-based devices are designed on top of radio-frequency (RF) devices.

Incidentally, in the FET, a field plate electrode is provided, whereby a high breakdown voltage is realized. The above technology has been disclosed in, for example, the following documents: JPN.PAT.APPLN.KOKAI Publication Nos. 5-21793 and 2001-230263, Published Japanese Patent No. 3271613.

Contents of the invention

It is an object of the present invention to provide a power semiconductor device which has a high avalanche withstand capability and an extremely low on-resistance.

According to the solution of the present invention, a power semiconductor device is provided, comprising:

A first semiconductor layer of undoped _{AlXGa1 -XN} (0≤X≤1);

A second semiconductor layer of non-doped or n-type _{AlYGa1 -} YN (0≤Y≤1, X<Y) formed on one surface of the first semiconductor layer;

Selecting a third semiconductor layer of p-type _{AlZGa1 -ZN} (0≤Z≤1) formed on the second semiconductor layer;

a first electrode located on one of both sides of the third semiconductor layer and formed on the second semiconductor layer;

an insulating film formed on the second semiconductor layer adjacent to the third semiconductor layer between the third semiconductor layer and the first electrode; and

A field plate electrode formed on an insulating film.

The power semiconductor device of the present invention can realize low on-resistance by combining an AlGaN-based heterojunction structure to generate a two-dimensional electron gas with high mobility, and using the electron gas thus generated as a carrier when carrying current. Using a nitride semiconductor with a wide bandgap, and employing a field plate electrode, a high breakdown voltage can be achieved. In addition, a p-type AlGaN layer is formed on the surface of the semiconductor layer, whereby holes can be quickly discharged when avalanche breakdown occurs; therefore, high avalanche withstand capability can be obtained. The location where avalanche breakdown occurs exists in the semiconductor, that is, on the p-n junction surface, not at the interface between the semiconductor and the end face of a passivation film such as a field plate electrode. For this reason, interface instability caused by heat can be prevented, thus realizing a device with high reliability.

Description of drawings

1 is a cross-sectional view schematically showing a power semiconductor device according to a first embodiment of the present invention;

2 is a cross-sectional view schematically showing a power semiconductor device according to a first modification of the first embodiment;

3 is a cross-sectional view schematically showing a power semiconductor device according to a second modification of the first embodiment;

4 is a cross-sectional view schematically showing a third modified power semiconductor device according to the first embodiment;

5 is a cross-sectional view schematically showing a power semiconductor device according to a second embodiment of the present invention;

6A-6B are sectional views and characteristic diagrams respectively explaining the above-mentioned second embodiment;

7A-7C are sectional views and characteristic diagrams respectively explaining the above-mentioned second embodiment;

8 is a cross-sectional view schematically showing a power semiconductor device according to a third embodiment of the present invention;

9 is a cross-sectional view schematically showing a power semiconductor device according to a fourth embodiment of the present invention;

10 is a cross-sectional view schematically showing a power semiconductor device according to a modification of the fourth embodiment;

11 is a cross-sectional view schematically showing a power semiconductor device according to a fifth embodiment of the present invention;

12 is a sectional view schematically showing a power semiconductor device according to a first modification of the fifth embodiment;

13A and 13B are a sectional view and a top plan view respectively showing a power semiconductor device according to a second modification of the fifth embodiment;

14 is a cross-sectional view schematically showing a power semiconductor device according to a sixth embodiment of the present invention;

15 is a cross-sectional view schematically showing a power semiconductor device according to a seventh embodiment of the present invention; and

16A and 16B are a sectional view and a characteristic view respectively explaining the seventh embodiment described above.

Best Mode for Carrying Out the Invention

Embodiments of the present invention will be described below with reference to the accompanying drawings. The same reference numerals denote the same parts throughout the drawings.

(first embodiment)

1 is a cross-sectional view schematically showing the structure of a junction power HEMT (High Electron Mobility Transistor) according to a first embodiment of the present invention.

The HEMT is provided with a channel layer 1 including a GaN layer (X=0) as non-doped _{AlXGa1 -XN} (0≤X≤1). The thickness of the channel layer 1 is set to be approximately 1 to 2 μm in order to obtain a breakdown voltage of 600V. On the surface (one side) of the channel layer 1, a barrier layer 2 is formed as an n-type _{AlYGa1 -} YN (0≤Y≤1, X<Y) to a thickness of 0.02 µm. The barrier layer 2 includes an Al _0.2 Ga _0.8 N layer (Y=0.2) in which Si is doped as an impurity at a dose of about 10 ¹³ (atoms/cm ² ). Further, semiconductor layer 3 is selectively formed on barrier layer 2 as p-type _{AlZGa1 -} ZN (0≤Z≤1) with a thickness of 0.01 µm. The semiconductor layer 3 includes Al _0.1 Ga _0.9 N (Z=0.1) in which Mg is doped as an impurity.

A drain electrode (D: first electrode) 4 and a source electrode (S: second electrode) 5 composed of Ti/Al/Ni/Au are formed separately from each other on both sides of the above-mentioned semiconductor layer 3 on the barrier layer 2 . The aforementioned drain and source electrodes 4 and 5 are electrically connected to the surface of the barrier layer 2, respectively.

A gate electrode (G: control electrode) 6 made of Pt or Ni/Au is formed on the semiconductor layer 3 . Gate electrode 6 is electrically connected to the surface of semiconductor layer 3 .

The insulating film 7 is formed to continuously cover the above-mentioned gate electrode 6 and the surrounding barrier layer 2 . Field plate electrode 8 composed of Ti/Al/Ni/Au is formed on insulating film 7 so that it can be disposed between gate electrode 6 and drain electrode 4 . Field plate electrode 8 is electrically connected to the surface of source electrode 5 .

The HEMT having the above structure operates as a junction FET in which the depth of the depletion layer formed in the surface region of the channel layer 1 is controlled according to the voltage applied to the gate electrode 6 . Therefore, the current flowing between the source electrode 5 and the drain electrode 4 is controlled according to the depth of the depletion layer.

In the HEMT of the first embodiment, a nitride semiconductor having a wide bandgap such as _{AlXGa1 -XN} , _{AlYGa1 -} YN, and _{AlZGa1 -} ZN is used as a device material. Therefore, the critical field is enhanced, so that a high breakdown voltage of the device can be achieved. Field plate electrode 8 is formed between a gate electrode and a drain electrode that determine a breakdown voltage. Therefore, when a voltage is applied, the electric field applied between the gate electrode 6 and the drain electrode 4 is regenerated, so that the breakdown voltage can be prevented from gradually decreasing. A two-dimensional electron gas with high mobility is generated in the AlGaN/GaN hetero interface including the barrier layer 2 and the channel layer 1; therefore, low on-resistance can be realized.

A p-type semiconductor layer 3 is further formed on the n-type barrier layer 2 . Therefore, if an avalanche breakdown occurs in the device, the generated holes quickly move into the p-type semiconductor layer 3, thereby achieving high avalanche withstand capability.

In addition, p-type semiconductor layer 3 is formed on barrier layer 2; therefore, the effect of reducing gate leakage current is obtained.

In a normal HEMT structure, the breakdown voltage is determined by the electric field generated in the Schottky junction of the gate. In contrast, in the above-mentioned HEMT structure of the above-mentioned embodiment, the electric field generated in the p-n junction between the p-type semiconductor layer 3 and the n-type barrier layer determines the above-mentioned breakdown voltage. In other words, there is a breakdown point in the semiconductor layer compared to a structure in which characteristic non-uniformity of a Schottky junction device tends to become large. Therefore, the effect of non-uniformity in breakdown voltage can be prevented.

Furthermore, in a normal HEMT structure, high electric fields are generated in Schottky interfaces, field plate ends, metal interfaces between semiconductors and passivation films, and the like. For this reason, if it is designed so that avalanche breakdown occurs in the above-mentioned point, characteristic changes caused by heat are likely to occur. In contrast, in the HEMT structure of the above-described embodiments, the breakdown point exists in the pn junction of the semiconductor layer. Therefore, the stability of avalanche breakdown increases, and thus a device with high reliability can be realized.

Field plate electrode 8 is connected to source electrode 5, so the gate/drain capacitance therebetween becomes small; therefore, high-speed switching operation can be realized.

Semiconductor layer 3 including p-type Al _0.1 Ga _0.9 N is uniformly formed together with channel layer 1 and barrier layer 2 by crystal growth. Afterwards, the semiconductor layer 3 may be patterned and formed by etching. In addition, the semiconductor layer 3 is formed by crystal growth, and thereafter, may be formed by a selective oxidation process. Furthermore, the channel layer 1 and the barrier layer 2 are formed by crystal growth; thereafter, the semiconductor layer 3 can be formed on the surface of their layers by selective growth.

(First modified example of the first embodiment)

FIG. 2 is a cross-sectional view schematically showing the structure of the power HEMT shown in FIG. 1 according to a first modification. In the power HEMT shown in FIG. 1 , dielectric layer 7 is formed to continuously cover gate electrode 6 and the surrounding barrier layer 2 , and field plate electrode 8 is electrically connected to source electrode 5 .

In contrast, the power HEMT of FIG. 2 has the following structure. That is, dielectric layer 7 is formed between semiconductor layer 3 and drain electrode 4 and adjacent to semiconductor layer 3 . Gate electrode 6 is formed to extend to dielectric layer 7 in addition to the upper surface of semiconductor layer 3 . In other words, according to the first modification, gate electrode 6 simultaneously functions as field plate electrode 8 shown in FIG. 1 .

The power HEMT of this modified example can obtain the same effect as that of FIG. 1, and in addition, the field plate electrode and the gate electrode can be formed together. Therefore, the following effects can be obtained; that is, the manufacturing process is simplified compared with FIG. 1 .

(Second modified example of the first embodiment)

FIG. 3 is a cross-sectional view schematically showing the structure of the power HEMT shown in FIG. 1 according to a second modification. The power HEMT of FIG. 3 differs from FIG. 1 in that the gate electrode 6 is formed to extend to the surface of the barrier layer 2 adjacent to the drain electrode 4 side of the semiconductor layer 3 .

That is, in the power HEMT of FIG. 3 , the gate electrode 6 and the barrier layer 2 form a Schottky junction.

According to the second modification, the gate electrode 6 is Schottky-connected with the barrier layer 2 . However, since the semiconductor layer 3 is connected to the gate electrode 6, holes are discharged through the semiconductor layer 3 at the time of avalanche breakdown; therefore, a high avalanche withstand capability is realized like the case of FIG. 1 . In addition, the same effects as in the case of Fig. 1 are obtained.

(Third modified example of the first embodiment)

4 is a cross-sectional view schematically showing the structure of the power HEMT shown in FIG. 1 according to a third modification. In the power HEMT of FIG. 3 , gate electrode 6 is formed to extend to the surface of barrier layer 2 adjacent to the side of drain electrode 4 of semiconductor layer 3 . In contrast, in the power HEMT of FIG. 4 , the gate electrode 6 is formed to extend to the surface of the barrier layer 2 adjacent to the source electrode 5 of the semiconductor layer 3 .

According to the third modification, the gate electrode 6 forms a Schottky connection with the barrier layer 2 . However, since the semiconductor layer 3 is connected to the gate electrode 6, holes are discharged through the semiconductor layer 3 at the time of avalanche breakdown; therefore, a high avalanche withstand capability is realized as in the case of FIG. 1 . In addition, the same effects as in the case of Fig. 1 are obtained.

(second embodiment)

5 is a cross-sectional view schematically showing the structure of a junction power HEMT according to a second embodiment of the present invention. In the power HEMT of FIG. 1 , semiconductor layer 3 including a p-AlGaN layer is formed to have the same length as gate electrode 6 . That is, the end of the semiconductor layer 3 on the drain electrode 4 side is positionally aligned with the end of the gate electrode 6 on the drain electrode 4 side.

In contrast, in the power HEMT of the second embodiment, the semiconductor layer 3 including the p-AlGaN layer is formed so that the end portion on the drain electrode 4 side can extend from the end portion of the gate electrode 6 on the drain electrode 4 side to side of the drain electrode 4. Furthermore, the semiconductor layer 3 is formed such that an end portion on the side of the drain electrode 4 can be positioned under the field plate electrode 8 .

6A is an enlarged cross-sectional view of the end portion of the semiconductor layer 3 of the power HEMT of FIG. 5, and FIG. 6B is a characteristic diagram showing the electric field distribution in the barrier layer 2 when the power HEMT of FIG. 5 operates.

As shown in FIG. 5 , semiconductor layer 3 is formed such that an end portion on the side of drain electrode 4 can be positioned under field plate electrode 8 . Thereby, as shown in FIG. 6B , field concentration points exist at the end portion of the semiconductor layer 3 and the end portion of the field plate electrode 8 . In FIG. 6B , characteristic curve (line) 21 represents the case where insulating film 7 is formed thick to a certain length; on the other hand, characteristic curve 22 represents the case where insulating film 7 is formed thin to some extent.

More specifically, insulating layer 7 under field plate electrode 8 is formed to have an appropriate thickness so as to be provided at the end of semiconductor layer 3 at the point where avalanche breakdown occurs, that is, the point where the electric field becomes maximum. Therefore, holes are quickly discharged at the time of avalanche breakdown, and thus sufficient avalanche withstand capability can be ensured.

Next, a method of setting the thickness of the insulating film 7 so that the electric field becomes highest at the end of the semiconductor layer 3 will be described. FIG. 7A is an enlarged cross-sectional view of the end portion of the semiconductor layer 3 of the power HEMT shown in FIG. 5 . FIG. 7B is a characteristic diagram showing the electric field distribution in the horizontal direction when the power HEMT of FIG. 5 is in operation. FIG. 7C is a characteristic diagram showing the electric field distribution in the vertical direction when the power HEMT of FIG. 5 is in operation. 7B and 7C, the point of the end of the semiconductor layer 3 on the side of the drain electrode 4 is set to A, the point of the barrier layer 2 below the end of the field plate electrode 8 is set to B, and the point of the field plate electrode 8 The point on the end is set to C. The electric fields at the above-mentioned points AC are set to _EA , _EB , and _Ec , respectively. In addition, the distance from point A to B, that is, the length of the field plate electrode 8 is set to L, and the thickness of the insulating film 7 is set to t.

On the basis of the magnitude of the electric field at each point and the size of each element, the voltage V _AB between points A and B and the voltage V between points C and B are expressed by the following equations (1) and (2), respectively _CB .

V _AB ＝(E _A +E _B )L/2 …(1)

V _CB = E _c t ... (2)

The potential of the field plate electrode 8 is substantially equal to the potential of the semiconductor layer 3; therefore, the voltage V _AB is equal to the voltage V _CB . As the electric flux density continues, the relationship between the electric fields E _B and E _C is expressed by the following equation (3).

ε _i E _C ＝ ε _S E _B …(3)

where ε _i is the dielectric constant (relative dielectric constant) of the insulating layer 7 and ε _S is the dielectric constant of the barrier layer 2 . The above equations (1)-(3) are modified so that the relationship between the electric fields _EA and _EB can be determined. The above relationship is represented by the following equation (4).

E _A /E _B ＝2ε _S t/ε _i L-1 …(4)

In this case, the electric field E _A is set larger than the electric field E _B , whereby the avalanche withstand capability becomes larger. Therefore, the ratio of E _A to E _B represented by equation (4) is set to be greater than one. Based on the above facts, when equation (4) is modified, the following equation (5) is obtained.

ε _S t > ε _I L ... (5)

Therefore, it is desirable to set the thickness t of the insulating film 7 and the length L of the field plate electrode so that the relationship expressed by the above-mentioned equation (5) can be satisfied.

If the length L of the field plate electrode is set to 2 μm, the insulating film 7 is made of SiO ₂ , and the composition ratio of the barrier layer 2 including the AlGaN layer is set to 0.2, the dielectric constants ε _i and ε _s are 3.9 and 9.3, respectively. Therefore, it is desirable that the thickness of insulating film 7 is set to 0.83 μm or more.

In wide bandgap semiconductors such as AlGaN and GaN, the critical field is close to the dielectric breakdown field of the insulating film. If the dielectric breakdown voltage of the insulating film 7 is smaller than the avalanche breakdown voltage, the dielectric breakdown voltage determines the device breakdown voltage. In this case, if a voltage equal to the breakdown voltage of the device is applied to the device, the device is broken down. If the critical field of the semiconductor layer is equal to the dielectric breakdown field of the insulating film, the electric field E _C at point C shown in FIG. 7C is smaller than the electric field E _A at point A shown in FIG. 7B . Thereby, dielectric breakdown can be avoided.

When the above-mentioned equations (1)-(3) are modified so that the relationship between E _A and E _C can be determined, the above-mentioned relationship is expressed by the following equation (6).

E _A /E _C ＝2t/L-ε _i /ε _S …(6)

The ratio expressed by the above equation (6) becomes larger than 1, whereby dielectric breakdown can be avoided. Therefore, it is desirable to set the thickness t of the insulating film 7 and the length L of the field plate electrode so as to satisfy the following equation (7).

2t/L＞(1+ε _i /ε _S ) …(7)

Likewise, if the length L of the field plate electrode is set to 2 μm, the insulating film 7 is made of SiO ₂ , and the composition ratio of the barrier layer 2 including AlGaN is set to 0.2, the dielectric constants ε _i and ε _S are 3.9 and 9.3, respectively. Therefore, it is desirable to set the thickness t of insulating film 7 to 1.4 μm or more.

(third embodiment)

8 is a cross-sectional view showing the structure of a junction power HEMT according to a third embodiment of the present invention. The distance between the gate and the drain determines the breakdown voltage of the lateral type power device shown in FIG. 1; therefore, it is desirable to set the above distance to be longer. In addition, the distance between the source and gate, which has no relation to the breakdown voltage, is shortened. This is useful for reducing on-resistance. In the power HEMT of the third embodiment, the distance between the gate and the drain is set wider than the distance between the gate and the source in order to achieve a high breakdown voltage and low on-resistance. More specifically, the distance Lgd is set wider than the distance Lgs. That is, the distance Lgd is the length between the end of the gate electrode 6 on the drain electrode 4 side and the end of the drain electrode 4 on the gate electrode 6 side. The distance Lgs is the length between the end of the gate electrode 6 on the source electrode 5 side and the end of the source electrode 5 on the gate electrode 6 side.

FIG. 8 shows a case where the end portion of the semiconductor layer 3 on the side of the drain electrode 4 is located under the field plate electrode 8 . However, the third embodiment is not limited to the above arrangement, and as shown in FIG. 1 , the semiconductor layer 3 may be formed such that the end on the drain electrode 4 side can be aligned with the end of the gate electrode 6 . As shown in FIGS. 3 and 4, the gate electrode 6 may be formed to extend to the surface of the barrier layer 2 adjacent to the drain electrode 4 side of the semiconductor layer 3, or to the source electrode 5 side thereof.

(fourth embodiment)

9 is a cross-sectional view schematically showing the structure of a junction power HEMT according to a fourth embodiment of the present invention. The power HEMT shown in FIG. 9 differs from FIG. 1 in the following respects. That is, semiconductor layer 9 including a GaN layer (W=0) in which Mg is doped as an impurity is formed on the back surface of channel layer 1 as p-type _{AlWGa1 -WN} . (0≤W≤1). A back electrode 10 composed of Pt is further formed on the surface of the semiconductor layer 3 . In this case, the back electrode 10 is electrically connected to the source electrode 5 .

In the power HEMT having the above structure, holes generated when an avalanche occurs are discharged through the semiconductor layer 9 and the back electrode 10; therefore, the avalanche withstand capability can be further enhanced.

(Modification of the fourth embodiment)

Fig. 10 is a sectional view showing a modified example of the fourth embodiment. As shown in FIG. 10 , the thickness of channel layer 1 is set to be smaller than the distance Lgd between gate electrode 6 and drain electrode 4 . Thereby, avalanche breakdown hardly occurs at the junction between the channel layer 1 and the semiconductor layer 9; therefore, the thickness of the channel layer 1 determines the breakdown voltage. In this case, the thickness of the channel layer 1 is controlled in crystal growth; therefore, a device with little variation in breakdown voltage can be manufactured. The impurity concentration contained in the semiconductor layer 9 is high; therefore, holes are released quickly, and thus a high avalanche withstand capability can be obtained.

In the HEMTs of the fourth embodiment and the modification, the contacts formed on the back surface of the channel layer 1 are drawn out from the back surface of the substrate with respect to the semiconductor layer 9 . This contact with respect to the semiconductor layer 9 can be brought out from the same surface as the source electrode 5 . In this case, no conductive substrate is required.

The p-type semiconductor layer 9 quickly discharges holes generated in the channel layer 1 ; therefore, it is desirable that the semiconductor layer 9 has the same or narrower bandgap than the channel layer 1 . For this reason, it is desirable that the composition ratio W of the semiconductor layer 9 is equal to or smaller than the composition ratio X of the channel layer 1 .

(fifth embodiment)

11 is a cross-sectional view schematically showing the structure of a lateral GaN-MISFET according to a fifth embodiment of the present invention.

In the MISFET of the fifth embodiment, a gate insulating film 11 is added to the HEMT shown in FIG. 5 . More specifically, the gate insulating film 11 is formed to continuously cover the semiconductor layer 3 and the surrounding barrier layer 2 . The gate electrode 6 is formed on the gate insulating film 11 above the semiconductor layer 3 . In this case, the gate insulating film 11 is partially formed with an opening portion so that the semiconductor layer 3 can be electrically connected to the gate electrode 6 through the opening portion.

In the MISFET having the above structure, the surface of the channel layer 1 is formed with a reverse channel according to the voltage applied to the gate electrode 6 . The current flowing between the source electrode 5 and the drain electrode 4 is controlled according to the formation state of the reverse channel.

In the MISFETs of the above-described embodiments, nitride semiconductors having wide band gaps such as _{AlXGa1 -XN} , _{AlYGa1 -} YN, and _{AlZGa1 -} ZN are used as device materials. In this way, the critical field can be increased, and a high breakdown voltage can be achieved in the device. A field plate electrode 8 is formed between the gate electrode and the drain electrode to determine a breakdown voltage. This serves to release the electric field applied between the gate electrode 6 and the drain electrode 4 at the time of voltage application; therefore, a decrease in breakdown voltage can be prevented. A two-dimensional electron gas with high mobility is generated in the hetero interface between the barrier layer 2 and the channel layer; therefore, low on-resistance is achieved.

The p-type semiconductor layer 3 is formed on the n-type barrier layer 2 . Therefore, when an avalanche breakdown occurs in the device, the generated holes quickly move into the p-type semiconductor layer 3, whereby a high avalanche effect can be obtained.

In addition, p-type semiconductor layer 3 is formed on barrier layer 2; therefore, the following effect can be obtained in order to reduce gate leakage current.

In the structures of the above embodiments, the electric field in the p-n junction between the p-type semiconductor layer 3 and the n-type barrier layer 2 determines the breakdown voltage. Since the breakdown point exists in the semiconductor layer, the following effect can be obtained in order to prevent non-uniformity of the breakdown voltage.

In the structures of the above-described embodiments, the breakdown point exists in the p-n junction of the semiconductor layer. Therefore, avalanche breakdown is stably increased, and a device with high reliability can be realized.

Since the field plate electrode 8 is connected to the source electrode 5, the capacitance between the gate electrode and the drain electrode becomes small; therefore, high-speed switching operation can be realized.

The semiconductor layer 3 is electrically connected to the gate electrode 6; therefore, the effect that the gate leakage current can be made small can be obtained.

(First modified example of fifth embodiment)

FIG. 12 shows a MISFET according to a first modification of the fifth embodiment. As seen from the MISFET shown in FIG. 12 , the gate insulating film 11 can be formed without an opening portion so that the semiconductor layer 3 can be isolated from the gate electrode 6 . This MISFET has the above structure, whereby gate leakage current can be greatly reduced.

In this case, the semiconductor layer 3 is not electrically connected to the gate electrode, so it becomes a potential floating state, whereby holes are not discharged into the semiconductor layer 3 . For this reason, in the MISFET of the present modification, the source electrode 5 is formed so that it partially extends to the upper portion of the semiconductor layer 3 . Thereby, the semiconductor layer 3 is electrically connected to the source electrode 5 . Therefore, an avalanche current flows into the source electrode 5 through the semiconductor layer 3 ; however, it does not flow into the gate electrode 6 . This serves to reduce the load of the gate drive circuit that drives the gate electrode 6 .

Incidentally, it is desirable that the interface state with the semiconductor layer 3 is small. For this reason, the following films are preferable as the gate insulating film 11 . These films include oxide films such as _{AlxGa2 -XO3 films of} oxidized AlGaN layers, insulating films such as _Al2O3 , SiN deposited by a CVD process, and the like.

If the impurity concentration of the semiconductor layer 3 is too high, this is a factor that degrades the control characteristics of the reverse channel generated by the voltage applied to the gate electrode. In other words, the mutual capacitance of the gate electrode 6 becomes small. On the contrary, if the impurity concentration of the semiconductor layer 3 is too low, the discharge resistance becomes large when holes are discharged. Therefore, it is desirable to set the impurity concentration of the semiconductor layer 3 to be the same as that of the barrier layer 2 in consideration of the above two points.

(Second Modification of Fifth Embodiment)

13A and 13B are a sectional view and a top plan view schematically showing a structure according to a second modification example of the power MISFET shown in FIG. 12 . In the power MISFET shown in FIG. 12, the semiconductor layer 3 has been formed on the entire surface in the gate width direction.

In contrast, in the power MISFET shown in FIGS. 13A and 13B , the semiconductor layer 3 is formed like a rectangular shape in the gate width direction. The semiconductor layer 3 has the above-described shape, whereby the gate threshold voltage and on-resistance can be controlled.

The semiconductor layer 3 is formed in a rectangular shape, thereby forming two portions, that is, two portions in which the semiconductor layer 3 is formed and not formed under the gate. In the portion where the semiconductor layer 3 is formed, the gate threshold voltage is high, and in addition, the channel resistance and the bias resistance between the gate electrode and the source electrode are large. In contrast, in the portion where the semiconductor layer 3 is not formed under the gate, the threshold voltage of the gate is low, and furthermore, the channel resistance and the bias resistance between the gate and the source are small.

Throughout the device, the former and the latter partly operate in parallel; therefore, the threshold voltage or on-resistance can be controlled by changing the spacing and density between the rectangular semiconductor layers 3 .

(sixth embodiment)

14 is a cross-sectional view schematically showing the structure of a lateral GaN-Schottky barrier diode (SBD) according to a sixth embodiment of the present invention.

The SBD is provided with a channel layer 1 comprising an undoped GaN layer, like the FET shown in FIG. 1 . Barrier layer 2 including an n-type Al _0.2 Ga _0.8 N layer (Y=0.2) is formed on the surface of channel layer 1 . Furthermore, a plurality of semiconductor layers 3 including a p-type Al _0.1 Ga _0.9 N layer are selectively formed on the barrier layer 2 .

An anode (A: second electrode) 12 made of Ni/Au is formed to continuously cover the aforementioned semiconductor layer 3 and the surrounding barrier layer 2 . An insulating film 7 is formed on the barrier layer 2 so as to be in contact with the anode 12 . Field plate electrode 8 made of Ni/Au is formed on insulating film 7 . Field plate electrode 8 is electrically connected to anode 12 . Further, a cathode (K: first electrode) 13 composed of Ti/Al/Ni/Au is formed on the barrier layer 2 in a state of being insulated from the above-mentioned anode 12 .

In the SBD of the sixth embodiment, an n-AlGaN/GaN heterostructure including the barrier layer 2 and the channel layer 1 is employed as in the aforementioned HEMT. With this, high breakdown voltage and ultra-low on-resistance can be achieved.

Semiconductor layer 3 including a p-AlGaN layer is formed on barrier layer 2 including n-AlGaN. Thereby, holes can be safely discharged when avalanche breakdown occurs; thus, a high voltage effect can be realized. By forming the semiconductor layer 3 in the above manner, it is possible to reduce the area of the Schottky junction where the anode 12 is in direct contact with the barrier layer, and to reduce the reverse leakage current.

(seventh embodiment)

15 is a cross-sectional view schematically showing a Schottky barrier diode (SBD) according to a seventh embodiment of the present invention.

In the SBD of the seventh embodiment, the semiconductor layer 3 is formed at the end of the Schottky junction. In this case, the end of the semiconductor layer 3 on the cathode 13 side is located between the end of the field plate electrode 8 on the cathode 13 side and the end of the anode 12 on the cathode 13 side.

16A is an enlarged cross-sectional view of the end portion of the semiconductor layer 3 shown in FIG. 15, and FIG. 16B is a characteristic diagram showing the electric field distribution in the barrier layer 2 when the SBD of FIG. 15 operates.

As shown in FIG. 15 , the semiconductor layer 3 is formed so that the end portion on the cathode 13 side can be located under the field plate electrode 88 . By this, a field concentration point exists at the end of the semiconductor layer 3 and the end of the field plate electrode 8, as shown in FIG. 16B. In FIG. 16B, a characteristic curve 23 indicates the case where the insulating film 7 is formed thick to a certain extent; on the other hand, a characteristic curve 24 indicates the case where the insulating film 7 is formed thinner to a certain extent.

More specifically, in the SBD, the thickness t of the insulating film 7 is set so as to satisfy the above-mentioned equations (5) and (7), as described in the above-mentioned HEMT of the second embodiment. In this way, avalanche withstand capability can be ensured and dielectric breakdown can be avoided.

The present invention has been described above on the basis of the first to seventh embodiments. Incidentally, the present invention is not limited to the above-described embodiments, and various modifications can be easily made by those skilled in the art.

For example, in terms of hole discharge, it is desirable that semiconductor layer 3 including a p-AlGaN layer for discharging holes has a bandgap narrower than that of barrier layer 2 including an n-AlGaN layer. That is, it is desirable that the composition ratio of Al is small, and a p-GaN layer can be used. In order to reduce the contact resistance with respect to the semiconductor layer 3, a semiconductor layer having a narrow band gap such as an InGaN layer is used as a contact layer. A contact layer may be formed between the gate electrode 6 or the anode 12 and the semiconductor layer 3 .

In the above-described embodiments, a combination of AlGaN/GaN is used as the device material. In this case, GaN/InGaN or AlN/AlGaN can be used.

The invention is not limited to unipolar devices such as junction FETs. In this case, the present invention is easily applicable to bipolar devices such as pin diodes and IGBTs provided with a p-layer on the drain side of MISFETs as long as the devices are of the lateral type.

Industrial Applicability

As is apparent from the above description, according to the present invention, a lateral type GaN-based power device having high avalanche withstand capability, high breakdown voltage and ultra-low on-resistance can be obtained.

Claims (17)

1. A power semiconductor device, comprising: A first semiconductor layer of undoped _{AlXGa1 -XN} (0≤X≤1); A second semiconductor layer of non-doped or n-type _{AlYGa1 -} YN (0≤Y≤1, X<Y) formed on one surface of the first semiconductor layer; a third semiconductor layer of p-type _{AlZGa1 -} ZN (0≤Z≤1) selectively formed on the second semiconductor layer; a first electrode located on one of both sides of the third semiconductor layer and formed on the second semiconductor layer; an insulating film formed on the second semiconductor layer adjacent to the third semiconductor layer between at least the third semiconductor layer and the first electrode; and A field plate electrode formed on an insulating film. 2. The power semiconductor device according to claim 1, further comprising: a second electrode located on the other side of the sides of the third semiconductor layer and formed on the second semiconductor layer; and a control electrode formed on the third semiconductor layer, The field plate electrode is electrically connected to the control electrode or the second electrode. 3. The power semiconductor device according to claim 2, wherein the end of the third semiconductor layer on the first electrode side is located between the end of the control electrode on the first electrode side and the field plate electrode on the first electrode side. between the ends. 4. The power semiconductor device according to claim 2, wherein when the thickness of the insulating film positioned below the field plate electrode is set to t, the dielectric constant of the insulating film is set to ε _i , and the dielectric constant of the second semiconductor layer is set to ε _S , and when the distance between the end of the third semiconductor layer on the first electrode side and the end of the control electrode on the first electrode side is set to L, then the thickness t of the insulating layer is set to satisfy the following relationship: ε _S t > ε _i L. 5. The power semiconductor device according to claim 2, wherein when the thickness of the insulating film positioned below the field plate electrode is set to t, the dielectric constant of the insulating film is set to ε _i , and the dielectric constant of the second semiconductor layer is set to ε _S , and when the distance between the end of the third semiconductor layer on the first electrode side and the end of the control electrode on the first electrode side is set to L, then the thickness t of the insulating layer is set to satisfy the following relationship: 2t/L>(1+ε _i /ε _S ). 6. The power semiconductor device according to claim 2, wherein an interval between the first electrode and the control electrode is wider than an interval between the second electrode and the control electrode. 7. The power semiconductor device according to claim 2, further comprising: A gate insulating film is formed between the control electrode and the third semiconductor layer. 8. The power semiconductor device according to claim 7, wherein the second electrode is electrically connected to the third semiconductor layer. 9. The power semiconductor device according to claim 8, wherein the third semiconductor layer is formed in a rectangular shape in a direction perpendicular to the first and second electrodes arranged in parallel 10. The power semiconductor device according to claim 2, further comprising: A fourth semiconductor layer of p-type Al _W Ga _1-W N (0≤W≤1, W≤X) is formed on the other surface of the first semiconductor layer, and the fourth semiconductor layer is electrically connected to the second electrode. 11. The power semiconductor device according to claim 10, wherein the thickness of the first semiconductor layer is smaller than the interval between the control electrode and the first electrode. 12. A power semiconductor device, comprising: A first semiconductor layer of undoped _{AlXGa1 -XN} (0≤X≤1); An undoped or n-type _{AlYGa1 -} YN (0≤Y≤1, X<Y) second semiconductor layer formed on the first semiconductor layer; a third semiconductor layer of p-type _{AlZGa1 -} ZN (0≤Z≤1) selectively formed on the second semiconductor layer; an insulating film formed on the second semiconductor layer; a field plate electrode formed on the insulating film; a first electrode formed on the second semiconductor layer; and A second electrode is formed on the third semiconductor layer. 13. The power semiconductor device according to claim 12, wherein the second electrode is electrically connected to the second semiconductor layer. 14. The power semiconductor device according to claim 12, wherein the second electrode is electrically connected to the field plate electrode. 15. The power semiconductor device according to claim 12, wherein an end of the third semiconductor layer on the first electrode side is located at an end of the field plate electrode on the first electrode side and an end of the second electrode on the first electrode side between departments. 16. The power semiconductor device according to claim 12, wherein when the thickness of the insulating film below the field plate electrode is set to t, the dielectric constant of the insulating film is set to ε _i , and the dielectric constant of the second semiconductor layer is set to ε _S , and when the distance between the end of the third semiconductor layer on the first electrode side and the end of the control electrode on the first electrode side is set to L, then the thickness t of the insulating layer is set to satisfy the following relationship: ε _S t > ε _i L. 17. The power semiconductor device according to claim 12, wherein when the thickness of the insulating film below the field plate electrode is set to t, the dielectric constant of the insulating film is set to ε _i , and the dielectric constant of the second semiconductor layer is set to ε _S , and when the distance between the end of the third semiconductor layer on the first electrode side and the end of the control electrode on the first electrode side is set to L, then the thickness t of the insulating layer is set to satisfy the following relationship: 2t/L>(1+ε _i /ε _S ).

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