CN1628334A - image display device - Google Patents

Abstract

An image display device, wherein a gray scale potential generating circuit (24) of a color liquid crystal display device comprises: 65 resistor elements (R1-R65) connected in series, and dividing the voltage (VH-VL) applied between the first and second nodes (N30, N31) to generate 64 gradation voltages (V1 d-V64 d); first current amplifying circuits (31) provided respectively corresponding to gradation potentials (V33 d-V64 d) higher than a precharge potential (VPC) of a data line (6), the charging capability being higher than the discharging capability; the second current amplifying circuits (32) are provided corresponding to gray scale potentials (V1 d-V32 d) lower than the precharge potential (VPC), and have a higher discharging capability than charging capability.

Description

image display device

technical field

The present invention relates to an image display device, and more particularly to an image display device that displays an image based on an image signal.

Background technique

Conventionally, in liquid crystal display devices, a voltage modulation method in which the light transmittance of the liquid crystal cell is changed by changing the drive voltage of the liquid crystal cell has been used. For example, when displaying 64 gray levels, any one of the 64 gray level voltages is selected according to the video signal, and the selected voltage is applied to the liquid crystal unit.

FIG. 37 is a block diagram showing the configuration of a grayscale potential generating circuit 200 for generating 64 grayscale voltages V1d to V64d in such a liquid crystal display device. In FIG. 37, the gray scale potential generation circuit 200 includes resistance elements R1 to R65 and current amplification circuits 201.1 to 201.64.

The resistance elements R1-R65 are connected in series between the nodes N201 and N200, and after dividing the voltage between the nodes N201 and N200, 64 gray scale voltages V1d-V64d are generated. In order to prevent deterioration of the liquid crystal cell, the potentials applied to the nodes N200 and N201 are switched alternately at a predetermined cycle. FIG. 37 shows a state where a high potential VH and a low potential VL are applied to nodes N200 and N201, respectively.

The current amplifying circuits 201.1-201.64 all include pull-up transistors and pull-down transistors. Both pull-up transistors and pull-down transistors have large current drive capabilities. Current amplifying circuits 201.1 to 201.64 output potentials V1d to V64d at the same level as grayscale voltages V1d to V64d generated in resistance elements R1 to R65, respectively.

However, in such a gradation potential generating circuit 200, if the threshold voltages of the transistors of the current amplification circuits 201.1 to 201.64 vary, there is a problem that both the pull-up transistor and the pull-down transistor are turned on at the same time depending on the input potential. As a result, a large through current flows. When such a large through current flows, the power consumption of the liquid crystal display device increases.

FIG. 38 is a structural circuit diagram of a conventional current amplifying circuit 210 . Such a current amplifying circuit 210 is disclosed, for example, in JP-A-2002-123326. In FIG. 38 , the current amplifying circuit 210 includes resistance elements 211 to 213 , a pull-type drive circuit 214 and a push-type drive circuit 215 . The resistance elements 211 to 213 are connected in series between the nodes N210 and N213, and divide the voltage VH-VL between the nodes N210 and N213 to generate an upper limit potential V211 and a lower limit potential V212. The pull-type drive circuit 214 includes a pull-down N-type transistor, and causes a current to flow from the output node N215 when the potential VO of the output node N215 is higher than the upper limit potential V211. The push drive circuit 215 includes a pull-up P-type transistor, and flows a current into the output node N215 when the potential VO of the output node N215 is lower than the lower limit potential V212. Therefore, the output potential VO is maintained between the upper limit potential V211 and the lower limit potential V212.

However, in the current amplifying circuit 210, when the threshold voltages of the transistors in the drive circuits 214 and 215 vary, the pull-up N-type transistor and the pull-down P-type transistor may be turned on at the same time. The problem of through current.

Contents of the invention

An object of the present invention is to provide an image display device with low power consumption.

The image display device of the present invention is an image display device for displaying images based on image signals, comprising: a plurality of pixel display elements arranged in multiple rows and columns, respectively performing grayscale display according to applied grayscale potentials; a plurality of scanning lines , respectively set corresponding to multiple rows; multiple data lines, respectively set corresponding to multiple columns; vertical scanning circuit, sequentially select multiple scanning lines at regular intervals, and activate each pixel display element corresponding to the selected scanning line ; The horizontal scanning circuit provides gray scale potentials for each pixel display element activated by the vertical scanning circuit according to the image signal. Here, the horizontal scanning circuit includes: a pre-charging circuit, which makes each data line reach a predetermined pre-charging potential; a potential generating circuit, which generates a plurality of gray-scale potentials different from each other; a first current amplification circuit, corresponding to a plurality of gray-scale potentials. Each gray level potential setting in the potential is higher than the pre-charging potential, and is used to output a potential equal to the corresponding gray level potential, and its charging capacity is higher than the discharging capacity; the second current amplification circuit corresponds to a plurality of gray level potentials The setting of each gray level potential lower than the pre-charging potential is used to output the potential equal to the corresponding gray level potential, and its discharge capacity is higher than the charging capacity; the selection circuit selects multiple gray level potentials according to the image signal Any one of the gray scale potentials, the output potential of the first or second current amplifying circuit corresponding to the selected gray scale potential is provided to each activated pixel display element through each data line. Therefore, since the first current amplifying circuit having a charging capability higher than the discharging capability and the second current amplifying circuit having a discharging capability higher than the charging capability are used, compared with the prior art using a current amplifying circuit having a high charging capability and a discharging capability, The through current in each current amplifier circuit can be reduced, and the power consumption can be reduced.

Description of drawings

1 is a block diagram of the overall structure of a color liquid crystal display device according to Embodiment 1 of the present invention;

Fig. 2 is a structural circuit diagram of a liquid crystal drive circuit arranged corresponding to the liquid crystal element shown in Fig. 1;

Fig. 3 is a structural block diagram of the horizontal scanning circuit shown in Fig. 1;

Fig. 4 is a structural circuit diagram of the gray level potential generating circuit shown in Fig. 3;

Fig. 5 is a structural circuit diagram of the push drive circuit shown in Fig. 4;

Fig. 6 is a structural circuit diagram of the pull-type driving circuit shown in Fig. 4;

Fig. 7 is a structural circuit diagram of the equalizer+precharge circuit shown in Fig. 3;

8 is a circuit diagram showing the operation of the color liquid crystal display device shown in FIGS. 1 to 7;

Fig. 9 is a circuit diagram of a modified example of embodiment 1;

Fig. 10 is a circuit diagram of another modified example of embodiment 1;

11 is a structural circuit diagram of a push drive circuit according to Embodiment 2 of the present invention;

12A to 12C are structural circuit diagrams of the constant current circuit shown in FIG. 11 ;

Fig. 13 is a circuit diagram of a modified example of Embodiment 2;

Fig. 14 is a circuit diagram of another modified example of embodiment 2;

15 is a structural circuit diagram of a push drive circuit according to Embodiment 3 of the present invention;

16A to 16C are structural circuit diagrams of the constant current circuit shown in FIG. 15 respectively;

17 is a circuit diagram of a modified example of Embodiment 3;

Fig. 18 is a circuit diagram of another modified example of embodiment 3;

19 is a structural circuit diagram of a pull-type driving circuit according to Embodiment 4 of the present invention;

Fig. 20 is a circuit diagram of a modified example of Embodiment 4;

Fig. 21 is a circuit diagram of another modified example of Embodiment 4;

22 is a structural circuit diagram of a push-pull drive circuit according to Embodiment 5 of the present invention;

Fig. 23 is a circuit diagram of a modified example of Embodiment 5;

Fig. 24 is a circuit diagram of another modified example of Embodiment 5;

Fig. 25 is a circuit diagram of yet another modified example of Embodiment 5;

26 is a structural circuit diagram of a push-pull drive circuit according to Embodiment 6 of the present invention;

27 is a structural circuit diagram of a push-pull drive circuit according to Embodiment 7 of the present invention;

28 is a structural circuit diagram of a push-pull drive circuit according to Embodiment 8 of the present invention;

29 is a structural circuit diagram of a push-pull drive circuit according to Embodiment 9 of the present invention;

30 is a structural circuit diagram of a push-pull drive circuit according to Embodiment 10 of the present invention;

Fig. 31 is a circuit diagram of a modified example of Embodiment 10;

32 is a structural circuit diagram of a push drive circuit with offset compensation function according to Embodiment 11 of the present invention;

Fig. 33 is the timing diagram of the operation of the push type drive circuit with offset compensation function shown in Fig. 32;

Fig. 34 is another timing diagram of the operation of the push drive circuit with offset compensation function shown in Fig. 32;

35 is a structural circuit diagram of a push-pull drive circuit with an offset compensation function according to Embodiment 13 of the present invention;

36 is a structural circuit diagram of a push-pull drive circuit with offset compensation function according to Embodiment 14 of the present invention;

Fig. 37 is a structural circuit diagram of a gray scale potential generating circuit of a conventional liquid crystal display device;

Fig. 38 is a structural circuit diagram of a conventional current amplifying circuit.

Detailed ways

Example 1

1 is a block diagram showing the structure of a color liquid crystal display device according to Embodiment 1 of the present invention. In FIG. 1, the color liquid crystal display device includes a liquid crystal panel 1, a vertical scanning circuit 7, and a horizontal scanning circuit 8, and is provided, for example, in a mobile phone.

The liquid crystal panel 1 includes a plurality of liquid crystal cells 2 arranged in multiple rows and columns, scanning lines 4 and common potential lines 5 corresponding to each row, and data lines 6 corresponding to each column.

In each row, the liquid crystal cells 2 are grouped in groups of three in advance. In the three liquid crystal cells 2 of each group, R, G, and B color filters are provided, respectively. Three liquid crystal cells 2 of each group constitute one pixel 3 .

In each liquid crystal cell 2, as shown in FIG. 2, a liquid crystal drive circuit 10 is provided. The liquid crystal drive circuit 10 includes an N-type field effect transistor (hereinafter referred to as an N-type transistor) 11 and a capacitor 12 . The N-type transistor 11 is connected between the data line 6 and an electrode 2 a of the liquid crystal cell 2 , and its gate is connected to the scan line 4 . The capacitor 12 is connected between one electrode 2 a of the liquid crystal cell 2 and the common potential line 5 . A drive potential VDDL is supplied to the other electrode of the liquid crystal cell 2 , and a common potential VSS is supplied to the common potential line 5 .

Returning to FIG. 1 , the vertical scanning circuit 7 sequentially selects one of the plurality of scanning lines 4 at predetermined time intervals according to the image signal, and turns the selected scanning line 4 to the "H" level of the selection level. When the scanning line 4 becomes the "H" level of the selection level, the N-type transistor 11 in FIG. Line 6 is coupled.

The horizontal scanning circuit 8 sequentially selects a plurality of data lines 6 , for example 12, during the period when one scanning line 4 is selected by the vertical scanning circuit 7 according to the image signal, and provides grayscale potentials for each selected data line 6 . The light transmittance of the liquid crystal cell 2 varies with the level of the gray scale potential.

When all the liquid crystal cells 2 of the liquid crystal panel 1 are scanned by the vertical scanning circuit 7 and the horizontal scanning circuit 8 , one image is displayed on the liquid crystal panel 1 .

FIG. 3 is a block diagram showing the structure of the horizontal scanning circuit 8 shown in FIG. 1 . In FIG. 3 , the horizontal scanning circuit 8 has a shift register 21 , data latch circuits 22 and 23 , a gray scale potential generating circuit 24 , a multiplexer 25 and an equalizer+precharge circuit 26 .

The shift register 21 controls the data latch circuit 22 in synchronization with the clock signal CLK. The video signal includes 6-bit data signals D0 to D5 serially input in synchronization with the clock signal CLK. Accordingly, 260,000 colors can be displayed in each pixel 3 . The data latch circuit 22 sequentially takes in the 6-bit data signals D0 to D5 included in the video signal controlled by the shift register 21 . The data latch circuit 23 reads the video signal of one line taken into the data latch circuit 22 at a time in response to the latch signal φLT.

The grayscale potential generation circuit 24 generates 64 (=2 ⁶ ) grayscale voltages V1d to V64d. The equalizer + precharge circuit 26 responds to the equalization signal φEQ, is connected between a plurality of data lines 6, and while equalizing the potentials of the plurality of data lines 6, responds to the precharge signal φPC, and precharges each data line 6 to a precharge potential VPCs. The multiplexer 25 selects any one of the 64 grayscale voltages V1d to V64d from the grayscale potential generation circuit 24 according to the 6-bit data signals D0 to D5 from the data latch circuit 23 corresponding to each data line 6 . One potential, the selected potential is supplied to the data line 6.

FIG. 4 is a circuit block diagram showing the structure of the gray level potential generating circuit 24 shown in FIG. 3 . In FIG. 4 , the gray scale potential generating circuit 24 includes resistance elements R1 to R65 and current amplification circuits 30.1 to 30.64.

The resistance elements R1 to R65 are connected in series between the nodes N31 and N30, and divide the voltage supplied between the nodes N31 and N30 to generate 64 gray scale voltages V1d to V64d. Resistive elements R1-R65 form a ladder resistance circuit. Since the liquid crystal driving voltage and the light transmittance of the liquid crystal cell 2 generally have a nonlinear relationship, the resistance values of the resistance elements R1 to R65 are not equal to each other.

Since the liquid crystal cell 2 needs to be AC-driven in a predetermined period (one row period, one column period, etc.), the potential of the node N30 and the potential of the node N31 are alternately switched in a predetermined period. The drive potential VDDL in FIG. 2 is set to the same potential as the node N31. FIG. 4 shows a state where the high potential VH is supplied to the node N30 and the low potential VL is supplied to the node N31.

The current amplifying circuits 30.1 to 30.64 output potentials V1d to V64d at the same level as the 64 gray scale voltages V1d to V64d respectively. The current amplifying circuit 30.1 includes a push drive circuit 31, a pull drive circuit 32 and switches S1, S2. As shown in FIG. 5 , the push drive circuit 31 includes a differential amplifier circuit 40 , a switch S3 , a P-type field effect transistor (hereinafter referred to as a P-type transistor) 46 and a constant current circuit 47 . One terminal of the switch S3 receives the power supply potential VDD. The ON/OFF control of the switch S3 is performed in synchronization with the potentials VH, VL of the nodes N30, N31.

The differential amplifier circuit 40 includes P-type transistors 41 , 42 , N-type transistors 43 , 44 and a constant current circuit 45 . The P-type transistors 41 and 42 are respectively connected between the other terminal of the switch S3 and the nodes N41 and N42, and their gates are connected to the node N42. The P-type transistors 41 and 42 constitute a current mirror circuit. N-type transistors 43 and 44 are respectively connected between nodes N41, N42 and node N43, and their gates receive the potential VI (V1d) of the input node N45 and the potential VO of the output node N46, respectively. The constant current circuit 45 flows a constant current I1 of a predetermined value from the node N43 to the ground potential GND line. The P-type transistor 46 is connected between the other terminal of the switch S3 and the output node N46, and its gate receives the potential V41 of the node N41. The constant current circuit 47 flows a constant current I2 of a predetermined value from the output node N46 to the ground potential GND line. The value of the constant current I2 is set very small, thereby suppressing the through current in the drive circuit 31 to be very small.

When the switch S3 is in the off state, the power supply potential VDD is not supplied to the push drive circuit 31 , and no power is consumed in the push drive circuit 31 . When the switch S3 is in an open state, the power supply potential VDD is provided to the push drive circuit 31 to activate the push drive circuit 31 . Currents whose values correspond to the input potential VI and the output potential VO flow through the N-type transistors 43 and 44 , respectively. N-type transistor 44 and P-type transistor 42 are connected in series, and P-type transistors 41 and 42 constitute a current mirror circuit. Therefore, a current whose value corresponds to output potential VO flows through P-type transistor 41 .

When the output potential VO is higher than the input potential VI, the current flowing in the P-type transistor 41 is larger than the current flowing in the N-type transistor 43, the potential V41 of the node N41 rises, and after the current flowing in the P-type transistor 46 decreases, the output potential VO decline. When the output potential VO is lower than the input potential VI, the current flowing in the P-type transistor 41 is smaller than the current flowing in the N-type transistor 43, the potential V41 of the node N41 drops, and after the current flowing in the P-type transistor 46 increases, the output potential VO rise. Therefore, VO=VI.

As shown in FIG. 6 , the pull-type driving circuit 32 includes a differential amplifier circuit 50 , a switch S4 , a constant current circuit 56 and an N-type transistor 57 . One terminal of the switch S4 receives the power supply potential VDD. The ON/OFF control of the switch S4 is performed in synchronization with the potentials VH, VL of the nodes N30, N31.

The differential amplifier circuit 50 includes a constant current circuit 51 , P-type transistors 52 and 53 and N-type transistors 54 and 55 . The constant current circuit 51 flows a constant current I1 of a predetermined value from the other terminal of the switch S4 to the node N51. P-type transistors 52 and 53 are respectively connected between node N51 and nodes N52 and N53, and their gates receive potential VI (V1d) of input node N55 and potential VO of output node N56, respectively. N-type transistors 54 and 55 are connected between nodes N52 and N53 and the ground potential GND line, respectively, and their gates are connected to node N53. N-type transistors 54 and 55 constitute a current mirror circuit. The constant current circuit 56 flows a constant current I2 of a predetermined value from the other terminal of the switch S4 to the output node N56. The N-type transistor 57 is connected between the output node N56 and the ground potential GND line, and its gate receives the potential V52 of the node N52. The value of the constant current I2 is set very small, thereby suppressing the through current in the drive circuit 32 to be very small.

When the switch S4 is in the off state, the power supply potential VDD is not supplied to the pull-type drive circuit 32 , and no power is consumed in the pull-type drive circuit 32 . When the switch S4 is in the open state, the pull-type drive circuit 32 is activated after the power supply potential VDD is provided to the pull-type drive circuit 32 . Currents having values corresponding to the input potential VI and the output potential VO flow through the P-type transistors 52 and 53 , respectively. The P-type transistor 53 and the N-type transistor 55 are connected in series, and the N-type transistors 54 and 55 constitute a current mirror circuit. Therefore, a current having a value corresponding to the output potential VO flows through the N-type transistor 54 .

When the output potential VO is higher than the input potential VI, the current flowing in the N-type transistor 54 is smaller than the current flowing in the P-type transistor 52, so that the potential V52 of the node N52 rises, and the current flowing in the N-type transistor 57 increases, thereby outputting Potential VO drops. When the output potential VO is lower than the input potential VI, the current flowing in the N-type transistor 54 is larger than the current flowing in the P-type transistor 52, so that the potential V52 of the node N52 drops, and the current flowing in the N-type transistor 57 decreases, thereby outputting The potential VO rises. Therefore, VO=VI.

Returning to FIG. 4 , the input nodes N45 and N55 of the drive circuits 31 and 32 both receive the gray level potential V1d, and their output nodes N46 and N56 are respectively connected to one terminal of the switches S1 and S2. The other terminals of the switches S1 and S2 are both connected to the output node of the current amplifying circuit 30.1. The switches S1, S2 are turned on/off simultaneously with the switches S3, S4 respectively. The structures of other current amplifying circuits 30.2-30.64 are also the same as those of the current amplifying circuit 30.1.

Before applying any one of the gray scale voltages V1d to V64d to the data line 6 described later, the data line 6 is precharged to a potential VPC=(VH+VL)/2 between the high potential VH and the low potential VL. The precharge potential VPC is a potential between V32d and V33d.

During the period when the high potential VH and the low potential VL are respectively applied to the nodes N30 and N31, the switches S2 and S4 of the current amplifying circuits 30.1 to 30.32 are turned on, and the output nodes of the current amplifying circuits 30.1 to 30.32 are respectively pulled down to gray levels At the same time, the switches S1 and S3 of the current amplifying circuits 30.33-30.64 are turned on, and the output nodes of the current amplifying circuits 30.33-30.64 are pulled up to the gray scale voltages V33d-V53d respectively. At this time, V64d>VPC>V1d.

During the period when the low potential VL and the high potential VH are respectively applied to the nodes N30 and N31, the switches S1 and S3 of the current amplifying circuits 30.1 to 30.32 are turned on, and the output nodes of the current amplifying circuits 30.1 to 30.32 are respectively pulled up to the gray scale At the same time, the switches S2 and S4 of the current amplifying circuits 30.33-30.64 are turned on, and the output nodes of the current amplifying circuits 30.33-30.64 are respectively pulled down to the gray-scale voltages V33d-V64d. At this time, V64d<VPC<V1d.

FIG. 7 is a structural circuit diagram of the equalizer+precharge circuit 26 shown in FIG. 3 . In FIG. 7 , the equalizer+precharge circuit 26 includes a switch S5 provided for each data line 6 and a switch S6 provided corresponding to every two adjacent data lines 6 . One terminal of the switch S5 receives the precharge potential VPC=(VH+VL)/2, and the other terminal is connected to the corresponding data line 6 . The precharge potential VPC can be imported from the outside or generated internally. The switch S5 is turned on in response to the precharge signal φPC changing to the “H” level of the active level. When the switch S5 is turned on, each data line 6 becomes the precharge potential VPC. The switch S6 is connected between the two data lines 6, and is turned on in response to the "H" level of the active level of the equalization signal φEQ. When the switch S6 is turned on, the potentials VG1 ˜ VGn of n data lines 6 (where n is an integer greater than or equal to 2) are averaged.

FIG. 8 is an operation time chart of the color liquid crystal display device shown in FIGS. 1 to 7 . In FIG. 8 , in the initial state, the equalization signal φEQ and the precharge signal φPC are at the inactive “L” level, and the switches S1 to S6 are turned off. At this time, the potentials VG1 to VGn of the n data lines 6 all become the potentials written in the previous period, and become any one of the potentials V1d to V64d. Then, the potential VS of the scanning line 4 becomes "L" level, and the N-type transistor 11 becomes non-conductive.

First, at time t0, when the equalization signal φEQ is at the “H” level of the active level, the switches S6 are turned on, and the n data lines 6 are short-circuited. Accordingly, potentials VG1 to VGn of n data lines 6 are averaged. The potential of each data line 6 at this time is determined by the potentials VG1 to VGn of the n data lines 6 at time t0, and is not a constant value. At time t1, when the equalization signal φEQ is at the inactive “L” level, each switch S6 is turned off, and the n data lines 6 are electrically disconnected from each other.

Next, at time t2, when the precharge signal φPC is at the “H” level of the active level, each switch S5 is turned on, and each data line 6 is at the precharge potential VPC. At time t3, when the precharge signal φP1 is at the active “L” level, each switch S5 is turned off, and the n data lines 6 are electrically disconnected from each other.

Next, at time t4, for example, high potential VH and low potential VL are respectively applied to nodes N30 and N31, switches S1 and S3 of current amplifying circuits 30.33 to 30.64 are turned on, and at the same time, switches of current amplifying circuits 30.1 to 30.32 S2 and S4 are turned on, and the potentials VG1 to VGn of the n data lines 6 all change to the output potential of the drive circuit 31 or 32 connected through the multiplexer 25 .

At this time, the data line 6 connected to any amplifying circuit in the current amplifying circuits 30.33-30.64 is rapidly charged through the P-type transistor 46 of the push-type driving circuit 31, and is connected to any amplifying circuit in the current amplifying circuits 30.1-30.32. The connected data line 6 is rapidly charged through the N-type transistor 57 of the pull-type driving circuit 32 .

Next, at time t5, the potential VS of one scanning line 4 rises to the "H" level of the selection level. Therefore, each N-type transistor 11 in FIG. 7 is turned on, and the potential VG of each data line 6 is supplied to the liquid crystal cell 2 through the N-type transistor 11 . When the potential VG of the scanning line 4 falls to “L” level, the N-type transistor 11 is turned off, and the voltage between the electrodes of the liquid crystal cell 2 is held by the capacitor 12 . The liquid crystal cell 2 exhibits a light transmittance of a value corresponding to the voltage between its electrodes.

In Embodiment 1, a push drive circuit 31, a pull drive circuit 32, and switches S1 and S2 are all provided in the current amplifying circuits 30.1 to 30.64, and the current amplifying circuit that outputs a potential higher than the precharge potential VPC (in FIG. 4 30.33 to 30.64), the switch S1 is turned on and only the push drive circuit 31 is used, and in the current amplification circuit (30.1 to 30.32 in FIG. Only the pull-type drive circuit 32 is used after being turned on. In the drive circuits 31 and 32 not connected to the data line 6, the supply of the power supply potential VDD is stopped after the switches S3 and S4 are turned off. Therefore, the through current in the current amplifying circuits 30.1 to 30.64 can be suppressed to the minimum, and the power consumption can be reduced.

In addition, the field effect transistors 11. 41-44, 46, 52-55, 57 can all be MOS transistors or thin film transistors (TFT). The thin film transistor may be formed using a semiconductor thin film such as a polysilicon thin film or an amorphous silicon thin film, or may be formed on an insulating substrate such as a resin substrate or a glass substrate.

FIG. 9 is a circuit diagram showing the configuration of a grayscale potential generating circuit of a color liquid crystal display device according to a modified example of Embodiment 1, and is a diagram for comparison with FIG. 4 . In FIG. 9, the gray level potential generating circuit includes two sets of ladder resistance circuits 60, 61 and 64 current amplification circuits 63.1-63.64. The resistance ladder circuit 60 includes resistance elements R1 to R65 connected in series between nodes N61 and N60. High potential VH and low potential VL are always applied to nodes N60 and N61, respectively. 64 grayscale voltages V1a to V64a are generated by the ladder resistance circuit 60 (V64a>V1a). The ladder resistance circuit includes resistance elements R1 to R65 connected in series between nodes N63 and N62. Low potential VL and high potential VH are always applied to nodes N62 and N63, respectively. 64 grayscale voltages V1b to V64b are generated by the ladder resistance circuit 61 (V64b<V1b).

The current amplifying circuits 63.1-63.64 all include the push-type driving circuit 31, the pull-type driving circuit 32 and the switches S1, S2 shown in Fig. 4- Fig. 6 . The input nodes of the push drive circuit 31 of the current amplifying circuits 63.33-63.64 respectively receive the output potentials V33a-V64a of the ladder resistance circuit 60, and the input nodes of the pull drive circuit 32 of the current amplification circuits 63.1-63.32 respectively receive the output potentials V33a-V64a of the ladder resistance circuit 60. Output potentials V1a-V32a, the input nodes of the pull drive circuit 32 of the current amplification circuits 63.33-63.64 receive the output potentials V33b-V64b of the ladder resistance circuit 61, and the input nodes of the push-type drive circuits 31 of the current amplification circuits 63.1-63.32 respectively receive Output potentials V1b to V32b of the ladder resistance circuit 61 . The output node of each push driving circuit 31 is connected to the output node of the corresponding current amplifying circuit through the switch S1, and the output node of each pulling driving circuit 32 is connected to the output node of the corresponding current amplifying circuit through the switch S2.

The switches S1 to S4 operate at the timings described in FIGS. 4 to 6 . In a certain cycle, as shown in Figure 9, the switches S1 and S3 of the current amplifying circuits 63.33 to 63.64 are turned on, and at the same time, the switches S2 and S4 of the current amplifying circuits 63.1 to 63.32 are turned on, and V64d> VPC>V1d. In the next cycle, the switches S2 and S4 of the current amplifying circuits 63.33-63.64 are turned on, and at the same time, the switches S1 and S3 of the current amplifying circuits 63.1-63.32 are turned on, V1d>VPC>V64d. Also in the modified example, the same effect as that of the first embodiment can be obtained.

FIG. 10 is a circuit diagram of a main part of an image display device according to a modified example of Embodiment 1, and is a diagram for comparison with FIG. 2 . In FIG. 10 , this modification replaces the liquid crystal cell 2 of FIG. 2 with a P-type transistor 65 and an EL (Electro Luminescence) element 66 . P-type transistor 65 and EL element 66 are connected in series between power supply potential VDD line and common potential line 5 , and the gate of P-type transistor 65 is connected to node N11 between N-type transistor 11 and capacitor 11 . When the gradation potential is supplied to the node N11, a current having a value corresponding to the gradation potential flows through the P-type transistor 65, and the EL element 66 emits light with a light intensity corresponding to the current value. In the EL element 66, it is not necessary to switch the polarity of the applied voltage as in the liquid crystal cell 2. Therefore, in the gray level potential generating circuit 24 in FIG. 4, the nodes N30 and N31 are respectively fixed at the high potential VH and the low potential VL, and the current amplifying circuits 30.1-30.32 only include the pull-type drive circuit 32, and the current amplifying circuits 30.33-30. 30.64 contains the push drive circuit 31 only. Also in this modified example, the same effect as that of the first embodiment can be obtained.

Example 2

In the push drive circuit 31 in FIG. 5, the output potential VO is directly fed back to the differential amplifier circuit 40, and there is a problem of resonance phenomenon due to the large load capacity. In Example 2, this problem was solved.

FIG. 11 is a structural circuit diagram of a push drive circuit 70 according to Embodiment 2 of the present invention.

In FIG. 11 , the push drive circuit 70 replaces the P-type transistor 46 of the push drive circuit 31 in FIG. 5 with a P-type transistor 71 , N-type transistors 72 , 73 and a constant current circuit 74 . In addition, in order to simplify the drawing and description, switches S3 and S4 for supplying power to the drive circuit will be omitted hereafter.

The P-type transistor 71, the N-type transistor 72, and the constant current circuit 74 are connected in series between the power supply potential VDD line and the ground potential GND line. The gate of the P-type transistor 71 receives the potential V41 of the output node N41 of the differential amplifier circuit 40 . The gate of the N-type transistor 72 is connected to its drain. The N-type transistor 72 constitutes a diode element. The potential VM of the source (node N72 ) of the N-type transistor 72 is supplied to the gate of the N-type transistor 44 . The constant current circuit 74 flows a constant current I3 of a predetermined value from the node N72 to the ground potential GND line. N-type transistor 73 is connected between the power supply potential VDD line and output node N46 , and its gate receives potential VC at node N71 between P-type transistors 71 and 72 .

Next, the operation of the drive circuit 70 will be described. In this drive circuit 70, due to the operation of the differential amplifier circuit 40, the potential VM of the node N72 is equal to the potential VI of the input node N45. That is, N-type transistor 44 and P-type transistor 42 are connected in series, and P-type transistors 41 and 42 constitute a current mirror circuit. Therefore, a current having a value corresponding to monitor potential VM flows through P-type transistor 41 .

When the monitor potential VM is higher than the input potential VI, the current flowing through the P-type transistor 41 is larger than the current flowing through the N-type transistor 43, and the potential V41 of the node N41 rises. Accordingly, the current flowing through the P-type transistor 71 decreases, and the monitor potential VM decreases. When the monitor potential VM is lower than the input potential VI, the current flowing in the P-type transistor 41 is smaller than the current flowing in the N-type transistor 43, and the potential V41 of the node N41 drops. Accordingly, the current flowing through the P-type transistor 71 increases, and the monitor potential VM rises. Therefore, VM=VI.

Since the current I3 of the constant current circuit 74 is set to a small value, the potential VC of the node N71 is VC=VM+VTN. Here, VTN is the threshold voltage of an N-type transistor. Moreover, when the current driving capability of the N-type transistor 73 is sufficiently greater than the current driving capability of the constant current circuit 74, the N-type transistor 73 performs a source follower operation, and the output potential VO of the output node N46 becomes VO=VC-VTN=VM =VI. Therefore, an output potential VO equal to the input potential VI is obtained.

In Embodiment 2, because the capacitance leading to the feedback loop of the differential amplifier circuit 40 is the gate capacitance of the N-type transistors 44, 72, 73, the load capacitance and the load capacitance are directly connected to the differential amplifier circuit 40. Compared with the drive circuit 31, the capacitance of the feedback loop leading to the differential amplifier circuit 40 is very small. Therefore, no resonance phenomenon occurs in the drive circuit 70 .

12A to 12C are circuit diagrams showing the structure of the constant current circuit 74 shown in FIG. 11 . In FIG. 12A , a constant current circuit 74 includes a resistance element 75 and N-type transistors 76 and 77 . The resistance element 75 and the N-type transistor 76 are connected in series between the power supply potential VDD line and the ground potential GND line, and the N-type transistor 77 is connected between the node N72 and the ground potential GND line. The gates of the N-type transistors 76 and 77 are both connected to the drain of the N-type transistor 76 . N-type transistors 76 and 77 constitute a current mirror circuit. A constant current having a value corresponding to the resistance value of the resistance element 75 flows through the resistance element 75 and the N-type transistor 76 . A constant current I3 having a value corresponding to the current flowing in the N-type transistor 76 flows through the N-type transistor 77 .

In FIG. 12B , the constant current circuit 74 includes an N-type transistor 78 . The N-type transistor 78 is connected between the node N72 and the ground potential GND line, and its gate receives a constant bias potential VBN. Bias potential VBN is set to a predetermined level at which N-type transistor 78 operates in a saturation region. Accordingly, a constant current I3 flows through the N-type transistor 78 .

In FIG. 12C , the constant current circuit 74 includes a depression-type N-type transistor 79 . The N-type transistor 79 is connected between the node N72 and the ground potential GND line, and its gate is connected to the ground potential GND line. The N-type transistor 79 is formed so that a constant current I3 flows even when the gate-source voltage is 0V. The constant current circuit 74 may also be constituted by a resistance element connected between the node N72 and the ground potential GND line. The structures of the constant current circuits 45 and 47 may also be the same as those of the constant current circuit 74 .

In the drive circuit 80 of FIG. 13 , the sources of the P-type transistors 41 and 42 and the source of the P-type transistor 71 and the drain of the transistor 73 are supplied with mutually different power supply potentials V1 , V2 , and V3 , respectively. The low potential side terminals of the constant current circuits 45, 74, 47 are respectively connected to different power supply potentials V4, V5, V6. Also in this modified example, the same effect as that of the drive circuit 70 of FIG. 11 can be obtained.

In the drive circuit 81 of FIG. 14 , the differential amplifier circuit 40 of the drive circuit 70 of FIG. 11 is replaced with a differential amplifier circuit 82 . The differential amplifier circuit 82 replaces the P-type transistors 41, 42 of the differential amplifier circuit 40 with resistance elements 83, 84, respectively. Resistive elements 83, 84 are connected between the power supply potential VDD line and nodes N41, N42, respectively.

The sum of the current flowing in the N-type transistor 43 and the current flowing in the N-type transistor 44 is equal to the current I1 flowing in the constant current circuit 45 . When the monitoring potential VM is equal to the input potential VI, the current flowing in the N-type transistor 43 and the current flowing in the N-type transistor 44 are equal. When the monitoring potential VM is higher than the input potential VI, the current of the N-type transistor 44 increases and the current of the N-type transistor 43 decreases. After the potential V41 of the node N41 rises, the current of the P-type transistor 71 decreases and the monitoring potential VM decreases. When the monitoring potential VM is lower than the input potential VI, the current of the N-type transistor 44 decreases and the current of the N-type transistor 43 increases. After the potential V41 of the node N41 drops, the current of the P-type transistor 71 increases and the monitoring potential VM rises. Therefore, monitor potential VM is kept at the same level as input potential VI, and VI=VO. Also in this modified example, the same effect as that of the drive circuit 70 of FIG. 11 can be obtained.

Example 3

FIG. 15 is a structural circuit diagram of a push drive circuit 85 according to Embodiment 3 of the invention. In Fig. 15, the driving circuit 85 replaces the differential amplifying circuit 40 of the driving circuit 80 of Fig. 11 with the differential amplifying circuit 50 of Fig. 6, and replaces the P-type transistor 71 and Constant current circuit 74. The constant current circuit 86 is connected between the power supply potential VDD line and the node N71, and flows a constant current I3 of a predetermined value from the power supply potential VDD line to the node N71. The N-type transistor 87 is connected between the node N72 and the ground potential GND line, and its gate receives the potential V52 of the output node N52 of the differential amplifier circuit 50 .

Next, the operation of the drive circuit 85 will be described. In the drive circuit 85, the monitor potential VM is equal to the input potential VI due to the operation of the differential amplifier circuit 50. That is, the P-type transistor 53 and the N-type transistor 55 are connected in series, and the N-type transistors 54 and 55 constitute a current mirror circuit. Therefore, a current having a value corresponding to the monitor potential VM flows through the N-type transistor 54 .

When the monitor potential VM is higher than the input potential VI, the current flowing in the N-type transistor 54 is smaller than the current flowing in the P-type transistor 52, and the potential V52 of the node N52 rises. Accordingly, the current flowing through the N-type transistor 87 increases, and the monitor potential VM decreases. When the monitor potential VM is lower than the input potential VI, the current flowing through the N-type transistor 54 is larger than the current flowing through the P-type transistor 52, and the potential V52 of the node N52 drops. Accordingly, the current flowing through the N-type transistor 87 becomes smaller, and the monitor potential VM rises. Therefore, VM=VI.

The current I3 of the constant current circuit 86 is set to a sufficiently small value, and therefore, the potential VC of the node N71 becomes VC=VM+VTN. When the current driving capability of the N-type transistor 73 is sufficiently larger than that of the constant current circuit 47, the N-type transistor 73 operates as a source follower, and the potential VO of the output node N46 becomes VO=VC-VTN=VM=VI. Therefore, an output potential VO of a level equal to the input potential VI is obtained.

In Embodiment 3, the capacitance leading to the feedback loop of the differential amplifier circuit 50 is used as the gate capacitance of the transistors 53, 72, 73, therefore, the drive circuit 31 of FIG. 5 that is directly connected to the differential amplifier circuit 40 with the load capacitance In comparison, the capacitance of the feedback loop to the differential amplifier circuit 50 becomes very small. Therefore, no resonance phenomenon occurs in the drive circuit 85 .

16A to 16C are circuit diagrams showing the configuration of the constant current circuit 86 shown in FIG. 15 . In FIG. 16A , a constant current circuit 86 includes P-type transistors 88 and 89 and a resistance element 90 . The P-type transistor 88 and the resistance element 90 are connected in series between the power supply potential VDD line and the ground potential GND line, and the P-type transistor 89 is connected between the power supply potential VDD line and the node N71. The gates of the P-type transistors 88 and 89 are both connected to the drain of the P-type transistor 88 . P-type transistors 88, 89 constitute a current mirror circuit. A constant current having a value corresponding to the resistance value of the resistance element 90 flows through the P-type transistor 88 and the resistance element 89 . A constant current I3 having a value corresponding to the current flowing in the P-type transistor 88 flows through the P-type transistor 89 .

In FIG. 16B , the constant current circuit 86 includes a P-type transistor 91 . The P-type transistor 91 is connected between the power supply potential VDD line and the node N71, and its gate receives a constant bias potential VBP. Bias potential VBP is set to a predetermined level at which P-type transistor 91 operates in a saturation region. Accordingly, a constant current I3 flows through the P-type transistor 91 .

In FIG. 16C , the constant current circuit 86 includes a pump-down P-type transistor 92 . The P-type transistor 92 is connected between the power supply potential VDD line and the node N71, and its gate is connected to the power supply potential VDD line. The P-type transistor 92 is formed so that a constant current I3 flows even when the gate-source voltage is 0V. The constant current circuit 86 may also be constituted by a resistance element connected between the power supply potential VDD line and the node N71. The structure of the constant current circuit 51 may also be the same as that of the constant current circuit 86 .

In the drive circuit 95 of FIG. 17 , the differential amplifier circuit 50 of the drive circuit 85 of FIG. 15 is replaced with a differential amplifier circuit 96 . In the differential amplifier circuit 96 , the N-type transistors 54 and 55 of the differential amplifier circuit 50 are replaced with resistor elements 97 and 98 . Resistive elements 97, 98 are connected between nodes N52, 53 and the ground potential GND line, respectively. The sum of the current flowing in the P-type transistor 52 and the current flowing in the P-type transistor 53 is equal to the current I1 flowing in the constant current circuit 51 . When the monitoring potential VM is equal to the input potential VI, the current of the P-type transistor 52 is equal to the current of the P-type transistor 53 . When the monitoring potential VM is higher than the input potential VI, the current of the P-type transistor 53 decreases, while the current of the P-type transistor 52 increases. After the potential V52 of the node N52 rises, the current of the N-type transistor 87 increases, and the monitoring potential VM decreases. When the monitoring potential VM is lower than the input potential VI, the current of the P-type transistor 53 increases and the current of the P-type transistor 52 decreases. After the potential V52 of the node N52 decreases, the current of the N-type transistor 87 decreases and the monitoring potential VM increases. Therefore, monitor potential VM remains at input potential VI, and VO=VI. Also in this modified example, the same effect as that of the drive circuit 85 of FIG. 15 can be obtained.

In the drive circuit 100 of FIG. 18 , the differential amplifier circuit 50 of the drive circuit 85 of FIG. 15 is replaced with the differential amplifier circuit 40 of FIG. 5 . The gate of the N-type transistor 87 receives the potential V41 of the node N41, and the gate of the N-type transistor 44 receives the monitor potential VM. When the monitoring potential VM is higher than the input potential VI, the current flowing through the P-type transistor 41 is larger than the current flowing through the N-type transistor 43, the potential V41 of the node N41 increases, the current of the N-type transistor 87 increases, and the monitoring potential VM decreases. When the monitoring potential VM is lower than the input potential VI, the current flowing in the P-type transistor 41 is smaller than the current flowing in the N-type transistor 43, the potential V41 of the node N41 decreases, the current of the N-type transistor 87 decreases, and the monitoring potential VM increases. Therefore, VM=VI, VO=VI. Also in this modified example, the same effect as that of the drive circuit 85 of FIG. 15 can be obtained.

Example 4

FIG. 19 is a structural circuit diagram of a pull-type driving circuit 105 according to Embodiment 4 of the present invention, which is a diagram for comparison with FIG. 6 . In FIG. 19 , the drive circuit 105 uses P-type transistors 106 to 108 and a constant current circuit 109 instead of the N-type transistor 57 of the drive circuit 32 in FIG. 6 . In addition, below, in order to simplify drawing and description, the switch S4 for power supply is abbreviate|omitted.

The P-type transistors 106 and 107 and the constant current circuit 109 are connected in series between the power supply potential VDD line and the ground potential GND line. The gate of the P-type transistor 106 receives the potential V52 of the node N52. The gate of the P-type transistor 53 receives the potential VM of the node N106 between the P-type transistors 106 and 107 . The gate of the P-type transistor 107 is connected to its drain (node N107). The P-type transistor 107 constitutes a diode element. The constant current circuit 109 flows a constant current I3 of a predetermined value from the node N107 to the ground potential GND line. The P-type transistor 108 is connected between the output node N56 and the ground potential GND line, and its gate receives the potential VC of the node N107.

The monitor potential VM is maintained at the input potential VI by the operation of the differential amplifier circuit 50 . That is, when the monitor potential VM is higher than the input potential VI, the current of the N-type transistor 54 is smaller than the current of the P-type transistor 52, the potential V52 of the node N52 rises, and after the current flowing through the P-type transistor 106 decreases, the monitor potential VM falls. When the monitoring potential VM is lower than the input potential VI, the current of the N-type transistor 54 is larger than the current of the P-type transistor 52, the potential V52 of the node N52 drops, and after the current flowing through the P-type transistor 106 increases, the monitoring potential VM rises. Therefore, VM=VI.

When the current drive capability of the P-type transistor 107 is sufficiently greater than the constant current I3 of the constant current circuit 109, the potential VC of the node N107 becomes VC=VM−|VTP|. Here, VTP is the threshold voltage of the P-type transistor. When the current driving capability of the P-type transistor 108 is sufficiently greater than the constant current I2 of the constant current circuit 56, the output potential VO becomes VO=VC+|VTP|=VM-|VTM|+|VTP|=VM=VI.

In Embodiment 4, the capacitance leading to the feedback loop of the differential amplifier circuit 50 is used as the gate capacitance of the transistors 53, 107, and 108. Therefore, the drive circuit 32 of FIG. Compared with that, the capacitance of the feedback loop leading to the differential amplifier circuit 50 is very small. Therefore, no resonance phenomenon occurs in the drive circuit 105 .

The drive circuit 110 of FIG. 20 replaces the P-type transistor 106 and the constant current circuit 109 of the drive circuit 105 of FIG. 19 with a constant current circuit 111 and an N-type transistor 112, respectively. The constant current circuit 111 flows a constant current I3 of a predetermined value from the power supply potential VDD line to the node N106. The N-type transistor 112 is connected between the node N107 and the ground potential GND line, and its gate receives the potential V52 of the node N52. When the monitor potential VM is higher than the input potential VI, the potential V52 of the node N52 rises, the current flowing into the N-type transistor 112 increases, and the monitor potential VM falls. When the monitor potential VM is lower than the input potential VI, the potential V52 of the node N52 falls, the current flowing into the N-type transistor 112 decreases, and the monitor potential VM rises. Therefore, VM=VI, VO=VI. Also in this modified example, the same effect as that of the drive circuit 105 of FIG. 10 can be obtained.

The drive circuit 115 of FIG. 21 replaces the differential amplifier circuit 50 of the drive circuit 105 of FIG. 19 with the differential amplifier circuit 40 of FIG. 5 . When the monitor potential VM is higher than the input potential VI, the potential V41 of the node N41 rises, the current flowing into the P-type transistor 106 decreases, and the monitor potential VM falls. When the monitor potential VM is lower than the input potential VI, the potential V41 of the node N41 falls, the current flowing into the P-type transistor 106 increases, and the monitor potential VM rises. Therefore, VM=VI, VO=VI. Also in this modified example, the same effect as that of the drive circuit 105 of FIG. 19 can be obtained.

Example 5

FIG. 22 is a structural circuit diagram of a push-pull drive circuit 120 according to Embodiment 5 of the present invention. In FIG. 22 , the drive circuit 120 is a combination of the push drive circuit 70 of FIG. 11 and the pull drive circuit 110 of FIG. 20 . The input node N45 of the push drive circuit 70 and the input node of the pull drive circuit 110 are connected to each other, and the output node N46 of the push drive circuit 70 and the output node of the pull drive circuit 110 are connected to each other.

When the output potential VO is higher than the input potential VI, the gate-source voltage of the N-type transistor 73 is less than the threshold voltage VTN of the N-type transistor 73, the N-type transistor 73 becomes non-conductive, and at the same time, the source-gate voltage of the P-type transistor 108 If the voltage between them is greater than the absolute value of the threshold voltage VTP of the P-type transistor 108, the P-type transistor 108 is turned on, and the output potential VO drops.

When the output potential VO is lower than the input potential VI, the source-gate voltage of the P-type transistor 108 is less than the absolute value of the threshold voltage VTP of the P-type transistor 108, the P-type transistor 108 becomes non-conductive, and at the same time, the N-type transistor 73 The gate-source voltage is greater than the threshold voltage VTN of the N-type transistor 73, the N-type transistor 73 is turned on, and the output potential VO rises. Therefore, VO=VI.

The drive circuit 120 is used as the push drive circuit 31 or the pull drive circuit 32 of FIGS. 4 and 5 . When the drive circuit 120 is used as the push drive circuit 31 , the current drive capability of the discharge P-type transistor 108 is set to be sufficiently smaller than the current drive capability of the charge N-type transistor 73 . When the drive circuit 120 is used as the pull drive circuit 32 , the current drive capability of the charge N-type transistor 73 is set to be sufficiently smaller than the current drive capability of the discharge P-type transistor 108 . Therefore, the through current in the drive circuits 31 and 32 can be reduced, and the power consumption can be reduced.

In Example 5, in addition to the same effects as in Example 2, power consumption can be reduced.

Various modifications will be described below. The push-pull drive circuit 125 of FIG. 23 is a combination of the push-type drive circuit 85 of FIG. 15 and the pull-type drive circuit 115 of FIG. 21 . The input node N45 of the push drive circuit 85 and the input node of the pull drive circuit 115 are connected to each other, and the output node N46 of the push drive circuit 85 and the output node of the pull drive circuit 115 are connected to each other. Also in this modified example, the same effect as that of the drive circuit 120 of FIG. 22 can be obtained.

The push-pull drive circuit 130 of FIG. 24 is a combination of the push-type drive circuit 70 of FIG. 11 and the pull-type drive circuit 115 of FIG. 21 . The push-pull drive circuit 131 of FIG. 25 is a combination of the push-type drive circuit 85 of FIG. 15 and the pull-type drive circuit 110 of FIG. 20 . Also in these modified examples, the same effect as that of the drive circuit 120 of FIG. 22 can be obtained. In addition, any one of the push-pull drive circuits 120, 125, 130, 131 can omit one or both of the constant current circuits 47, 56.

Example 6

FIG. 26 is a structural circuit diagram of a push-pull drive circuit 135 according to Embodiment 6 of the present invention. Referring to FIG. 26 , the drive circuit 135 has P-type transistors 136 and 137 added to the push drive circuit 70 of FIG. 11 . The P-type transistor 136 and the constant current circuit 74 are connected in series between the node N72 and the ground potential GND line, and the gate of the P-type transistor 136 is connected to the drain (node N136 ). The P-type transistor 136 constitutes a diode element. The P-type transistor 137 is connected between the output node N46 and the ground potential GND line, and its gate receives the potential VC1 of the node N136.

By the operation of the differential amplifier circuit 40, the potential VM of the node N72 becomes VM=VI. Therefore, the potential VC of the node N71 becomes VC=VI+VTN, and the potential VC1 of the node N136 becomes VC1=VI-|VTP|. When the output potential VO is higher than the input potential VI, the N-type transistor 73 becomes non-conductive, and at the same time, the P-type transistor 137 is conductive. When the output potential VO is lower than the input potential VI, the P-type transistor 137 becomes non-conductive, and at the same time, the P-type transistor 73 is conductive. Therefore, VO=VI.

In Embodiment 6, in addition to obtaining the same effects as in Embodiment 5, the design area can be reduced because only one differential amplifier circuit is used.

Example 7

FIG. 27 is a structural circuit diagram of a push-pull drive circuit 140 according to Embodiment 7 of the present invention. Referring to FIG. 27 , the drive circuit 140 has N-type transistors 141 and 142 added to the pull drive circuit 110 of FIG. 20 . The constant current circuit 111 and the N-type transistor 141 are connected in series between the power supply potential VDD line and the node N106, and the gate of the N-type transistor 141 is connected to its drain (node N111). The N-type transistor 141 constitutes a diode element. The N-type transistor 142 is connected between the power supply potential VDD line and the output node N56, and its gate receives the potential VC1 of the node N111.

By the operation of the differential amplifier circuit 50, the potential VM of the node N106 becomes VM=VI. Therefore, the potential VC1 of the node N111 becomes VC1=VI+VTN, and the potential VC of the node N107 becomes VC=VI-|VTP|. When the output potential VO is higher than the input potential VI, the N-type transistor 142 becomes non-conductive, and at the same time, the P-type transistor 108 is conductive. When the output potential VO is lower than the input potential VI, the P-type transistor 108 becomes non-conductive, and at the same time, the N-type transistor 142 is conductive. Therefore, VO=VI.

Also in Example 7, the same effect as that of Example 6 can be obtained.

In addition, the constant current circuit 56 may be omitted.

Example 8

FIG. 28 is a structural circuit diagram of a push drive circuit 150 according to Embodiment 8 of the present invention. In FIG. 28 , the drive circuit 150 includes a level shift circuit 151 , a pull-up circuit 155 and a constant current circuit 158 .

The level shift circuit 151 includes a constant current circuit 152 , an N-type transistor 153 , and a P-type transistor 154 connected in series between a node of a power supply potential V11 (15V) and a node of a ground potential GND. The gate of the N-type transistor 153 is connected to its drain (node N152). The N-type transistor 153 constitutes a diode element. The gate of the P-type transistor 154 receives the potential VI of the input node N45. The current driving capability of the constant current circuit 152 is set to a level sufficiently smaller than the current driving capabilities of the transistors 153 and 154 .

The potential V153 of the source (node N153 ) of the P-type transistor 154 is V153=VI+|VTP|, and the potential V152 of the drain (node N152 ) of the N-type transistor 153 is V152=VI+|VTP|+VTN. Therefore, the level shift circuit 151 outputs a potential V152 in which the level of the input potential VI is shifted by |VTP|+VTN.

Pull-up circuit 155 includes N-type transistor 156 and P-type transistor 157 connected in series between the node of power supply potential V12 (15V) and output node N46. The constant current circuit 158 is connected between the output node N46 and the ground potential GND line. The gate of the N-type transistor 156 receives the output potential V152 of the level shift circuit 151 . The gate of the P-type transistor 157 is connected to its drain. The P-type transistor 157 constitutes a diode element. Since the power supply potential V12 is set such that the N-type transistor 156 operates in a saturation region, the N-type transistor 156 performs a so-called source follower operation. The current driving capability of the constant current circuit 158 is set to a level sufficiently smaller than the current driving capabilities of the transistors 156 and 157 .

The potential V156 of the source (node N156) of the N-type transistor 156 becomes V156=V152-VTN=VI+|VTP|. The potential VO of the output node N46 becomes VO=V156-|VTP|=VI.

In Embodiment 8, no resonance phenomenon occurs in the drive circuit 150 because the output potential VO is not completely fed back.

Example 9

FIG. 29 is a structural circuit diagram of a pull-type driving circuit 160 according to Embodiment 9 of the present invention. In FIG. 29 , the drive circuit 160 includes a level shift circuit 161 , a constant current circuit 165 and a pull-down circuit 166 .

The level shift circuit 161 includes an N-type transistor 162 , a P-type transistor 163 , and a constant current circuit 164 connected in series between a node of a power supply potential V13 (5 V) and a node of a power supply potential V14 (−10 V). The gate of the N-type transistor 162 receives the potential of the input node N55. The gate of the P-type transistor 163 is connected to its drain (node N163). The P-type transistor 163 constitutes a diode element. The current driving capability of the constant current circuit 164 is set to a level sufficiently smaller than the current driving capabilities of the transistors 162 and 163 .

The potential V162 of the source (node N162) of the N-type transistor 162 becomes V162=VI-VTN. The potential V163 of the drain (node N163) of the P-type transistor 163 becomes V163=VI-VTN-|VTP|. Therefore, the level shift circuit 161 outputs a potential V163 in which the input potential VI is level-shifted by -VTN-|VTP|.

The constant current circuit 165 is connected between the node of the power supply potential V13 and the output node N56. Pull-down circuit 166 includes P-type transistor 168 and N-type transistor 167 connected in series between a node of power supply potential V15 (−10V) and output node N166 . The gate of the P-type transistor 168 receives the output potential V163 of the level shift circuit 161 . The gate of the N-type transistor 167 is connected to its drain. The N-type transistor 167 constitutes a diode element. Since the power supply potential V15 is set such that the P-type transistor 168 operates in a saturation region, the P-type transistor 168 performs a so-called source follower operation. The current driving capability of the constant current circuit 165 is set to a level sufficiently smaller than the current driving capabilities of the transistors 167 and 168 .

The potential V167 of the source (node N167) of the P-type transistor 168 becomes V167=V163+|VTP|=VI-VTN. The potential VO of the output node N56 becomes VO=V167+VTN=VI.

In Example 9, the same effect as in Example 8 was obtained.

Example 10

FIG. 30 is a structural circuit diagram of a push-pull drive circuit 170 according to Embodiment 10 of the present invention. In FIG. 30 , the drive circuit 170 is a combination of the push drive circuit 150 of FIG. 28 and the pull drive circuit 160 of FIG. 29 . The gate of the P-type transistor 154 of the level shift circuit 151 and the gate of the N-type transistor 162 of the level shift circuit 161 receive the potential VI of the input node N171. The drain of the P-type transistor 157 of the pull-up circuit 155 and the drain of the N-type transistor 167 of the pull-down circuit 166 are connected to the output node N172.

When the output potential VO is higher than the input potential VI, the transistors 156 and 157 of the pull-up circuit 155 are turned off, and the transistors 167 and 168 of the pull-down circuit 166 are turned on, so that the output potential VO drops. When the output potential VO is lower than the input potential VI, the transistors 167 and 168 of the pull-down circuit 166 become non-conductive, and at the same time, the transistors 156 and 157 of the pull-up circuit 155 are conductive, and the output potential VO rises. Therefore, VO=VI.

The drive circuit 170 is used as the push drive circuit 31 or the pull drive circuit 32 of FIGS. 4 and 5 . When drive circuit 170 is used as push drive circuit 31 , the current drive capability of transistors 167 and 168 of pull-down circuit 166 is set to be sufficiently smaller than the current drive capability of transistors 156 and 157 of pull-up circuit 155 . When the drive circuit 170 is used as the pull-type drive circuit 32 , the current drive capability of the transistors 156 and 157 of the pull-up circuit 155 is set to be sufficiently smaller than the current drive capability of the transistors 167 and 168 of the pull-down circuit 166 . Therefore, the through current in the drive circuits 31 and 32 can be reduced, and the power consumption can be reduced.

In Example 10, in addition to obtaining the same effects as in Example 8, power consumption can be reduced.

FIG. 31 is a circuit diagram showing the configuration of a push-pull drive circuit 175 according to a modification of Embodiment 10. FIG. In FIG. 31 , the push-pull drive circuit 175 replaces the level shift circuits 151 and 152 of the push-pull drive circuit 170 of FIG. 30 with level shift circuits 176 and 178 , respectively. The level shift circuit 176 replaces the constant current circuit 152 of the level shift circuit 151 with a resistance element 177 . The level shift circuit 178 replaces the constant current circuit 164 of the level shift circuit 161 with a resistance element 179 . The resistance value of the resistance elements 177 and 179 is set to a value at which a current of the same level as that of the constant current circuits 152 and 164 flows through the resistance elements 177 and 179 . Also in this modified example, the same effect as that of the push-pull drive circuit 170 of FIG. 30 can be obtained.

Furthermore, in the push-pull type drive circuits 170, 175, one or both of the constant current circuits 158, 165 may be omitted.

Example 11

FIG. 32 is a structural circuit diagram of a push drive circuit 180 with offset compensation function according to Embodiment 11 of the present invention. In FIG. 32 , a push drive circuit 180 with an offset compensation function includes a drive circuit 70 , a capacitor 181 and switches S11 to S13 . The driving circuit 70 is the same as that shown in FIG. 11 . When the capacitor 181 and the switches S11 to S13 generate a potential difference between the input potential VI and the output potential VO of the drive circuit 70, that is, an offset voltage VOF due to variations in the threshold voltages of the transistors of the drive circuit 70, etc., they are configured to compensate for the offset. Offset compensation circuit for voltage VOF.

That is, the switch S11 is connected between the input node N45 and the gate of the N-type transistor 43 . The capacitor 181 and the switch S12 are connected in series between the gate of the N-type transistor 43 and the output node N45, and the switch S13 is connected between the input node N45 and a node between the capacitor 181 and the switch S12. The switches S11 - S13 may all be P-type transistors, may also be N-type transistors, or may be P-type transistors and N-type transistors connected in parallel. The switches S11 to S13 are all on/off controlled by a control signal (not shown).

Now, only the case where the output potential VO of the drive circuit 1 is lower than the input potential VI by the offset voltage VOF will be described. Referring to FIG. 33 , in the initial state, all the switches S11 - S13 are in the off state. When the switches S11 and S12 are turned on at a certain time t1, the output potential VO becomes VO=VI−VOF, and the capacitor 181 is charged to the offset voltage VOF.

Next, at time t2, when the switches S11 and S12 are turned off, the offset voltage VOF is held in the capacitor 181 . Next, at time t3, when the switch S13 is turned on, the gate potential V43 of the N-type transistor 43 becomes VI+VOF. As a result, the output potential VO of the driving circuit 70 becomes VO=VI+VOF−VOF=VI, and the offset voltage VOF of the driving circuit 70 is canceled out.

In the eleventh embodiment, the offset voltage VOF of the drive circuit 70 can be canceled, and the output potential VO and the input potential VI can be matched more accurately.

In addition, in the eleventh embodiment, the case of canceling the offset voltage VOF of the driving circuit 70 has been described, but of course, the same method can be used to cancel the driving circuits 31, 32, 80, 81, 85, 95, 100, 105, 110, 115, 135, 140, 150, 160 offset voltage VOF.

As shown in FIG. 34 , the operation of compensating the offset voltage VOF can be performed during a blanking period, which is: from the potential VSi of the i-th (where i is an integer greater than or equal to 1) scan line 4 from The "H" level falls to the "L" level until the potential VSi+1 of the i+1-th scanning line 4 rises from the "L" level to the "H" level. Alternatively, the operation of compensating the offset voltage VOF may be performed during a blanking period between two frames. If the operation of compensating the offset voltage VOF is performed during the blanking period, the image display frequency does not drop due to this operation.

Example 12

FIG. 35 is a structural circuit diagram of a push-pull drive circuit 185 with offset compensation function according to Embodiment 12 of the present invention. In FIG. 35 , the driving circuit 185 includes the driving circuit 120 shown in FIG. 22 , capacitors 186 a and 186 b , and switches S11 a to S14 a and S11 b to S14 b.

The switches S11a, S11b are connected between the input node N45 and the gates of the N-type transistors 43, 52 of the drive circuits 70, 115, respectively. The capacitor 186 a and the switch S12 a are connected in series between the gate of the N-type transistor 43 and the source of the N-type transistor 73 (node N73 ) of the drive circuit 70 . The capacitor 186b and the switch S12b are connected in series between the gate of the P-type transistor 52 and the source of the P-type transistor 108 (node N56 ) of the drive circuit 110 . The switch S13a is connected between the input node N45 and the node between the capacitor 186a and the switch S12a. The switch S13b is connected between the input node N45 and the node between the capacitor 186b and the switch S12b. The switches S14a, S14b are connected between the nodes N73, N56 and the output node N46, respectively.

Next, the operation of the drive circuit 185 will be described. In the initial state, all the switches S11a-S14a, S11b-S14b are in the off state. At a certain moment, when the switches S11a, S12a, S11b, and S12b are turned on, the potentials V73, V56 of the nodes N73, N56 become V73=VI-VOFa, V56=VI-VOFb respectively, and the capacitors 186a, 186b are respectively Charge to the offset voltage VOFa, VOFb.

Next, when the switches S11a, S12a, S11b, and S12b are turned off, the offset voltages VOFa, VOFb are held in the capacitors 186a, 186b, respectively. Next, when the switches S13a and S13b are turned on, the gate potentials of the N-type transistors 43 and 52 of the drive circuits 70 and 110 become VI+VOFa and VI+VOFb, respectively. As a result, the output potentials V73 and V56 of the driving circuits 70 and 110 become V73=VI+VOFa-VOFa=VI and V56=VI+VOFb-VOFb=VI respectively, and the offset voltages VOFa and VOFb of the driving circuits 70 and 110 are canceled out. . Finally, the switches S14a and S14b are turned on, and VO=VI.

The drive circuit 185 is used as the push drive circuit 31 or the pull drive circuit 32 of FIGS. 4 and 5 . When drive circuit 185 is used as push drive circuit 31 , the current drive capability of discharge P-type transistor 108 is set to a level sufficiently smaller than the current drive capability of charge N-type transistor 73 . When the drive circuit 185 is used as the pull drive circuit 32 , the current drive capability of the charging N-type transistor 73 is set to be sufficiently smaller than the current drive capability of the discharging P-type transistor 108 . Therefore, the through current in the drive circuits 31 and 32 can be reduced, and the power consumption can be reduced.

In Example 12, a drive circuit 185 having no offset voltage and having low power consumption was obtained.

Example 13

FIG. 36 is a structural circuit block diagram of a drive circuit 190 with offset compensation function according to Embodiment 13 of the present invention. In FIG. 36 , a drive circuit 190 with an offset compensation function has capacitors 191 a and 191 b and switches S11 a to S14 a and S11 b to S14 b added to the drive circuit 170 of FIG. 30 .

The switches S11a, S11b are connected between the input node N190 and the gates of the transistors 154, 162 (nodes N171a, N171b), respectively. The switches S14a, S14b are connected between the output node N191 and the drains (nodes N172a, N172b) of the transistors 157, 167, respectively. The capacitor 191a and the switch S12a are connected in series between the nodes N171a and N172a. The capacitor 191b and the switch S12b are connected in series between the nodes N171b and N172b. The switch S13a is connected between the input node N190 and the node N191a between the capacitor 191a and the switch S12a. The switch S13b is connected between the input node N190 and the node N191b between the capacitor 191b and the switch S12b.

Next, the operation of the drive circuit 190 will be described. In the initial state, all the switches S11a-S14a, S11b-S14b are in the off state. At a certain time, when the switches S11a, S12a, S11b, and S12b are turned on, the potentials V172a, V172b of the nodes N172a, N172b become V172a=VI-VOFa, V172b=VI-VOFb respectively, and the capacitors 191a, 191b are respectively Charge to the offset voltage VOFa, VOFb.

Next, when the switches S11a, S12a, S11b, and S12b are turned off, the offset voltages VOFa, VOFb are held in the capacitors 191a, 191b, respectively. Next, when the switches S13a and S13b are turned on, the gate potentials of the transistors 154 and 162 become VI+VOFa and VI+VOFb, respectively. As a result, the potentials V172a, V172b of the nodes N172a, N172b respectively become V172a=VI+VOFa-VOFa=VI, V172b=VI+VOFb-VOFb=VI, and the offset voltages VOFa, VOFb of the driving circuit 170 are canceled. Finally, the switches S14a and S14b are turned on, and VO=VI.

The drive circuit 190 is used as the push drive circuit 31 or the pull drive circuit 32 of FIGS. 4 and 5 . When the drive circuit 190 is used as the push drive circuit 31 , the current drive capabilities of the transistors 167 and 168 are set to a level sufficiently smaller than the current drive capabilities of the transistors 156 and 157 . When the drive circuit 190 is used as the pull-type drive circuit 32 , the current drive capabilities of the transistors 156 and 157 are set to be sufficiently smaller than the current drive capabilities of the transistors 167 and 168 . Therefore, the through current in the drive circuits 31 and 32 can be reduced, and the power consumption can be reduced.

In Example 13, a drive circuit 190 with no offset voltage and low power consumption was obtained.

All embodiments disclosed herein are illustrative and not restrictive. The scope of the present invention is shown by the claims not described above, and includes all changes within the claims and the scope equivalent to the claims.

Claims (20)

1. An image display device, displaying an image according to an image signal (D0～D5), comprising: A plurality of pixel display elements (2, 11, 12), arranged in multiple rows and multiple columns, respectively perform gray scale display according to the applied gray scale potential; A plurality of scanning lines (4), respectively set correspondingly to the above-mentioned plurality of lines; A plurality of data lines (6) are respectively set correspondingly to the above-mentioned plurality of columns; The vertical scanning circuit (7) sequentially selects from the plurality of scanning lines (4) at regular intervals, and activates each pixel display element (2, 11, 12) corresponding to the selected scanning line (4); and The horizontal scanning circuit (8) supplies the gray scale potential to each pixel display element (D0-D5) activated by the above-mentioned vertical scanning circuit (7) according to the above-mentioned image signal (D0-D5), Wherein the above-mentioned horizontal scanning circuit (8) comprises: A pre-charging circuit (26), making each data line (6) reach a predetermined pre-charging potential (VPC); A potential generating circuit (R1-R65), which generates a plurality of gray-scale potentials (V1d-V64d) different from each other; The first current amplifying circuit (31) is set corresponding to each gray-scale potential higher than the above-mentioned pre-charge potential (VPC) among the above-mentioned multiple gray-scale potentials (V1d-V64d), and outputs a potential equal to the corresponding gray-scale potential , the charging capacity is higher than the discharging capacity; The second current amplifying circuit (32) is set corresponding to each gray-scale potential lower than the above-mentioned pre-charge potential (VPC) among the above-mentioned multiple gray-scale potentials (V1d-V64d), and outputs a potential equal to the corresponding gray-scale potential , the discharge capacity is higher than the charge capacity; The selection circuit (25) selects any one of the above-mentioned multiple gray-scale potentials (V1d-V64d) according to the above-mentioned image signals (D0-D5), and transmits the corresponding selected gray-scale potential through each data line (6). The output potential of the above-mentioned first or second current amplifying circuit (31 or 32) of the gray scale potential is supplied to each activated pixel display element (2, 11, 12). 2. The image display device according to claim 1, wherein Above-mentioned first current amplifying circuit (31) comprises: a first transistor (46), connected between the first power supply potential (VDD) line and the first output node (N46), and causes current to flow into the first output node (N46); The first current limiting element (47), connected between the first output node (N46) and the second power supply potential (GND) line, has a current driving capability smaller than that of the first transistor (46), causing current to flow from said first output node (N46); and A first control circuit (40), controlling the gate potential of the first transistor (46), so that the potential (VO) of the first output node (N46) is consistent with the corresponding gray level potential (VI); Above-mentioned second current amplifying circuit (32) comprises: The second current limiting element (56) is connected between the third power supply potential (VDD) line and the second output node (N56), so that current flows into the second output node (N56); The second transistor (57), connected between the second output node (N56) and the fourth power supply potential (GND) line, has a current driving capability greater than that of the second current limiting element (56), causing current to flow from said second output node (N56); and The second control circuit (50) controls the gate potential of the second transistor (57), so that the potential (VO) of the second output node (N56) is consistent with the corresponding gray scale voltage (VI). 3. The image display device according to claim 2, wherein said first control circuit (40, 71, 72, 74) comprises: A third transistor (71) connected between the fifth power supply potential (VDD) line and the gate electrode of the above-mentioned first transistor (73); a fourth transistor (72), the gate electrode and the first electrode of which are connected to the gate electrode of the above-mentioned first transistor (73), and have the same conductivity type as the above-mentioned first transistor (73); The third current limiting element (74), connected between the second electrode of the above-mentioned fourth transistor (72) and the sixth power supply potential (GND) line; and The differential amplifier circuit (40) controls the gate potential of the third transistor (71), so that the potential (VM) of the second electrode of the fourth transistor (72) is consistent with the corresponding gray level potential (VI). 4. The image display device according to claim 2, wherein said first control circuit (50, 86, 72, 87) comprises: A third current limiting element (86), connected between the fifth power supply potential (VDD) line and the gate electrode of the first transistor (73); a third transistor (72), the gate electrode and the first electrode of which are connected to the gate electrode of the above-mentioned first transistor (73), and have the same conductivity type as the above-mentioned first transistor (73); A fourth transistor (87) connected between the second electrode of the third transistor (72) and the sixth power supply potential (GND) line; and The differential amplifier circuit (50) controls the gate potential of the fourth transistor (87), so that the potential (VM) of the second electrode of the third transistor (72) is consistent with the corresponding gray level potential (VI). 5. The image display device according to claim 2, wherein said second control circuit (50, 106, 107, 109) comprises: A third transistor (106), the first electrode of which is connected to the fifth power supply potential (VDD) line; A fourth transistor (107), whose first electrode is connected to the second electrode of the above-mentioned third transistor (106), its gate electrode and second electrode are connected to the gate electrode of the above-mentioned second transistor (108), and has the same the same conductivity type of the second transistor (108); A third current limiting element (109), connected between the second electrode of the fourth transistor (107) and the sixth power supply potential (GND) line; and The differential amplifier circuit (50) controls the gate potential of the third transistor (106), so that the potential (VM) of the first electrode of the fourth transistor (107) is consistent with the corresponding gray level potential (VI). 6. The image display device according to claim 2, wherein the second control circuit (50, 111, 107, 112) comprises: A third current limiting element (111), one electrode of which is connected to the fifth power supply potential (VDD) line; The third transistor (107), its first electrode is connected to the other electrode of the above-mentioned third transistor (111), its second electrode and gate electrode are connected to the gate electrode of the above-mentioned second transistor (108), and has the same the same conductivity type of the second transistor (108); A fourth transistor (112) connected between the second electrode of the third transistor (107) and the sixth power supply potential (GND) line; and The differential amplifier circuit (50) controls the gate potential of the fourth transistor (112), so that the potential (VM) of the first electrode of the third transistor (107) is consistent with the corresponding gray scale potential (VI). 7. The image display device according to claim 1, wherein the above-mentioned first and second current amplifying circuits (31, 32) all include: a first transistor (73) connected between the first power supply potential (VDD) line and the output node (N46), and causes current to flow into the above output node (N46); a second transistor (108), connected between the above-mentioned output node (N46) and a second power supply potential (GND) line, so that current flows from the above-mentioned output node (N46); The control circuit (40, 71, 72, 74, 50, 111, 107, 112) controls the respective gate potentials of the first and second transistors (73, 108) so that the potential (VO ) is consistent with the corresponding gray level potential (VI); Wherein in the above-mentioned first current amplifying circuit (31), the current driving capability of the above-mentioned first transistor (73) is larger than the current driving capability of the above-mentioned second transistor (108), In the second current amplifying circuit (32), the current driving capability of the second transistor (108) is greater than that of the first transistor (73). 8. The image display device according to claim 7, wherein the above-mentioned first and second current amplifying circuits (31, 32) all include: a current limiting element (47, 56), connected between the output node (N46) and the third Between the power supply potential (GND, VDD) lines. 9. The image display device according to claim 7, wherein said control circuit (40, 71, 72, 74, 50, 111, 107, 112) comprises: A third transistor (71) connected between the third power supply potential (VDD) line and the gate electrode of the above-mentioned first transistor (73); a fourth transistor (72), the gate electrode and the first electrode of which are connected to the gate electrode of the above-mentioned first transistor (73), and have the same conductivity type as the above-mentioned first transistor (73); A first current limiting element (74), connected between the second electrode of the fourth transistor (72) and the fourth power supply potential (GND) line; The first differential amplifier circuit (40) controls the gate potential of the above-mentioned third transistor (71), so that the potential (VM) of the second electrode of the above-mentioned fourth transistor (72) and the corresponding gray scale potential (VI) consistent; The second current limiting element (111), one electrode of which is connected to the fifth power supply potential (VDD) line; The fifth transistor (107), its first electrode is connected to the other electrode of the second current limiting element (111), its second electrode and gate electrode are connected to the gate electrode of the second transistor (108), and has the same conductivity type as the above-mentioned second transistor (108); A sixth transistor (112), connected between the second electrode of the fifth transistor (107) and the sixth power supply potential (GND) line; and The second differential amplifier circuit (50) controls the gate potential of the sixth transistor (112), so that the potential (VM) of the first electrode of the fifth transistor (107) and the corresponding gray scale potential (VI) unanimous. 10. The image display device according to claim 7, wherein said control circuit (50, 86, 72, 87, 40, 106, 107, 109) comprises: The first current limiting element (86) is connected between the third power supply potential (VDD) line and the gate electrode of the first transistor (73); a third transistor (72), the gate electrode and the first electrode of which are connected to the gate electrode of the above-mentioned first transistor (73), and have the same conductivity type as the above-mentioned first transistor (73); A fourth transistor (87), connected between the second electrode of the third transistor (72) and the fourth power supply potential (GND) line; The first differential amplifier circuit (50) controls the gate potential of the above-mentioned fourth transistor (87), so that the potential (VM) of the second electrode of the above-mentioned third transistor (72) and the corresponding gray scale potential (VI) consistent; A fifth transistor (106), the first electrode of which is connected to the fifth power supply potential (VDD) line; The sixth transistor (107), its first electrode is connected to the second electrode of the above-mentioned fifth transistor (106), its gate electrode and second electrode are connected to the gate electrode of the above-mentioned second transistor (108), and has the same the same conductivity type of the second transistor (108); A second current limiting element (109), connected between the second electrode of the sixth transistor (107) and the sixth power supply potential (GND) line; and The second differential amplifier circuit (40) controls the gate potential of the above-mentioned fifth transistor (106), so that the potential (VM) of the first electrode of the above-mentioned sixth transistor (107) and the corresponding gray scale potential (VI) unanimous. 11. The image display device according to claim 7, wherein said control circuit (40, 71, 72, 74, 40, 106, 107, 109) comprises: A third transistor (71) connected between the third power supply potential (VDD) line and the gate electrode of the above-mentioned first transistor (73); a fourth transistor (72), the gate electrode and the first electrode of which are connected to the gate electrode of the above-mentioned first transistor (73), and have the same conductivity type as the above-mentioned first transistor (73); A first current limiting element (74), connected between the second electrode of the fourth transistor (72) and the fourth power supply potential (GND) line; The first differential amplifier circuit (40) controls the gate potential of the above-mentioned third transistor (71), so that the potential (VM) of the second electrode of the above-mentioned fourth transistor (72) and the corresponding gray scale potential (VI) consistent; A fifth transistor (106), the first electrode of which is connected to the fifth power supply potential (VDD) line; The sixth transistor (107), its first electrode is connected to the second electrode of the above-mentioned fifth transistor (106), its gate electrode and second electrode are connected to the gate electrode of the above-mentioned second transistor (108), and has the same the same conductivity type of the second transistor (108); A second current limiting element (109), connected between the second electrode of the sixth transistor (107) and the sixth power supply potential (GND) line; and The second differential amplifier circuit (40) controls the gate potential of the above-mentioned fifth transistor (106), so that the potential (VM) of the first electrode of the above-mentioned sixth transistor (107) and the corresponding gray scale potential (VI) unanimous. 12. The image display device according to claim 7, wherein said control circuit (50, 86, 72, 87, 50, 111, 107, 112) comprises: The first current limiting element (86) is connected between the third power supply potential (VDD) line and the gate electrode of the first transistor (73); a third transistor (72), the gate electrode and the first electrode of which are connected to the gate electrode of the above-mentioned first transistor (73), and have the same conductivity type as the above-mentioned first transistor (73); A fourth current limiting element (87), connected between the second electrode of the third transistor (72) and the second power supply potential (GND) line; The first differential amplifier circuit (50) controls the gate potential of the above-mentioned fourth transistor (87), so that the potential (VM) of the second electrode of the above-mentioned third transistor (72) and the corresponding gray scale potential (VI) consistent; The second current limiting element (111), one electrode of which is connected to the fifth power supply potential (VDD) line; The fifth transistor (107), its first electrode is connected to the other electrode of the second current limiting element (111), its second electrode and gate electrode are connected to the gate electrode of the second transistor (108), and has the same conductivity type as the above-mentioned second transistor (108); A sixth transistor (112), connected between the second electrode of the fifth transistor (107) and the sixth power supply potential (GND) line; and The second differential amplifier circuit (50) controls the gate potential of the sixth transistor (112), so that the potential (VM) of the first electrode of the fifth transistor (107) and the corresponding gray scale potential (VI) unanimous. 13. The image display device according to claim 7, wherein said control circuit (40, 71, 72, 74) comprises: A third transistor (71) connected between the third power supply potential (VDD) line and the gate electrode of the above-mentioned first transistor (73); a fourth transistor (72), the gate electrode and the first electrode of which are connected to the gate electrode of the above-mentioned first transistor (71), and have the same conductivity type as the above-mentioned first transistor (73); The fifth transistor (136), its first electrode is connected to the second electrode of the above-mentioned fourth transistor (72), its gate electrode and second electrode are connected to the gate electrode of the above-mentioned second transistor (137), and has the same the same conductivity type of the second transistor (137); A current limiting element (74), connected between the second electrode of the fifth transistor (136) and the fourth power supply potential (GND) line; and The differential amplifier circuit (40) controls the gate potential of the third transistor (71), so that the potential (VM) of the second electrode of the fourth transistor (72) is consistent with the corresponding gray level potential (VI). 14. The image display device according to claim 7, wherein said control circuit (50, 111, 141, 107, 112) comprises: a current limiting element (111), connected between the third power supply potential (VDD) line and the gate electrode of the first transistor (142); a third transistor (141), the gate electrode and the first electrode of which are connected to the gate electrode of the above-mentioned first transistor (142), and have the same conductivity type as the above-mentioned first transistor (142); The fourth transistor (107), its first electrode is connected to the second electrode of the above-mentioned third transistor (141), its gate electrode and second electrode are connected to the gate electrode of the above-mentioned second transistor (108), and has the same the same conductivity type of the second transistor (108); A fifth transistor (112), connected between the second electrode of the above-mentioned fourth transistor (107) and the fourth power supply potential (GND) line; and The differential amplifier circuit (50) controls the gate potential of the fifth transistor (112) so that the potential (VM) of the first electrode of the fourth transistor (107) coincides with the fourth gray scale potential (VI). 15. The image display device according to claim 1, wherein said first current amplifying circuit (151, 155, 158) comprises: The first level shift circuit (151), outputting a potential (V152) higher than a specified voltage than the corresponding gray level potential (VI); a pull-up circuit (155) charging the first output node (N46) to a potential (VI) lower than the output potential (V152) of the first level shift circuit (151) by the predetermined voltage; and The first current limiting element (158), connected between the above-mentioned first output node and the first power supply potential (GND) line, has a current driving capability smaller than that of the above-mentioned pull-up circuit (155), so that the current from The above-mentioned first output node (N46) flows out, The above-mentioned second current amplifying circuit (161, 166, 165) includes: The second level shift circuit (161) outputs a potential (V163) lower than the above-mentioned specified voltage than the corresponding gray level potential (VI); a pull-down circuit (166), which discharges the second output node (N56) to a potential (VI) higher than the output potential (V163) of the second level shift circuit (161) by the predetermined voltage; and The second current limiting element (165), connected between the second power supply potential (VDD) line and the above-mentioned second output node (N56), has a current driving capability smaller than that of the above-mentioned pull-down circuit (166), so that A current flows into the above-mentioned second output node (N56). 16. The image display device according to claim 1, wherein the above-mentioned first and second current amplifying circuits (31, 32) all include: The first level shift circuit (151), outputting a potential (V152) higher than a specified voltage than the corresponding gray level potential (VI); The pull-up circuit (155) charges the output node (N172) to a potential (VI) lower than the output potential (V152) of the first level shift circuit (151) by the predetermined voltage; The second level shift circuit (161) outputs a potential (V163) lower than the corresponding gray level potential (VI) by a prescribed voltage; a pull-down circuit (166), discharging the output node to a potential (VI) higher than the output potential (V163) of the second level shift circuit (161) only by the specified voltage; In the above-mentioned first current amplifying circuit (31), the current driving capability of the above-mentioned pull-up circuit (155) is larger than that of the above-mentioned pull-down circuit (166), In the second current amplifying circuit (32), the current drive capability of the pull-down circuit (166) is greater than that of the pull-up circuit (155). 17. The image display device according to claim 16, wherein the above-mentioned first and second current amplifying circuits (31, 32) all comprise: The current limiting element (158, 165) is connected between the above-mentioned output node (N172) and the power supply potential (GND, VDD) line. 18. The image display device according to claim 1, wherein the above-mentioned horizontal scanning circuit (8) further comprises: an offset compensation circuit (181, S11-S13), respectively connected to the above-mentioned first and second current amplifying circuits (31, 32) Set correspondingly, detect the offset voltage (VOF) of the corresponding current amplifying circuit, and cancel the offset voltage (VOF) of the corresponding current amplifying circuit according to the detection result. 19. The image display device according to claim 1, wherein said pixel display element (2, 11, 12) comprises a liquid crystal cell (2) whose light transmittance varies with said gray scale potential, The above-mentioned potential generating circuits (R1-R65) generate the above-mentioned multiple gray scale voltages (V1d-V64d) after dividing the positive power supply voltage (VH-VL) in the first period, and the negative power supply voltage (VL-VH ) to generate the above-mentioned multiple gray scale voltages (V1d～B64d) after voltage division, Set two groups of the above-mentioned first and second current amplifying circuits (31, 32), one group of first and second current amplifying circuits (31, 32) are activated during the above-mentioned first period, and another group of first and second current amplifying circuits The circuits (31, 32) are activated during the above-mentioned second period, The above-mentioned selection circuit (25) provides the output potential of the above-mentioned group of first or second current amplifying circuits (31 or 32) selected in the first period to each activated pixel display element (2) through each data line (6). , 11, 12), through each data line (6), the output potential of the above-mentioned another group of first or second current amplifying circuits (31 or 32) selected during the second period is provided to each pixel display element activated ( 2, 11, 12). 20. The image display device according to claim 1, wherein said pixel display element (2, 11, 12) comprises a liquid crystal cell (2) whose light transmittance varies with said gray scale potential, The above-mentioned potential generating circuit (60, 61) includes: The first voltage divider circuit (60) divides the positive power supply voltage (VH-VL) to generate the above-mentioned multiple gray scale voltages (V1a-V64a) The second voltage divider circuit (61) divides the negative power supply voltage (VL-VH) to generate the above-mentioned multiple gray scale voltages (V1b-B64b) Set two groups of the above-mentioned first and second current amplifying circuits (31, 32), A group of first and second current amplifying circuits (31, 32) are set corresponding to the above-mentioned first voltage dividing circuit (60), and are activated during the first period, Another set of first and second current amplifying circuits (31, 32) are set corresponding to the above-mentioned second voltage dividing circuit (61), and are activated during the second period, The above-mentioned selection circuit (25) provides the output potential of the above-mentioned group of first or second current amplifying circuits (31 or 32) selected in the above-mentioned first period to the activated pixel display elements ( 2, 11, 12), through each data line (6), the output potential of the above-mentioned other group of first or second current amplifying circuits (31 or 32) selected in the second period is provided to each activated pixel display element (2, 11, 12).

Images