CN1625811A - Silicon germanium transistors with improved cut-off frequency - Google Patents

Abstract

A bipolar transistor for a small signal amplifier has an improved early voltage and an enhanced cutoff frequency. The SiGe layer (14) has a thickness (t) and Ge concentration greater than the SiGe stability limit, misfit dislocations do not create significant charge trapping sites and do not extend into the overlying base/collector junction, thereby improving performance without reducing yield.

Description

Silicon germanium transistors with improved cut-off frequency

technical field

The present invention relates to silicon germanium (SiGe) heterojunction bipolar transistors (HBTs).

Background technique

It is generally known to form HBTs by using a wafer comprising one or more layers of silicon germanium (SiGe) on a silicon substrate. On this substrate, germanium atoms create mechanical strain in the composite film due to the difference in lattice constant between the SiGe film and the silicon substrate. In the plane of the silicon substrate, a SiGe lattice with a larger lattice constant is pressed against a silicon substrate with a smaller lattice constant. In a plane perpendicular to the silicon substrate, the SiGe layer has a lattice constant greater than that of the silicon substrate and is thus under tensile stress. The strain, together with the Ge atoms themselves, produces a bandgap shift between the SiGe film and the underlying native Si substrate. This bandgap offset provides unique advantages of SiGe HBTs by creating a graded region in the base region that enhances carrier diffusion over the base region and thus increases transistor speed. SiGe HBTs have been used in transistors for small signal amplifiers (i.e. switching around 5 volts or less) to provide the switching speeds (above 1 GHz) required by today's wireless communication devices.

One of the difficulties encountered by the inventors during the use of SiGe HBTs in small-signal amplifiers is that the output characteristics (i.e., collector current vs. collector-emitter voltage) of the common emitter for such amplifiers typically show Poor early voltage. The "early voltage" (V _A ) is the slope characteristic of these output characteristics, as indicated by the extrapolation of the curve to the voltage at IC = 0A. The more horizontal the curve, the greater the voltage at which IC = 0 is extrapolated, and therefore the higher the early voltage. Figure 1a (prior art) shows the early voltage of a SiGe HBT without using the present invention. Each curve indicates the output characteristics for different applied base voltages; the higher the curve, the higher the applied base voltage. It should be noted that the slope of the curve becomes more vertical as the applied base voltage increases.

The inventors have noted that V _A is a key indicator of the current gain cutoff frequency (f _T ) of the SiGe HBT. NPN devices with low _VA have now been found to have low _fT . Devices with reduced current gain cutoff frequency provide suboptimal switching speed.

Therefore, there is a need in the art to develop SiGe HBTs with enhanced early voltage, which in turn increases the current gain cutoff frequency.

Contents of the invention

It is thus an object of the present invention to increase the current gain cutoff frequency of SiGe HBTs.

In a first aspect, the present invention is a SiGe HBT comprising a SiGe layer having a thickness and a Ge concentration greater than the SiGe stability limit in which multiple misfit dislocations do not create significant charge trapping sites.

In another aspect, the invention is a SiGe HBT having a SiGe layer having a thickness of at least about 70 nm, a Ge concentration of at least 10% on a plurality of isolation structures, base/collector junctions on the isolation structures, and no significant Multiple misfit dislocations extending across the base/collector junction.

In another aspect, the invention is a bipolar transistor for a small signal amplifier having a cutoff frequency of at least about 19 GHz, having a SiGe layer having a thickness and Ge concentration greater than the SiGe stability limit, a plurality of layers abutting the collector region isolation regions, and a base region formed on the collector region, a plurality of misfit dislocations in the SiGe layer are adjacent to the plurality of isolation regions and extend into the collector region, while substantially does not extend into the base region.

In another aspect, the present invention is a method of forming a bipolar transistor, comprising the steps of: forming a plurality of isolation regions in a silicon substrate; forming a SiGe layer on the substrate and the isolation regions, the a SiGe layer having a thickness and a Ge concentration greater than a SiGe stability limit; and doping the SiGe layer and substrate with a first dopant to form a collector region, wherein the collector region includes a plurality of misfit dislocations, Substantially no extension beyond the collector region into other portions of the bipolar transistor.

Description of drawings

The above and other structures and features of the present invention will become more apparent through the detailed description of the present invention shown below. In the following description, reference is made to the accompanying drawings in which:

Figure 1a is a graph of the IC and VCE of the experimental SiGe HBT;

Fig. 1 b is the graph of IC and VCE of SiGe HBT of the present invention;

Figure 2 shows a plot of collector current density versus cutoff frequency for NPNs with early voltages shown in Figures 1a and 1b, respectively;

3 is a graph of SiGe concentration versus thickness, showing multiple experimental data points superimposed on SiGe stability curves including those of the present invention and those reported in prior art articles;

Figure 4 is a cross-sectional view of a SiGe HBT constructed in accordance with the teachings of the first embodiment of the present invention;

Figure 5 shows the Gummel plot (IC, IB vs. VCE) of the NPN with the early voltages shown in Figures 1a and 1b respectively;

Figure 6 is standard yield data for the thickness of the SiGe HBT shown by the data points in Figure 3; and

FIG. 7 is a graph of three embodiments of Ge concentration and layer thickness of the SiGe layer of the present invention.

Detailed ways

The inventors have found that the early voltage (and thus cut-off frequency) can be significantly increased by increasing the thickness of the SiGe layer. Although it is known in the art to increase the thickness of SiGe layers for other purposes, thicker SiGe layers are generally avoided due to concerns about creating misfit dislocations. As will be described in detail below, the inventors discovered that when properly controlled, misfit dislocations do not negatively affect the performance or yield of the resulting SiGe HBT.

SiGe enhances the charge mobility by introducing mechanical strain due to the inherent lattice mismatch in Si-Ge compounds. However, if too much Ge is present, or if the SiGe layer is too thick, it is accepted in the art that the resulting crystal dislocations will degrade performance and yield. The performance deteriorates due to the bandgap shift provided by SiGe due to the release of mechanical stress by dislocations. Yield deteriorates due to defects affecting the crystal of the substrate. In fact, this general understanding became popular and is often recognized as the "Matthews-Blakesley Stability Limit" or "Stiffler Limit" in recognition of the researchers who first reported these interactions (Stiffler et al., Journal of Applied Physics, Vol.71, No.10, pp. 4820-4825; Matthews and Blakeslee "Defects in Epitaxial Multilayer", Journal of Crystal Growth 27, pp. 118-125 (1974)). For future reference, these results will be referred to as "SiGe Stability Limits". The different SiGe stability limits reported by Matthews-Blakesley and Stiffler are plotted in Fig. 3, showing the best relationship between SiGe thickness and Ge concentration.

More research has focused on various methods to exceed the stability limit of SiGe by eliminating these misfit dislocations. See US Patent 5,256,550 to Laderman et al., which discusses the use of low temperature epitaxy to deposit a first SiGe layer, then cap the Si layer, followed by appropriate thermal cycling to form a thicker SiGe layer free of misfit dislocations. In this structure, an overlying Si layer is required to preserve the strain of the SiGe layer without generating misfit dislocations. Paper by K. Schonenberg et al., entitled "The Stability of SiGe Strained Layers on Small Area Trench Isolated Silicon Islands", Electrochemical Society Proceedings, Vol.96-4, Proceedings of the 4 ^th International Symposium on Process Physics and Modeling in Semiconductor Technology. Los Angeles , CA May-October 1996, pp. 296-308, reported that as the size of the SiGe region surrounded by the isolation region decreased, the observed defect density decreased, and the shallow trench isolation process was modified to reduce stress. Related content of this area is also reported in Vescan, "Selective Epitaxial Growth of Strained SiGe/Si for Optoelectronic Devices," Materials Science and Engineering B, Solid-State Materials for Advanced Technology, Vol.51, No.1-3, 166-69 p. (1998).

Another reason to avoid misfit dislocations in the active region of bipolar transistors is to prevent charge trapping sites from being created. These charge trapping sites, if present in sufficient numbers, will reduce the minority carrier lifetime. In a typical bipolar transistor, this causes a reduction in current gain, which is undesirable in small signal applications. However, in power amplifier applications, reduced current gain can be tolerated. Thus, U.S. Patent 5,097,308 teaches intentionally introducing 9-20 μm dislocations from the SiGe-Si interface to provide traps for more recombination of minority carriers, thereby reducing minority carriers in bipolar power rectifiers lifespan. Low minority carrier lifetime is required in bipolar rectifiers to increase switching speed. The switching speed in a bipolar transistor is determined by the degree to which the charge in the base region is quickly removed. One charge removal process is recombination whereby electrons and holes recombine at charge trapping sites to turn off the transistor. However, for standard SiGe bipolar transistor small-signal amplification applications, the reduced current gain that accompanies this minority carrier lifetime is undesirable (in fact it can usually be avoided; said reduction in switching speed is coupled with an increase in switching speed off Incompatible target for current gain frequency).

The present inventors have now discovered that by compounding the SiGe layer at a thickness/concentration greater than the SiGe stability curve, the early voltage is significantly increased, the cut-off frequency is increased, and the mechanical stress is not significantly released without generating misfit dislocations. The gap offset does not significantly affect the crystallinity of the substrate. Figure 3 shows the SiGe thickness and concentration used to provide the data reported here. For comparison, the Ge concentration was fixed at 10%, and the thickness was increased. It should be noted that the first two data points are at or below the SiGe stability curve; these devices provide the early voltage results shown in Figure 1a. The SiGe thickness of the present invention starts at about 70 nm.

As shown in FIG. 4, the SiGe HBT of the present invention is formed on a single crystal silicon substrate 10 having a shallow trench isolation (STI) 12 therein. SiGe layer 14 is epitaxially grown on substrate 10 to a thickness of at least 40 nm with a Ge concentration of at least about 10% using conventional techniques. After proper doping to form collector region 14C, the SiGe layer is doped in situ with boron during growth to form base region 14B (not shown laterally to scale). It should be noted that in practice boron from the base region can diffuse deep into the SiGe layer, from depth X to depth Y of SiGe layer 14, during various processing thermal cycles. Thus, a substrate/collector junction can be created at either JA or JB. Thereby, an emitter electrode (not shown) is subsequently formed using well-known techniques to complete the formation of the HBT. The HBT of the present invention is then connected to other HBTs formed on the substrate to form an integrated circuit.

Figure 1b shows the collector circuit and collector-emitter voltage of the SiGe HBT of the present invention. It should be noted that the early voltage is increased significantly (the curve is very horizontal for all applied base voltages, implying a constant collector current for increasing collector-emitter voltage).

Figure 2 shows plots of collector current density versus cutoff frequency for cases a and b: (a) NPN with the early voltage shown in Figure 1a (shown in dashed lines); and (b) with the voltage shown in Figure 1b NPN of early voltage (shown by solid line). It should be noted that the cut-off frequency is increased for transistors with increased early voltage for the present invention. The peak Ft is about 19GHz. It should also be noted that the cutoff frequency increases over a wider range of collector currents.

It is an aspect of the invention that these gains and cutoff frequencies in early voltage do not come at the expense of performance (via charge trapping) or yield (via crystal dislocations).

Considering charge trapping first, it should be noted that the increase in cutoff frequency shown in Fig. 4 is first observed; if proper charge trapping is introduced through misfit dislocations, the resulting carrier recombination will lower the cutoff frequency, without increasing it. Also, Figure 5 shows the Gummel curves (IC, IB and VCE) of the NPN with the early voltages shown in Figures 1a and 1b, respectively. It should be noted that the IB and IC in the Gummel plot have ideal slopes (n ~ 1 (n is an ideal measure) or 60mV/decade at room temperature), indicating the absence of misfit dislocations introduced by misfit dislocations formed as part of the thicker SiGe. Significant charge trapping. One of the consequences of avoiding increased charge trapping is shown in Figures 1a and 1b, achieving these higher cutoff frequencies while unresponsively reducing the breakdown voltage (BVCEO) of the device; or, put another way, as SiGe thickness increases , the cut-off frequency Ft of the device with a given breakdown voltage BVCEO increases. This becomes especially important for device designs that require high breakdown voltage devices (eg in power amplifiers or read heads).

Considering yield now, Figure 6 shows the standard yield curves for SiGe HBTs of the present invention for different SiGe thicknesses. The first region shown (300 Angstrom thickness, 10% Ge concentration) approximates the upper limit of the SiGe stability curve (see Figure 2). It should be noted that the yield does not change significantly as the thickness increases above the SiGe stability curve at 10% Ge concentration. This indicates that misfit dislocations in the SiGe layer of the present invention do not significantly affect the crystallinity of the substrate, since if they did, the yield would drop with increasing SiGe thickness.

FIG. 7 shows a plot of Ge concentration percentage versus depth of a 70 nm thick SiGe layer for three embodiments of the present invention. In the first embodiment, as shown by curve A, the Ge concentration in the SiGe layer of the present invention is approximately 10% in the entire thickness of a 40 nm-thick SiGe film. This example produces the collector current versus collector-emitter voltage curve of the present invention shown in solid line in FIG. 3 . In the second embodiment, as shown by curve B, the Ge concentration in the SiGe layer of the present invention is approximately 10% in the entire thickness of a 70 nm-thick SiGe film. The first and second embodiments yield the yield data shown in FIG. 6 . In the third embodiment, as shown by the curve C, the Ge concentration in the SiGe layer of the present invention is about 25% at the upper surface of the SiGe layer and one-third of its thickness (about 23 nm for a 70 nm thick SiGe film) , then at two-thirds of the thickness of the SiGe film, the percentage of Ge drops in a remarkably linear manner from 25% to 10%, and then for the remaining thickness of the SiGe film, the concentration is 10%. By reducing the content at the lower surface to 10%, the misfit dislocations, yield and performance results are the same as observed for the first two examples of the present invention.

In a fourth embodiment of the invention (not shown in FIG. 7 ), the SiGe layer is 150 nm thick and has a Ge concentration of approximately 10% throughout its thickness. The inventors found that even at this thickness and Ge concentration, misfit dislocations have the overall properties reported here. From these results, the inventors believe that the SiGe layer could even be thicker than 150nm and still provide the reported properties.

The results reported here indicate that there is no fundamental reason why SiGe concentration and thickness need to be limited by dislocation generation factors.

Thus, it is apparent that the only qualitative limitation on the percent Ge concentration is the introduction of too little or too much stress in the underlying Si layer, and the inventors believe that concentration drops below about 5% do not provide sufficient stress to introduce a significant amount of stress. Increased charge mobility, concentration above about 35% provides prohibitive stress in the thickness range (about 70nm and above), apparently due to the formation of hillocks on the upper surface of the SiGe layer, optimizing early voltage or reducing yield .

The present inventors have found that the misfit dislocations in the SiGe layer of the present invention are located in most regions of the STI edges 12A, 12B shown in FIG. 3 . Dislocations tend to extend horizontally along the SiGe/Si interface shown by dashed line 10A. Apparently substantially no extension into the base/collector junction JA or JB is observed, and at this time, we do not observe extension into the emitter region. And, as mentioned earlier, the ideal Gummel curve shows that the resulting dislocations do not establish proper charge-trapping sites.

Thus, contrary to what is taught in the art, the inventors discovered that a SiGe layer with misfit dislocations can improve performance without reducing yield. Contrary to what is taught in the art, the inventors have found that a large number of misfit dislocations by themselves or within them does not determine performance or yield. Rather, the key is that the dislocations do not generate significant charge trapping and do not traverse the base/collector junction in significant numbers.

Although the invention has been described above with reference to specific embodiments, the invention is not limited thereto. Modifications to the described embodiments may be made without departing from the spirit and scope of the claimed invention. For example, while specific Ge concentrations, concentration gradients, and/or thicknesses are taught, other concentrations, gradients, and/or thicknesses may be used as long as they provide the same overall results reported herein.

Industrial Applicability

The invention is applicable to circuits and devices, particularly circuits and devices used in communication systems.

Claims (23)

1. A silicon germanium (SiGe) heterojunction bipolar transistor (HBT), comprising a SiGe layer (14) having a thickness (t) and a Ge concentration greater than the SiGe stability limit, and a plurality of misfit positions in it False did not produce significant charge trapping sites. 2. The HBT of claim 1, wherein said SiGe layer (14) has a base/collector junction, and wherein said plurality of misfit dislocations does not extend significantly over the base/collector junction. 3. The HBT according to claim 1, having a SiGe layer (14) having a thickness (t) of at least approximately 70 nm and a Ge concentration of at least 10% on a plurality of isolation structures (12), the base on the isolation structures (12) /collector junction, and multiple misfit dislocations that do not extend significantly over the base/collector junction. 4. The HBT of claim 3, wherein the plurality of misfit dislocations do not create significant charge trapping sites. 5. The HBT according to claim 1, wherein said HBT has a cut-off frequency of at least about 19 GHz, a plurality of isolation regions (12) abutting said collector region, and a base region formed on said collector region, Wherein the plurality of misfit dislocations in the SiGe layer are adjacent to the plurality of isolation regions (12) and extend into the collector region while substantially not extending into the base region. 6. Transistor according to claim 5, wherein said SiGe layer (14) has a Ge concentration of at least 10%. 7. Transistor according to claim 6, wherein said SiGe layer (14) has a thickness (t) of at least about 70 nm. 8. The transistor of claim 6, wherein said SiGe layer (14) has a thickness (t) of at least about 150 nm. 9. The transistor of claim 6, wherein said SiGe layer (14) has a Ge concentration that varies within said SiGe layer (14). 10. Transistor according to claim 9, wherein the Ge concentration of said SiGe layer (14) has a higher value at its upper surface and a lower value at its lower surface. 11. The transistor according to claim 10, wherein said Ge concentration has a first value in an upper portion of said SiGe layer (14) and a second value smaller than said first value in a lower portion of said SiGe film, and the value in the middle part of said SiGe layer (14) is changed from said first value to said second value. 12. The transistor of claim 11, wherein said upper value is about 25% and said lower value is about 10%. 13. Transistor according to claim 11, wherein said Ge concentration is about 25% in the upper third of the thickness (t) of said SiGe layer (14). 14. Transistor according to claim 13, wherein in the middle third of the thickness (t) of said SiGe layer (14) said Ge concentration decreases in a generally linear manner from 25% to 10%. 15. Transistor according to claim 14, wherein said Ge concentration is about 10% in the lower third of the thickness (t) of said SiGe layer (14). 16. A method of manufacturing a bipolar transistor according to any one of claims 1-15 with increased Ft and with a given BV _CEO , comprising the steps of: forming a plurality of isolation regions (12) in the silicon substrate (10); forming a SiGe layer (14) on said substrate (10) and said isolation region (12), said SiGe layer (14) having a thickness (t) and a Ge concentration greater than a SiGe stability limit; and doping the SiGe layer (14) and substrate (10) with a first dopant to form a collector region, wherein the collector region includes a plurality of misfit dislocations substantially not extending to the collector out of the region into the rest of the bipolar transistor. 17. The method according to claim 16, wherein said SiGe layer (14) has a Ge concentration between 5% and 35%. 18. The method of claim 16, wherein said SiGe layer (14) has a Ge concentration of at least about 10%. 19. The method according to claim 16, wherein said SiGe layer (14) has a thickness (t) of at least about 70 nm. 20. The method according to claim 19, wherein said SiGe layer (14) has a thickness (t) of at least about 150 nm. 21. The method of claim 17, wherein said SiGe layer (14) has a Ge concentration that varies within said SiGe layer (14). 22. A method according to claim 21, wherein the Ge concentration of said SiGe layer (14) has a higher value at its upper surface and a lower value at its lower surface. 23. The method according to claim 21 , wherein said Ge concentration has a first value in an upper portion of said SiGe layer (14) and a second value smaller than said first value in a lower portion of said SiGe film, and the value in the middle part of said SiGe layer (14) is changed from said first value to said second value.

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