CN1622067A - Method for high speed SATA interface data recovery and serial-parallel conversion and circuit module - Google Patents
Method for high speed SATA interface data recovery and serial-parallel conversion and circuit module Download PDFInfo
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Abstract
The high speed SATAn interface data restoring and serial-parallel conversion method includes the following steps: inputting high speed serial signal to obtain four ways of frequency-lowering shunt signal; sampling the four ways of frequency-reducing shunt signal separately; generating one clock signal from the serial line for subsequent sync circuit; outputting integrated sample signal in each clock period; eliminating excessive bits of the sample signal in each clock period and connecting effective bits to constitute bit sequence datan output; comparing the bit sequence datan and the sync word of the protocol for aligning bits and outputting effective protocol data. The circuit module based on the method includes frequency-reducing shunt circuit, successively connected four circuits of sample circuit, integrating output circuit, clock generator circuit and redundant bit eliminating circuit, as well as bit aligning circuit and micro controller.
Description
Technical field
The present invention relates to data processing, particularly the method and the circuit module of recovery of high speed SATA interface data and serial-parallel conversion circuit.
Background technology
The development of infotech improves constantly high bandwidth and easy internuncial requirement, thereby impels high-speed serial bus to obtain to develop rapidly.From USB1.1 to USB2.0, from PATA to SATA, the development from PCI to PCI-Express shows that high-speed serial interconnect has become a great development focus of computer realm.Specifically, be exactly in the design of high speed serialization ata bus interface integrated circuit, utilize the temporal information of transmitted bit, restore data from the high speed serialization line, and finish serial-to-parallel conversion.
Traditional parallel bus adopts source synchronous clock more, and clock and data send simultaneously by the unlike signal line.In the Synchronization Design of source, clock and data that transmit leg sends are to require them to arrive the take over party simultaneously through different wired circuit They on the circuit board, could correctly receive data,, make that the management of plate level clock distortion is more and more difficult along with improving constantly of transmission frequency.In high-speed serial bus, in order to improve transmission bandwidth, and avoid plate level clock distortion problem, high-speed serial bus adopts embedded clock to obtain the bandwidth of number G bits per second.Embedded clock scheme is meant by same signal line while tranmitting data register and data, recovers clock signal and data-signal by receiver from received signal.High speed serial transmission generally adopts 8B/10B coding (corresponding maximum transmitted pulsewidth is 5 bit), or non-return-to-zero coding NRZ (Non Return to Zero Coding) (corresponding maximum transmitted pulsewidth is 7 bit).For example, serial ATA 1.0 interfaces are exactly a HSSI High-Speed Serial Interface that adopts embedded clock, and bandwidth is 1.5Gbps, and coded system is the 8B/10B coding.Serial ATA interface adopts the full duplex mode communication; Carry out the transmitting-receiving of data simultaneously, adopt the mode that sends synchronization character to carry out during the transmission data bit.
From the high speed serialization line, data are recovered out, two kinds of methods are arranged usually: method 1, clock and data recovery technology CDR (Clock﹠amp; Data Recovery), the CDR technology locks the high-speed clock signal that embeds on the string line at receiving end with phase-locked loop circuit PLL (Phase Locked Loop), with the clock signal of recovering out, the data on the string line is carried out sampling in 1: 1.Method 2, over-sampling data recovery technique (Over-sampling Data Recovery), it does not need to recover synchronous high-speed clock signal from string line, but carry out over-sampling (＞1: 1) with a clock signal more at a high speed the take over party, and then remove the redundant bit in the data behind the over-sampling, thereby obtain actual bit signal.
In above-mentioned two kinds of methods, the CDR method need be obtained the clock signal of a high speed from string line, and the PLL circuit is realized with mimic channel usually.For example, the patent No. is the United States Patent (USP) in 6442225 (in Augusts, 2002): " Multi-phase-locked loopfor data recovery " is by a leggy voltage controlled oscillator, produce the different clock signal of a series of phase place and survey the transmission border of serial signal, thereby reduce the phase error of serial input signals and clocking.Although it can reduce the tolerance that clock trembles and improves the data random offset, when making, integrated circuit (IC) design uses analog-and digital-hybrid technique, and this will strengthen the difficulty of technology.And the shared chip area of mimic channel is big, and the phase locking time is long.Along with the continuous increase of transfer rate, PLL circuit at a high speed also more and more is difficult to realize.
For another example, the patent No. is the United States Patent (USP) in 6611219 (in Augusts, 2003): " Oversampling data recovery apparatusand method " adopted the data reconstruction method of over-sampling, and it is with a sampling that has 2 times of 4 phase places to the clock of serial signal serial input signals to be carried out 4: 1.In data recovery procedure, change the decision threshold of sampled data according to the variation of real input signal, can improve the tolerance of data random offset.But because a large amount of redundant signals of having sampled needs the circuit of a large amount of removal redundant bits to carry out aftertreatment, circuit scale is bigger.And along with the continuous increase of transfer rate, the high speed local clock signal that is used to sample also is the difficult point of design.
Overcome the phase locking overlong time that exists in the prior art, defectives such as circuit scale is excessive, and can improve the tolerance of data random offset effectively, finish better that serial data is recovered and serial data to the conversion of parallel data, be that technical task to be solved is arranged.
Summary of the invention
The data processing scheme that the purpose of this invention is to provide a kind of full-digital circuit, do not need extra locking time of restore data immediately, make manufacturing and designing of high-speed serial bus interface integrated circuit be more prone to realize, in the method that a kind of high speed SATA interface data recovery and string and conversion are provided, also provide a kind of circuit module that can reduce circuit power consumption effectively.
For achieving the above object, the invention provides a kind of high speed SATA interface data recovers and the method for going here and there and changing, this method is carried out recovery and the string and the conversion of high-speed serial data by the data processing circuit module that contains signal sample circuit, clock generation circuit and clock synchronization circuit, and its method comprises the steps:
1) input: receive high-speed serial signals;
2) frequency reducing along separate routes: with described high-speed serial signals 4 frequency divisions, and obtain 4 tunnel frequency reducing shunting signs respectively;
3) sampling: 4 tunnel frequency reducing shunting signs are sampled respectively, obtain 4 tunnel 4 bit sample data;
4) clock: in step 3), obtain a clock signal that is used for subsequent conditioning circuit from the string line of frequency reducing shunting sign;
5) integrate: 4 tunnel sampled datas are latched, obtain the 32 bit sample data synchronous with clock signal;
6) go redundancy: to described and 32 synchronous bit sample data of clock signal, remove wherein unnecessary bit, and effective bit is connected, obtain the significant bit sequence data of a certain-length and the useful signal of these data;
7) alignment: the synchronizing signal of described significant bit sequence data and Data Transport Protocol is compared, carry out bit aligned, obtain complete agreement valid data, export the useful signal of these data simultaneously;
8) output: the useful signal of described clock signal, agreement valid data and these data that output is obtained.
The invention provides a kind of high speed SATA interface data and recover and the method for going here and there and changing, its sampling comprises the steps:
1) each road frequency reducing shunting sign is made 1/2 bit time delays earlier, make 41 bit time delayses more successively, obtain 4 sampled signals;
2) latch this 4 sampled signals with this road frequency reducing shunting sign, obtain 4 tunnel 4 bit sample data.
The invention provides a kind of high speed SATA interface data and recover and the method for going here and there and changing, wherein, the clock signal that is used for subsequent conditioning circuit produces by the 3 tunnel frequency reducing shunting sign being carried out two divided-frequency.
The invention provides a kind of high speed SATA interface data and recover and the method for going here and there and changing, its integration comprises the steps:
1) latchs the 3 tunnel sampled data with the 1 road fractional frequency signal; Latch the 4 tunnel sampled data with the 2 road fractional frequency signal; Latch the 1 tunnel sampled data with the 3 road fractional frequency signal; Latch the 2 tunnel sampled data with the 4 road fractional frequency signal;
2) be latched in the two paths of data that latchs in the step 1) respectively with the 3 road fractional frequency signal and its inversion signal; Latch the data of gained again with the 3 road fractional frequency signal, obtain the 32 bit sample data synchronous with clock signal.
For reaching aforementioned purpose, the present invention also provides a kind of high speed SATA interface data to recover and the circuit module of going here and there and changing, comprise redundant bit circuit and coupled bit aligned circuit, and the microcontroller of setting the time-delay controlled variable, also comprise frequency reducing shunt circuit, 4 identical sample circuits, integration output circuit and clock generation circuits, wherein:
The frequency reducing shunt circuit is a four-divider, high-speed serial signals input four-divider, and its 4 road fractional frequency signal is connected to 4 sample circuits respectively, inserts simultaneously and integrates output circuit, and wherein one road fractional frequency signal also is connected to clock generation circuit;
Each sample circuit is made up of 1 1/2 bit that links to each other successively delay time adjustable unit and the latch of adjustable unit and 41 bits of delaying time, microcontroller and 1/2 bit adjustable unit and 4 the 1 bits adjustable unit of delaying time of delaying time links to each other respectively, one of 4 road fractional frequency signals are connected to the 1/2 bit adjustable unit of delaying time, wherein:
The delay time output signal of adjustable unit of 1/2 bit is connected to 1 bit that connects the successively adjustable unit of delaying time, and the delay time output signal of adjustable unit of 41 bits is connected to latch respectively, and 4 bit sample data of latch output are connected to the integration output circuit;
Clock generation circuit be connected to the frequency reducing shunt circuit and remove the redundant bit circuit and the bit aligned circuit between, fractional frequency signal is connected to the clock generation circuit input end; The clock signal of its output is connected to redundant bit circuit and bit aligned circuit respectively, and as the clock signal of circuit module;
Integrating output circuit is the d type flip flop group, and 32 synchronous bit sample data of its output and clock signal are connected to the redundant bit circuit;
Remove redundant bit circuit output significant bit sequence data, and export the useful signal of these data simultaneously, be connected to the bit aligned circuit;
The bit aligned circuit is exported the parallel agreement valid data of actual transmissions, and exports the useful signal of these data simultaneously.
High speed SATA interface data provided by the invention recovers the circuit module with string and conversion, and wherein, clock generation circuit is a two-divider, and input signal obtains clock signal through two-divider, as the clock signal output of subsequent conditioning circuit and circuit module.
High speed SATA interface data provided by the invention recovers the circuit module with string and conversion, and wherein, microcontroller is the MCU that is used to set delay parameter, and its 2 bit control signal is connected to the 1/2 bit adjustable unit of delaying time; Its 3 bit control signal is connected to the 1 bit adjustable unit of delaying time.
The Method and circuits module of a kind of high speed SATA interface data recovery provided by the invention and serial-parallel conversion circuit, its technical scheme has following distinguishing feature: (1) the invention provides the full-digital circuit of high-speed serial data recovery and serial-parallel conversion circuit, owing to do not have Analogous Integrated Electronic Circuits and digital integrated circuit hybrid technique problem, make that manufacturing and designing of high-speed serial bus interface integrated circuit is more prone to realize.(2) circuit of the present invention restore data does not immediately need extra locking time.(3) circuit of the present invention need not the local clock signal, nor uses the clock signal that recovers embedding from string line.Used clock signal is obtained from the serial input signals frequency division in the circuit, and when on the string line during no signal, circuit is not worked yet, and can reduce circuit power consumption effectively like this.
Reach embodiment below just in conjunction with the accompanying drawings technical scheme of the present invention is elaborated, so that further set forth purpose of the present invention, feature and advantage.
Description of drawings
Fig. 1 is the block scheme of high speed SATA interface data recovery of the present invention and serial-parallel conversion circuit;
Fig. 2 is the circuit theory diagrams of frequency reducing shunt circuit;
Fig. 3 is a frequency reducing shunt circuit input and output signal oscillogram;
Fig. 4 is the block scheme of sample circuit;
Fig. 5 is the oscillogram of sample circuit input and output signal;
Fig. 6 is the delay time circuit theory diagrams of adjustable element circuit of 1/2 bit;
Fig. 7 is the delay time circuit theory diagrams of adjustable element circuit of 1 bit;
Fig. 8 is for integrating the circuit theory diagrams of output circuit;
Fig. 9 is the block scheme of redundant bit circuit;
Figure 10 is the block scheme of bit aligned circuit.
Embodiment
The present invention realizes that high speed SATA interface data recovers and the circuit module of string and conversion is a full-digital circuit, and referring to Fig. 1, its course of work is as follows: (1) receives the high-speed serial signals of input, obtains 4 tunnel frequency reducing shunting signs.(2) 4 tunnel frequency reducing shunting signs are sampled respectively, then 4 tunnel sampled signals are exported.(3) produce the clock of a clock signal from string line as the subsequent synchronisation circuit.(4) sampled signal after each clock period output is integrated.(5) to the sampled signal of each clock period input, remove wherein unnecessary bit, and significant bit is connected, form a bit sequence data output.(6) these bit sequence data and the synchronization character of doing the view agreement are compared, carry out bit aligned, the output protocol valid data.
Below in conjunction with Figure of description, be described in detail specific embodiments of the invention.
(1) frequency reducing shunt circuit
Referring to Fig. 2, the four-divider of frequency reducing shunt circuit is by d type flip flop 201,202, inverse gate 200,203,204 and Sheffer stroke gate 205-208 form, the high speed serialization input signal is connected to the clk end of d type flip flop 201 respectively, inverse gate 200 and Sheffer stroke gate 205,206 input end, the output terminal of inverse gate 200 is connected to the clk end and the Sheffer stroke gate 207 of d type flip flop 202 respectively, 208 input end, d type flip flop 201,202 output terminal is connected to inverse gate 203 respectively, Sheffer stroke gate 206 and inverse gate 204, the input end of Sheffer stroke gate 208, the output terminal of inverse gate 203 is connected to the input end of d type flip flop 201 and Sheffer stroke gate 205 respectively, the output terminal of inverse gate 204 is connected to the input end of d type flip flop 202 and Sheffer stroke gate 207 respectively, and the output terminal of Sheffer stroke gate 205-208 is connected to 4 sample circuits arranged side by side respectively.
High speed serialization input signal 101 obtains 4 road fractional frequency signals 103,104,105 and 106 through the circuit frequency division.Referring to Fig. 3,4 road fractional frequency signals are all represented the pulse width of the high-low level of serial input signals with low level.The high level pulse width of the 1 road fractional frequency signal 103 and the 3 road fractional frequency signal 105 record serial input signals 101, for example, the high level pulse width ab section of showing input signal 101 with the low level pulse width ab segment table of fractional frequency signal 103, show the high level pulse width cd section of input signal 101 with the low level pulse width cd segment table of fractional frequency signal 105, both are expressions alternately; The low level pulse width of the 2 road fractional frequency signal 104 and the 4 road fractional frequency signal 106 record serial input signals 101, for example, the low level pulse width bc section of showing input signal 101 with the low level pulse width bc segment table of fractional frequency signal 104, show the low level pulse width de section of input signal 101 with the low level pulse width de segment table of fractional frequency signal 106, both also are expressions alternately.
(2) sample circuit
Fig. 4 is a sample circuit 107,108,109 and 110 circuit block diagram.With sample circuit 107 is example, and referring to Fig. 4, serial signal 103～106 obtains signal 403 through the 1/2 bit adjustable unit 402 of delaying time; Successively through the 1 bit adjustable unit 404,406,408,410 of delaying time, obtain signal 405,407,409,411 respectively again.With the latch signal of serial signal 103～106 as bank of latches 412, latch 4 signals such as 405,407,409,411 grades, obtain the latch output signal 111～114 of 4 bit bit wides.Wherein, add 1 as the number of " 0 " in the signal 111, the low level bit width of characterization signal 103 shows that as 1100 signal 103 has the pulsewidth of 3 bits.
Referring to Fig. 5, the signal waveform of circuit as can be known.
Referring to Fig. 6,1/2 bit is delayed time adjustable unit by two or four code translators 600, inverse gate 605,606,609,611 and Sheffer stroke gate 601-604,607,608,610 form, the sampled signal 103-106 of input and 4 signal S0 of two or four code translators 600, S1, S2 and S3 are connected to the input end of Sheffer stroke gate 601-604 respectively, Sheffer stroke gate 601,603 output terminal and Sheffer stroke gate 602,604 output terminal is through inverse gate 605,606 are connected to Sheffer stroke gate 607 respectively, 608) input end, the output terminal of Sheffer stroke gate 607 and Sheffer stroke gate 608 are connected to the input end of Sheffer stroke gate 610 respectively through the output terminal of inverse gate 609, and the output terminal of Sheffer stroke gate 610 exports the described 1 bit adjustable unit of delaying time to through inverse gate 611;
Referring to Fig. 7, the 1 bit adjustable unit of delaying time is made up of inverse gate 712,713 and Sheffer stroke gate 714-716 and 1 the 1/2 bit identical unit, adjustable unit of delaying time, input signal 403 is connected to the input end of Sheffer stroke gate 714 and is connected to the input end of Sheffer stroke gate 715 through inverse gate (713), the output terminal of Sheffer stroke gate 714,715 is connected to the input end of Sheffer stroke gate 716, the output terminal of Sheffer stroke gate 716 inserts the 1/2 bit adjustable unit of delaying time, and its output signal 717 is connected to described latch.
Owing to utilize the time signal of serial signal itself that serial signal is sampled, need carry out time-delay and the time-delay of 1 bit time of 1/2 bit time to signal.For compensation temperature, conditions such as technology have been used the time delay circuit unit of parameter control to the influence of circuit delay in the circuit, obtain more accurate time-delay by setting certain parameter.Referring to Fig. 4, dibit bit wide signal 126 is delay time time delay controlled variable of adjustable unit of 1/2 bit; 3 bit bandwidth signals 127 are delay time time delay controlled variable of adjustable unit of 1 bit.Parameter 126 and 127 is set by microcontroller 125.
Referring to Fig. 6, the time-delay of circuit is by signal 126 controls.Its precision of regulating time-delay is the time delay of 2 reverse swing doors.For the time 333ps of SATA1.0 interface 1/2 bit,, obtain more accurate time-delay through different paths by setting signal 126 control input signals.
Referring to Fig. 7, circuit structure is similar to Fig. 6, has just increased one-level time-delay control.The time-delay of circuit is by parameter signal 127 (comprise 2 bit signal 127[1:0] and 1 bit signal 127[2]) control, and time precision also is the time-delay of 2 inverse gates.For the time 666ps of SATA1.0 interface 1 bit, obtain more accurate time-delay through different paths by setting signal 127 control input signals.
(3) integrate output circuit
Referring to Fig. 8, described 4 tunnel frequency reducing shunting sign 103-106 are connected to the clk end of d type flip flop 801-804 respectively, 4 tunnel sampled data 111-114 are connected to the D end of d type flip flop 801-804 respectively, and the output terminal of d type flip flop 801-804 is exported A, B, four 4 bit signals of C, D respectively;
The 3 road fractional frequency signal 105 is connected to the clk end of d type flip flop 806,809 respectively, and two groups of data-signals of A, D are connected to the D end of d type flip flop 806,809 respectively, and the output terminal of d type flip flop 806,809 is exported AD[7:4 respectively] and AD[3:0] two 8 bit signals;
Signal 105 also is connected to d type flip flop group 810 and 811 corresponding clk ends respectively through the signal of inverse gate 805 outputs, signal AD[7:4], AD[3:0], BC[7:4] and BC[3:0] be connected to d type flip flop group 810 corresponding D ends respectively, the output terminal of d type flip flop group 810 obtains 16 bit signal ABCD[31:16]; Signal ABCD[31:16] be connected to d type flip flop group 811 corresponding D ends respectively, the output terminal of d type flip flop group 811 is exported 16 bit signal ABCD[15:0]; Two 16 bit signal ABCD[31:16] and ABCD[15:0] composition 32 bit bit wide sampled signals 116.
D type flip flop group 801,802,803,804,806,807,808,809,810 and 811 all is that clock is just along the d type flip flop that triggers.
(4) clock generation circuit
Referring to Fig. 8, clock generation circuit is a two-divider.Clock generation circuit 117 is made up of inverse gate 812, d type flip flop 813 and inverse gate 814.Input signal 105 usefulness two divided-frequencies obtain clock signal 118, as the clock signal of subsequent conditioning circuit system.Sampled signal 116 is synchronous with clock signal 118.
Table 1 is the data example that 4 tunnel sampled datas are integrated, and according to the sequencing of time, the sampled data of 4 tunnel 4 bits is integrated into the sampled data of 32 bits.
| 1 the | 2 the | 3 the | 4 the tunnel | |
| First group of input | ????1100 | ????1000 | ????1110 | ????1111 |
| Second group of input | ????1110 | ????1100 | ????1110 | ????1000 |
| Integrate output | ??1100??1000??????????1110??1111??????????1110??1100??????????1110??1000 | |||
Table 1: the data example that sampled data is integrated.
(5) remove the redundant bit circuit
Circuit module of the present invention is done following introduction to known redundant bit circuit and the bit aligned circuit of going with embodiment:
Referring to Fig. 9, go redundant bit circuit 119 to merge circuit 905 and form by change-over circuit 901, significant bit counting circuit 902 and bit.Entire circuit is synchronous with clock signal 118.
1) change-over circuit
Change-over circuit 901 converts the sampled data 116 of 32 bits to the removal redundant bit signal 903 of 32 bits.Here with a concrete instance explanation conversion method.The data 116 of 32 bits are sampled datas of being made up of 84 bits (two groups of front and back, every group 4 tunnel), and for example its form (seeing Table 2) is 1110_1100_1110_1000_1100_1111_1100_1110.Here the conversion method of being narrated is that the sampled data of per 4 bits is changed respectively.Such as, add 1 expression data bit width with the number of " 0 " in last group 1 tunnel sampled data 1110,1110 in the table 2, the bit wide that obtain this moment is 2, and 1 tunnel sampling is high level data, therefore, 2 bit wide position correspondences be exactly 11.Because circuit carries out under the control of clock signal 118, so to the conversion of 84 Bit datas, high level and low level hocket.For last group 2 tunnel sampled datas 1100, the bit wide of obtaining is 3, but because sampling is a low-level data, therefore conversion back result is 000.The rest may be inferred, can obtain all the other 6 data, is listed in the table 2.These data are merged, during 32 of less thaies, the back is with " 0 " polishing again, and 32 bit streams 903 that obtain after the conversion are 11_000_11_0000_111_0_111_00_000000000000, in this example, have mended 12 zero.
| 1 the |
2 the |
3 the |
4 the |
1 the |
2 the |
3 the |
4 the tunnel | |
| Sampled data (116) | 1110 | ?1100 | ?1110 | ?1000 | ?1100 | ?1111 | ?1100 | ?1110 |
| Result after the conversion (903) | 11 | ?000 | ?11 | ?0000 | ?111 | ?0 | ?111 | ?00 |
| Significant bit number (904) | 2 | ?3 | ?2 | ?4 | ?3 | ?1 | ?3 | ?2 |
Table 2: remove in the redundant bit circuit data example of bits switch circuit
2) significant bit counting circuit
The sampled data 116 of 902 pairs of 84 bits of significant bit counting circuit is counted respectively, calculates the number of wherein " 0 ", adds 1 again and is count value.For example,, calculate the number of wherein " 0 " to last group 2 tunnel 4 bit sample data " 1100 ", and add 1 count value is " 3 ", be called the significant bit number, see Table the row of the 3rd in 2.Then total count value 904 is obtained in all counting additions.In the data example of table 2, sampled data bit stream 116 is 1110_1100_1110_1000_1100_1111_1100_1110, and obtaining the significant bit number by calculating is 2_3_2_4_3_1_3_2, is exactly data 904 with these 8 numerical value additions.These preceding 20 of showing bit stream 11_000_11_0000_111_0_111_00_000000000000 after the conversion are number of significant digit (value of signal 904 is 20).
3) bit merges circuit
Data 903 and 904 input bits merge circuit 905.Bit stream is successively imported, and as bit stream 903 being called T clock input (32), then next bit stream is called T+1 clock input (32).Bit merges the significant bit figure place merging of circuit 905 with the bit stream of input of T clock and the input of T+1 clock, is combined into the data-signal 120 (usefulness that less than is 60 " 0 " polishing) of 60 bit bit wides, the output data as 905.For example, the bit stream 903 of T clock input is 11_000_11_0000_111_0_111_00_000000000000, and it contains 20 effective bits; The bit stream 903 of T+1 clock input is 111_00_111_000_11_0_11_00_00000000000000, it contains 18 effective bits, with 20 effective bits of T clock input and 18 effective bit additions of T+1 clock input, obtain 38 effective bits, fill 22 " 0 " again, promptly form the data-signal 120:11_000_11_0000_111_0_111_00_111_00_111_000_11_0_11_0 0_0000000000000000000000 of 60 bit bit wides.The data 120 of 60 bit wides are divided into 6 groups (are one group with 10) from left to right, export 6 useful signals simultaneously and show the 1-10 bit respectively, 11-20 bit, 21-30 bit, 31-40 bit, 41-50 bit, the validity of 51-60 number of bits certificate.Significant bit bit wide 38 shows that preceding 30 is effectively, and 10 of 8 (31 to 38) less thaies of back are inoperative, illustrates that it is effectively that data-signal has only preceding 3 groups, and the back is invalid for 3 groups.Effectively, invalid with 0 expression with 1 expression, be expressed as so will export the data useful signal 121 of 6 bits simultaneously: " 111000 ", in order to the validity of characterization data signal 120.
(6) bit aligned circuit
Referring to Figure 10, bit aligned circuit 122 is made up of regular circuit 1001 of data and alignment bit circuit 1004.Entire circuit is also synchronous with clock signal 118.
1) the regular circuit of data
The regular circuit 1001 of signal 120 (60 bit bit wide) and 121 (6 bit bit wides) input data, each clock period according to data bit useful signal 121 with 120 regular be the data-signal 1002 of 20 bit bit wides; Produce the data useful signal 1003 of 1 bit simultaneously, in order to the validity of characterization data 1002.
Prolong and use precedent, 60 bit signals 120 in the input of T clock are 11,_00,0_1,1_0,000,_11,1_0,_11,1_0,0_1,11_,00_,111,_00,0_1,1_0,_11,_00,_00 00000000000000000000, the regular circuit of data is according to 6 Bit data useful signals 121 " 111000 ", regular output 20 Bit data 1002:11_000_11_0000_111_0_111_00.Preceding 3 of 121 is 1, represents that preceding 30 of 120 data are useful signals, can be regular goes out the data 1002 of 20 bit bit wides, thereby gives 1003 with 1, is effective with characterization data 1002; If signal 121 is 100000, represent that only preceding 10 of 120 data are useful signals, then can not be regular go out the data of 20 bit bit wides, at this moment, can only give 1003 with 0, represent that 1002 is invalid this moment.
2) alignment bit circuit
Continue to prolong and use precedent, imagination is 110001110101_ at effective 20 bit signals 1002 of T-2 clock input
00111110, at effective 20 bit signals 1002 of T-1 clock input be
100101010101_
00011011, at effective 20 bit signals 1002 of T clock input be
11011000100111010100.The bit stream of alignment bit circuit after the T-1 clock is synthetic to T-2 clock and T-1 clock signal carries out the displacement detection of bit-by-bit, can detect synchronization character: "
0011111010_0101010101" (following setting-out is the numeral of single line), the alignment bit is also exported 20 bit synchronous digital data 123, and exporting useful signal 124 simultaneously is 1; Bitstream data 123 after T clock output synchronization character is
0001101111_0110001001(following setting-out is the numeral of two-wire), signal 124 is output as 1, continues thus always.
Technical scheme of the present invention can illustrate, the method that its high speed SATA interface data recovers and goes here and there and change, can realize by totally digitilized circuit, it is restore data fast, and can reduce the scale of circuit and the power consumption of reduction circuit, the parallel agreement valid data of output high speed SATA interface.
Claims (10)
1. a high speed SATA interface data recovers and the method for going here and there and changing, this method is carried out recovery and the string and the conversion of high-speed serial data by the data processing circuit module that contains signal sample circuit, clock generation circuit and clock synchronization circuit, and its method comprises the steps:
1) input: receive high-speed serial signals;
2) frequency reducing along separate routes: with described high-speed serial signals 4 frequency divisions, and obtain 4 tunnel frequency reducing shunting signs respectively;
3) sampling: 4 tunnel frequency reducing shunting signs are sampled respectively, obtain 4 tunnel 4 bit sample data;
4) clock: in step 3), obtain a clock signal that is used for subsequent conditioning circuit from the string line of frequency reducing shunting sign;
5) integrate: 4 tunnel sampled datas are latched, obtain the 32 bit sample data synchronous with clock signal;
6) go redundancy: to described and 32 synchronous bit sample data of clock signal, remove wherein unnecessary bit, and effective bit is connected, obtain the significant bit sequence data of a certain-length and the useful signal of these data;
7) alignment: the synchronizing signal of described significant bit sequence data and Data Transport Protocol is compared, carry out bit aligned, obtain complete agreement valid data, export the useful signal of these data simultaneously;
8) output: the useful signal of described clock signal, agreement valid data and these data that output is obtained.
2. method according to claim 1, wherein, described sampling comprises the steps:
1) each road frequency reducing shunting sign is made 1/2 bit time delays earlier, make 41 bit time delayses more successively, obtain 4 sampled signals;
2) latch this 4 sampled signals with this road frequency reducing shunting sign, obtain 4 tunnel 4 bit sample data.
3. method according to claim 1 and 2, wherein, the described clock signal that is used for subsequent conditioning circuit produces by the 3 tunnel frequency reducing shunting sign being carried out two divided-frequency.
4. method according to claim 3, wherein, described integration comprises the steps:
1) latchs the 3 tunnel sampled data with the 1 road fractional frequency signal; Latch the 4 tunnel sampled data with the 2 road fractional frequency signal; Latch the 1 tunnel sampled data with the 3 road fractional frequency signal; Latch the 2 tunnel sampled data with the 4 road fractional frequency signal;
2) be latched in the two paths of data that latchs in the step 1) respectively with the 3 road fractional frequency signal and its inversion signal; Latch the data of gained again with the 3 road fractional frequency signal, obtain the 32 bit sample data synchronous with clock signal.
5. a high speed SATA interface data recovers and the circuit module of going here and there and changing, comprise redundant bit circuit (119) and coupled bit aligned circuit (122), and the microcontroller (125) of setting the time-delay controlled variable, it is characterized in that: also comprise frequency reducing shunt circuit (102), 4 identical sample circuits (107-110), integrate output circuit (115) and clock generation circuit (117), wherein:
Described frequency reducing shunt circuit (102) is a four-divider, high-speed serial signals is imported described four-divider, its 4 road fractional frequency signal (103-106) is connected to 4 described sample circuits (107-110) respectively, insert described integration output circuit (115) simultaneously, wherein one road fractional frequency signal also is connected to described clock generation circuit (117);
Each described sample circuit (107-110) is made up of 1 1/2 bit that links to each other successively delay time adjustable unit (404,406,408,410) and the latch (412) of adjustable unit (402) and 41 bits of delaying time, described microcontroller (125) and described 1/2 bit adjustable unit (402) and described 4 the 1 bits adjustable unit (404,406,408,410) of delaying time of delaying time links to each other respectively, one of described 4 road fractional frequency signals (103-106) are connected to the described 1/2 bit adjustable unit (402) of delaying time, wherein:
The delay time output signal (403) of adjustable unit (402) of described 1/2 bit is connected to the described 1 bit adjustable unit (404) of delaying time,
The delay time output signal (405) of adjustable unit (404) of described 1 bit is connected to the described 1 bit adjustable unit (406) of delaying time,
The delay time output signal (407) of adjustable unit (406) of described 1 bit is connected to the described 1 bit adjustable unit (408) of delaying time,
The delay time output signal (409) of adjustable unit (408) of described 1 bit is connected to the described 1 bit adjustable unit (410) of delaying time,
The delay time output signal (405,407,409,411) of adjustable unit (404,406,408,410) of described 41 bits is connected to described latch (412) respectively, and 4 bit sample data (111-114) of described latch (412) output are connected to described integration output circuit (115);
Described clock generation circuit (117) is connected to described frequency reducing shunt circuit (102) and described going between redundant bit circuit (119) and the described bit aligned circuit (122), and fractional frequency signal (105) is connected to described clock generation circuit (117) input end; The clock signal of its output (118) is connected to described redundant bit circuit (119) and the described bit aligned circuit (122) of going respectively, and as the clock signal of circuit module;
Described integration output circuit (115) is the d type flip flop group, and 32 synchronous bit sample data (116) of its output and clock signal are connected to the described redundant bit circuit (119) that goes;
The described redundant bit circuit (119) that goes is exported significant bit sequence data (120), and exports the useful signal (121) of these data simultaneously, is connected to described bit aligned circuit (122);
Described bit aligned circuit (122) is exported the parallel agreement valid data (123) of actual transmissions, and exports the useful signal (124) of these data simultaneously.
6. circuit module according to claim 5, it is characterized in that: wherein, described frequency reducing shunt circuit (102) is by d type flip flop (201,202), inverse gate (200,203,204) and Sheffer stroke gate (205-208) form, the high speed serialization input signal is connected to (clk) end of d type flip flop (201) respectively, inverse gate (200) and Sheffer stroke gate (205,206) input end, the output terminal of inverse gate (200) is connected to (clk) end and the Sheffer stroke gate (207 of d type flip flop (202) respectively, 208) input end, d type flip flop (201,202) output terminal is connected to inverse gate (203) respectively, Sheffer stroke gate (206) and inverse gate (204), the input end of Sheffer stroke gate (208), the output terminal of inverse gate (203) is connected to the input end of d type flip flop (201) and Sheffer stroke gate (205) respectively, the output terminal of inverse gate (204) is connected to the input end of d type flip flop (202) and Sheffer stroke gate (207) respectively, and the output terminal of Sheffer stroke gate (205-208) is connected to 4 sample circuits arranged side by side (107-110) respectively.
7. circuit module according to claim 6 is characterized in that: in described sample circuit (107-110),
Described 1/2 bit is delayed time adjustable unit by two or four code translators (600), inverse gate (605,606,609,611) and Sheffer stroke gate (601-604,607,608,610) form, the sampled signal of input and 4 signal (S0 of two or four code translators (600), S1, S2 and S3) be connected to the input end of Sheffer stroke gate (601-604) respectively, Sheffer stroke gate (601,603) output terminal and Sheffer stroke gate (602,604) output terminal is through inverse gate (605,606) be connected to Sheffer stroke gate (607 respectively, 608) input end, the output terminal of Sheffer stroke gate (607) and Sheffer stroke gate (608) are connected to the input end of Sheffer stroke gate (610) respectively through the output terminal of inverse gate (609), and the output terminal of Sheffer stroke gate (610) is through inverse gate (611) output signal (403) to the described 1 bit adjustable unit (404) of delaying time;
The described 1 bit adjustable unit of delaying time is made up of inverse gate (712,713) and Sheffer stroke gate (714-716) and 1 the 1/2 bit identical unit, adjustable unit of delaying time, input signal (403) is connected to the input end of Sheffer stroke gate (714) and is connected to the input end of Sheffer stroke gate (715) through inverse gate (713), the output terminal of not gate (714,715) is connected to the input end of Sheffer stroke gate (716), the output terminal of Sheffer stroke gate (716) inserts the 1/2 bit adjustable unit of delaying time, and its output signal (405) is connected to described latch (412).
8. circuit module according to claim 7 is characterized in that: in described integration output circuit (115),
Described 4 tunnel frequency reducing shunting signs (103-106) are connected to (clk) end of d type flip flop (801-804) respectively, 4 tunnel sampled datas (111-114) are connected to (D) end of d type flip flop (801-804) respectively, and the output terminal of d type flip flop (801-804) is exported (A, B, C, D) four 4 bit signals respectively;
The 3 road fractional frequency signal (105) is connected to (clk) end of d type flip flop (806,809) respectively, (A, D) two groups of data-signals are connected to (D) end of d type flip flop (806,809) respectively, and the output terminal of d type flip flop (806,809) is exported AD[7:4 respectively] and AD[3:0] two 8 bit signals;
Signal (105) is connected to (clk) end of d type flip flop (807,808) respectively through the signal of inverse gate (805) output, two groups of data-signals of B, C are connected to (D) end of d type flip flop (807,808) respectively, and the output terminal of d type flip flop (807,808) is exported BC[7:4 respectively] and BC[3:0] two 8 bit signals;
Signal (105) also is connected to d type flip flop group (810) and (811) corresponding (clk) end respectively through the signal of inverse gate (805) output, signal AD[7:4], AD[3:0], BC[7:4] and BC[3:0] be connected to d type flip flop group (810) corresponding (D) end respectively, the output terminal of d type flip flop group (810) obtains 16 bit signal ABCD[31:16]; Signal ABCD[31:16] be connected to d type flip flop group (811) corresponding (D) end respectively, the output terminal of d type flip flop group (811) is exported 16 bit signal ABCD[15:0];
Two 16 bit signal ABCD[31:16] and ABCD[15:0] composition 32 bit bit wide sampled signals (116).
9. circuit module according to claim 8 is characterized in that: described clock generation circuit (117) is a two-divider, and input signal (105) obtains clock signal (118) through two-divider, as the clock signal output of subsequent conditioning circuit and circuit module.
10. circuit module according to claim 9 is characterized in that: described microcontroller (125) is for being used to set the MCU of delay parameter, and its 2 bit control signal (126) is connected to the described 1/2 bit adjustable unit (402) of delaying time; Its 3 bit control signal (127) is connected to the described 1 bit adjustable unit (404,406,408,410) of delaying time.
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