CN1620047A - Unified platform system of Ethernet exchanger and router - Google Patents
Unified platform system of Ethernet exchanger and router Download PDFInfo
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- CN1620047A CN1620047A CN 200310116721 CN200310116721A CN1620047A CN 1620047 A CN1620047 A CN 1620047A CN 200310116721 CN200310116721 CN 200310116721 CN 200310116721 A CN200310116721 A CN 200310116721A CN 1620047 A CN1620047 A CN 1620047A
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Abstract
本发明涉及网络交换和路由设备，公开了一种以太网交换机和路由器的统一平台系统，使得以太网交换机和路由器在硬件结构上兼容，减少组网设备种类，提高网络维护性，降低组网费用。这种以太网交换机和路由器的统一平台系统包含：CPU，MAC芯片，至少一个以太网接口和至少一个广域网接口；CPU用于对整个系统进行统一管理；MAC芯片用于控制以太网接口和广域网接口的数据传输；以太网接口用于连接外部以太网；广域网接口用于连接外部广域网；CPU通过PCI总线与MAC芯片、广域网接口连接；MAC芯片通过至少一种总线与广域网接口连接；MAC芯片还与以太网接口连接；CPU通过至少一种总线与广域网接口连接。
The invention relates to network switching and routing equipment, and discloses a unified platform system for Ethernet switches and routers, which makes the Ethernet switches and routers compatible in hardware structure, reduces the types of networking equipment, improves network maintainability, and reduces networking costs . This unified platform system of Ethernet switches and routers includes: CPU, MAC chip, at least one Ethernet interface and at least one WAN interface; the CPU is used for unified management of the entire system; the MAC chip is used to control the Ethernet interface and the WAN interface The Ethernet interface is used to connect to the external Ethernet; the WAN interface is used to connect to the external WAN; the CPU is connected to the MAC chip and the WAN interface through the PCI bus; the MAC chip is connected to the WAN interface through at least one bus; the MAC chip is also connected to the WAN interface The Ethernet interface is connected; the CPU is connected with the wide area network interface through at least one bus.
Description
Technical Field
The present invention relates to network switching and routing devices, and more particularly to systems compatible with ethernet switches and routers.
Background
In the current network, ethernet switches and routers are network node devices with wide application, and the network locations are different due to their respective functions, and in the current networking design, the two generally need to be used together.
Specifically, the ethernet switch is a network device that operates on a second layer of an Open System Interconnection (OSI) model, i.e., a data link layer, and implements selection of a path to complete data exchange. The ethernet switch determines a forwarding path according to a Media Access Control (MAC) address of the received packet, thereby implementing a switching function. The Ethernet switch has good openness in terms of self characteristics, has a large number of 10/100/1000BASE-TX/FX Ethernet interfaces, provides strong switching capacity through high-speed forwarding of the second layer, can realize wire-speed switching, and is largely used in the environments of enterprise networks and broadband user access.
A router is a network device that operates on the third layer OSI, the network layer, has the capability of connecting different types of networks, and is capable of selecting a data transfer path. A router typically connects two or more logical ports, identified by Internet Protocol (IP) subnets or point-to-point protocols, with at least 1 physical port. The router determines an output port and a next hop address according to the network layer address in the received data packet and a routing table maintained in the router, so as to realize the forwarding of the data packet. In terms of its characteristics, the user interface of the router is rich in variety and is mostly used for interconnection of different networks. Data and protocol messages of the low-end router are processed by a Central Processing Unit (CPU), so that only low-speed interfaces such as E1/T1 and a MODEM (MODEM) are provided to the outside generally, while the high-end router mostly adopts a Network Processor (NP) structure, and generally provides high-speed interfaces such as ethernet, synchronous digital hierarchy (Packet Over SDH), Asynchronous transmission Mode (Asynchronous Transfer Mode, ATM) and the like. Generally, heterogeneous network interconnection and interconnection of a plurality of subnets are all accomplished by using routers.
Functionally, the gradual convergence of the ethernet switch and the router is a trend of Network device development, and the ethernet switch can provide Wide Area Network (WAN) interfaces such as POS, E1/T1, E3/T3, MODEM, and the like, which are dedicated to the router before; the router may also be configured with an ethernet port such as 10/100/1000 BASE-TX/FX. The integration of the two functions can better meet the requirement of broadband networking.
In practical applications, the above scheme has the following problems: among these network devices, an ethernet switch is difficult to directly access the Internet, and can only be switched through a router, while a low-end router has relatively low performance and low message processing capability, and a high-end router has too high development cost and upgrade cost, and interfaces of both routers have certain limitations and certain limitations in use. Both of these problems add to the cost of networking and the complexity of the equipment.
The main reason for this is that the architecture of the ethernet switch and the router are relatively independent. Ethernet switches lack high-speed WAN interfaces, are difficult to access the Internet directly, and can only be switched through a router. The data and protocol messages of the low-end router are processed by the CPU, so the message processing capacity is low, and therefore, only low-speed interfaces such as E1/T1, MODEM and the like are generally provided for the outside, and high-speed interfaces such as POS, ATM and the like are rarely provided. High-end routers mostly adopt NP structures, but because NP is expensive, development cost and upgrading cost are high, and the high-end routers generally only provide high-speed interfaces such as Ethernet, POS and ATM, and lack specifications of low-speed interfaces such as E1/T1 and MODEM.
Disclosure of Invention
In view of the above, the main objective of the present invention is to provide a unified platform system for ethernet switches and routers, so that the ethernet switches and routers are compatible in terms of hardware structure, and have good expandability and upgradability, so as to reduce the types of networking devices, improve the network maintainability, and reduce the networking cost.
To achieve the above object, the present invention provides a unified platform system of ethernet switch and router, comprising: the system comprises a central processor, a media access control chip, at least one Ethernet interface and at least one wide area network interface;
the central processing unit is used for carrying out unified management on the whole system;
the media access control chip is used for controlling data transmission of the Ethernet interface and the wide area network interface;
the Ethernet interface is used for connecting an external Ethernet; the wide area network interface is used for connecting an external wide area network;
the central processor is connected with the media access control chip and the wide area network interface through a peripheral device interconnection bus; the media access control chip is connected with the wide area network interface through at least one bus; the media access control chip is also connected with the Ethernet interface; the central processor is connected to the wan interface via at least one bus.
The system also comprises an erasable programmable logic device chip, a bus interface and a wide area network interface, wherein the erasable programmable logic device chip is used for providing a slave serial bus under the control of the central processing unit, and the slave serial bus is connected with the wide area network interface;
the erasable programmable logic device chip is connected with the central processing unit through the local bus.
The bus connecting the central processor and the wan interface may comprise any one or a combination of the following bus types:
an inter-integrated circuit bus, or a peripheral component interconnect bus, or a hot-swap bus.
The internal integrated circuit bus is controlled by the central processing unit, and the central processing unit accesses and configures all chips with internal integrated circuit bus interfaces in the system through the internal integrated circuit bus.
The peripheral device interconnection bus is controlled by the central processing unit, and the central processing unit accesses and configures all chips with peripheral device interconnection bus interfaces in the system through the peripheral device interconnection bus.
The wide area network interface is made into a plug board form, supports hot plug operation through the hot plug bus and is configured in the wide area network interface.
The bus connecting the media access control chip and the wide area network interface comprises any one or a combination of the following bus types:
gigabit ethernet bus and management data input output bus.
The gigabit Ethernet bus is responsible for converting the gigabit physical layer chip into a gigabit media independent interface, providing a system side data bus interface for high-speed wide area network interfaces such as synchronous digital series-based data packet exchange and asynchronous transmission modes, converting the gigabit Ethernet bus into a media independent interface through a hundred-megabyte physical layer chip, and providing a system side data bus interface for low-speed wide area network interfaces such as E1/T1.
The management data input and output bus is managed by the media access control chip, and the central processing unit accesses a register related to the management data input and output bus in the media access control chip through a peripheral device interconnection bus, controls the operation of the management data input and output bus and completes the control of all physical layer chips.
Various buses are reserved in the system.
The technical scheme of the invention is different from the prior art in that the invention starts from the perspective of system bus design, combines by using the existing bus or bus extension, provides a complete system bus design, adopts different buses to respectively realize the functions of a management plane and a data plane, and completely realizes the integration of the functions of an Ethernet switch and high and low end routers.
The difference of the technical scheme brings obvious beneficial effects, namely, the unified platform system of the Ethernet switch and the router provided by the invention can be used for developing communication equipment with the functions of the Ethernet switch and the router at the same time, flexibly providing Ethernet ports of various Ethernet switches and WAN interfaces of the router, providing WAN interfaces with abundant types while having huge exchange bandwidth, being capable of being independently applied to various complex networking environments such as metropolitan area network, enterprise network, broadband access, private line and the like, reducing the types and the number of networking equipment, greatly reducing networking cost, facilitating the unified maintenance and management of the network, and better meeting the requirements of broadband networking.
Drawings
FIG. 1 is a diagram of a unified platform system organization of Ethernet switches and routers in accordance with a preferred embodiment of the present invention;
fig. 2 is a Slave-serial bus multiplexing diagram of a unified platform system of ethernet switches and routers in accordance with a preferred embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention will be described in further detail with reference to the accompanying drawings.
As is known, the system bus design of an ethernet switch, or router, determines the hardware architecture of the device, defining the user interface of these communication devices. The invention is mainly characterized in that a hardware platform integrating an Ethernet switch and a router is established from the perspective of system bus design. Through the platform, the communication equipment can provide various WAN interfaces such as a plurality of POS, E1/T1, E3/T3 and MODEM while providing Ethernet interfaces such as 10/100/1000BASE-TX/FX in a large quantity.
The basic principle of the invention is to make the management plane and the data plane in the communication device independent from each other, i.e. different buses are adopted to realize the functions of the management plane and the data plane respectively.
Referring now to fig. 1, the system components of a preferred embodiment of the present invention are described in further detail.
As shown in fig. 1, a unified platform system of ethernet switches and routers according to an embodiment of the present invention comprises: CPU10, MAC chip 20, erasable programmable Logic Device ("EPLD") chip 30, a number of 10/100/1000BASE-TX/FX Ethernet interfaces 40 and a number of WAN interfaces 50.
The CPU10 is connected to the MAC chip 20 and all WAN interfaces 50 via a Peripheral Component Interconnect (PCI) bus; the CPU10 is connected to the EPLD chip 30 via a Local Bus; the CPU10 is connected to all WAN interfaces 50 via a Hot-plug (Hot-Swap) bus; the CPU10 is connected to all WAN interfaces 50 via an Inter-integrated circuit ("I2C") bus; the EPLD chip 30 is connected to all WAN interfaces 50 via a Slave-serial bus; the MAC chip 20 is connected to all WAN interfaces 50 through a Management Data Input Output (MDIO) bus; the MAC chip 20 is connected to all WAN interfaces 50 via Gigabit Ethernet (GE for short) bus; the MAC chip 20 is connected to all 10/100/1000BASE-TX/FX ethernet interfaces 40 via Media Independent Interfaces (MII), Serial Media Independent Interfaces (SMII), and the like.
The CPU10 is a core of a management plane for performing unified management of devices, and externally provides an I2C bus, a PCI bus, a local bus, and a Hot-Swap bus. For example, in a preferred embodiment of the present invention, CPU10 manages MAC chip 20 and all WAN interfaces 50 through the PCI bus.
The MAC chip 20 is a core of a data plane and is configured to provide a plurality of 10/100/1000BASE-TX/FX ethernet interfaces 40 through MII, SMII, and the like, and to externally provide a GE bus and an MDIO bus. The 10/100/1000BASE-TX/FX Ethernet interfaces 40 and the GE bus interfaces are determined by the type and number of the MAC chip 20.
The EPLD chip 30 is used to provide a Slave-serial bus under the control of the CPU 10. The Slave-serial bus may be used as a serial port for loading field programmable Gate arrays (FPGAs for short) in various WAN interfaces 50.
10/100/1000BASE-TX/FX Ethernet interface 40 is used to provide an Ethernet interface. As described above, 10/100/1000BASE-TX/FX Ethernet interface 40 is provided directly by MAC chip 20 via MII, SMII, etc. interfaces, the specific number of which is determined by the model and number of MAC chip 20. In a preferred embodiment of the present invention, the 10/100/1000BASE-TX/FX Ethernet interface 40 does not occupy PCI bus bandwidth and allows wire-speed switching. In addition, 10/100/1000BASE-TX/FX Ethernet interface 40 may take various forms such as 24 Fast Ethernet (FE) ports, 48 FE ports, 10 GE ports, etc.
The WAN interface 50 is used to provide Hot plug (Hot-Swap) enabled slots compatible with various WAN interface cards. In a preferred embodiment of the present invention, the number of WAN interfaces 50 is determined by the number of GE bus interfaces provided by MAC chip 20, and does not occupy the PCI bus bandwidth. The high-speed WAN interface system side may be connected to the GE bus through FPGA logic, a physical layer (PHY) chip, etc., without being limited by the specific system side interface of the WAN interface 50 itself. The system side interface of the low-speed WAN interface may be a PCI bus or an MII interface converted from a GE bus.
The functions of the PCI bus, Local bus, GE bus, I2C bus, MDIO bus, Slave-serial bus, and Hot-Swap bus in the unified platform system of ethernet switches and routers according to a preferred embodiment of the present invention will be further described with reference to fig. 1.
With respect to the PCI bus, in the present embodiment, the CPU10 controls the PCI bus and is responsible for arbitration of the PCI bus. Specifically, the PCI bus has the following three functions: firstly, a management bus interface of an MAC chip 20 in the communication equipment is provided; secondly, a system side management bus interface of high-speed WAN interfaces such as POS, ATM and the like is provided; and thirdly, a system side data bus and a management bus interface for providing low-speed WAN interfaces such as E1/T1, MODEM and the like.
It should be noted that, in this embodiment, the PCI bus is compatible with the following specifications:
local Bus Specification (version 2.1) — Local Bus Specification (version 2.1);
PCI Local Bus Specification (Vision 2.2) -peripheral interconnect Local Bus Specification (version 2.2);
PCI-to-PCI Bridge Specification (replacement 1.1) — "peripheral component interconnect bus Bridge Specification (version 1.1);
PCI Bus Power Management Interface Specification (version 1.1) — "peripheral component interconnect Bus Power Management Interface Specification (version 1.1);
PICMG compact PCI Hot-Swap Specification (version 1.0) — peripheral component interconnect bus Industrial computer manufacturers group reduced peripheral component interconnect bus Hot plug Specification (version 1.0) ".
For the Local bus, which is controlled by the CPU10 in this embodiment, a management bus interface of the EPLD chip 30 in the communication device is provided.
For the GE bus, it is controlled by the MAC chip 20 and ethernet is used in this embodiment. The 1.25G differential line pair used for 1000BASE-FX has the following signal definition:
| name of signal | Signal definition |
| TX+ | Sending is |
| TX- | Sending a negative |
| RX+ | Receive positive |
| RX- | Receiving negative |
Functionally, the GE bus is responsible for converting into a Gigabit Media Independent Interface (GMII for short) through a Gigabit PHY chip, and provides a system side data bus Interface for high-speed WAN interfaces such as POS and ATM; and on the other hand, the system is responsible for converting the signals into MII interfaces through hundred mega PHY chips, and provides a system side data bus interface for low-speed WAN interfaces such as E1/T1.
In the present invention, the GE bus may use Emitter Coupled Logic (ECL) level, or Current Mode Logic (CML) level.
For the I2C bus, in the present invention, the CPU10 controls the I2C bus, and is responsible for arbitration of the I2C bus. Specifically, the CPU10 accesses and configures all chips with I2C bus interfaces in the system via the I2C bus.
The signals of the I2C bus are defined as the following table:
| name of signal | Signal definition |
| I2CCLK | I2C bus clock line |
| I2CDATE | I2C bus data line |
| I2CAD | I2C bus address line |
It should be noted that, in the present invention, since the I2C bus addresses sent to different WAN interface boards cannot be repeated, each WAN interface board has an independent address signal I2CAD, and each set of I2CAD signals sets different fixed values on the motherboard of the communication device. The specific number of address signals I2CAD is determined by the specific design and is not limited.
For the MDIO bus, the MDIO bus is a control bus for the internal registers of the PHY chip. In a preferred embodiment of the present invention, all the two-layer switching, GE bus to GMII interface and MII interface conversion, is performed by the PHY chip. The MAC chip 20 is responsible for managing the MDIO bus, and the CPU10 accesses the register in the MAC chip related to the MDIO bus through the PCI bus to control the operation of the MDIO bus, thereby completing the control of all PHY chips.
The signals of the MDIO bus are defined as the following table:
| name of signal | Signal definition |
| MDIOCLK | MDIO bus clock line |
| MDIODATE | MDIO bus data line |
| MDIOAD | MDIO bus address line |
Like the I2C bus, because the MDIO bus addresses sent to different WAN interface cards cannot be repeated, each WAN interface card has an independent address signal MDIOAD, and each set of MDIOAD signals sets a different fixed value on the motherboard of the communication device. The specific number of the address signals MDIOAD is determined by the specific design and is not limited.
For the Slave-serial bus, it is generated by the EPLD chip 30 where the system logic of the communication device resides. It can be used as the loading slave-serial port of FPGA in various WAN interfaces. And the CPU controls a register which is inside the EPLD and is related to the Slave-serial bus, generates a time sequence of a Slave string on the Slave-serial bus and finishes the loading of the FPGA.
SlaThe signals of the ve-serial bus are defined as the following table:
| name of signal | Signal definition |
| DIN | Loading logic data input signals |
| PROG | Low active signal, asynchronous reset load logic |
| DONE | Bidirectional signal, output indicating end of loading |
| CCLK | Configuring the clock to input the signal in the slave-string mode |
| WAN_SELECT | WAN socket slave string selection signal |
The system multiplexes DIN, PROG, DONE, CCLK and other signals by controlling the state of the WAN _ SELECT signal and loads the FPGA on the WAN interface plug board. The Slave-serial bus multiplexing is shown in fig. 2.
Each WAN interface board has a separate electronic switch. DIN, PROG, DONE, CCLK and other signals are loaded to FPGA on WAN interface plug board through the electronic switches. The switch state of the electronic switch is controlled by the WAN _ SELECT signal. The CPU10 of the communication device controls the state of the respective WAN _ SELECT signals.
For the Hot-Swap bus, it should be noted that the communication device can only provide a limited number of WAN interface slots to the outside due to its limited size. In order to be flexibly networked, these slots must be compatible with various WAN interfaces. In a preferred embodiment of the invention, the WAN interfaces are implemented on boards that support hot-plugging. Wherein, the Hot plug process of the plugboard is controlled by a Hot-Swap bus.
The Hot-Swap bus signals are defined as follows:
| name of signal | Signal definition |
| PRESENT | Plugboard in-place signal |
| ON | Power-on enable signal of plugboard |
| HEALTH | Normal signal of power-on of plug board |
In a preferred embodiment of the present invention, each slot has a separate set of hot plug control signals.
Those skilled in the art will appreciate that the board may be derived from the PCI bus via a south bridge if a local bus (LOCALBUS) is desired.
While the invention has been shown and described with reference to certain preferred embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined by the appended claims.
Claims (10)
1. A unified platform system of ethernet switches and routers, comprising: the system comprises a central processor, a media access control chip, at least one Ethernet interface and at least one wide area network interface; wherein,
the central processing unit is used for carrying out unified management on the whole system;
the media access control chip is used for controlling data transmission of the Ethernet interface and the wide area network interface;
the Ethernet interface is used for connecting an external Ethernet;
the wide area network interface is used for connecting an external wide area network; and,
the central processor is connected with the media access control chip and the wide area network interface through a peripheral device interconnection bus; the media access control chip is connected with the wide area network interface through at least one bus; the media access control chip is also connected with the Ethernet interface; the central processor is connected to the wan interface via at least one bus.
2. The unified platform system of ethernet switches and routers, according to claim 1, further comprising an erasable programmable logic device chip for providing a slave serial bus under control of said central processor, said slave serial bus interfacing with said wide area network;
the erasable programmable logic device chip is connected with the central processing unit through a local bus.
3. The unified platform system of ethernet switches and routers, according to claim 1, wherein said bus connecting said central processor and said wide area network interface comprises any one or combination of the following bus types:
an inter-integrated circuit bus, or a peripheral component interconnect bus, or a hot-swap bus.
4. The unified platform system of ethernet switches and routers, according to claim 3, wherein said inter-integrated circuit bus is controlled by said central processing unit, said central processing unit accessing and configuring all chips with inter-integrated circuit bus interface in the system through the inter-integrated circuit bus.
5. The unified platform system for ethernet switches and routers, according to claim 3, wherein said peripheral component interconnect bus is controlled by said central processing unit, said central processing unit accessing and configuring all chips with peripheral component interconnect bus interface in the system through the peripheral component interconnect bus.
6. The unified platform system for ethernet switches and routers, according to claim 3, wherein said wan interface is in form of a plug board and supports hot plug operation through said hot plug bus, configured in said wan interface.
7. The unified platform system of ethernet switches and routers, according to claim 1, wherein said bus connecting said mac chip and said wan interface comprises any one or a combination of the following bus types:
gigabit ethernet bus and management data input output bus.
8. The unified platform system for ethernet switches and routers, according to claim 7, wherein said gigabit ethernet bus is configured to be converted to a gigabit media independent interface via a gigabit physical layer chip, and provide a system side data bus interface for high speed wan interfaces such as synchronous digital hierarchy-based packet switching and asynchronous transfer mode, and a gigabit physical layer chip, and convert to a media independent interface, and provide a system side data bus interface for low speed wan interfaces such as E1/T1.
9. The unified platform system for ethernet switches and routers, according to claim 7, wherein said management data input/output bus is managed by said mac chip, and said cpu accesses a register related to said management data input/output bus in said mac chip through a peripheral device interconnection bus to control the operation of said management data input/output bus, thereby completing the control of all physical layer chips.
10. The unified platform system of ethernet switches and routers according to any of claims 1 to 9, wherein various said buses are reserved in said system.
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| CN 200310116721 CN1620047A (en) | 2003-11-18 | 2003-11-18 | Unified platform system of Ethernet exchanger and router |
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|---|---|---|---|
| CN 200310116721 CN1620047A (en) | 2003-11-18 | 2003-11-18 | Unified platform system of Ethernet exchanger and router |
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Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100461734C (en) * | 2006-12-28 | 2009-02-11 | 杭州华三通信技术有限公司 | Communication equipment with LAN/WAN port switching function and implementation method |
| CN101325551B (en) * | 2008-07-28 | 2010-09-22 | 杭州华三通信技术有限公司 | Method and device for processing message |
| CN1794673B (en) * | 2005-12-27 | 2011-11-30 | 王卫亚 | Method of constructing local network using IP protocol |
| CN102299811A (en) * | 2010-06-24 | 2011-12-28 | 创锐讯通讯技术（上海）有限公司 | Method for remotely managing user side equipment by using local side equipment |
| CN102771093A (en) * | 2010-02-22 | 2012-11-07 | 日本电气株式会社 | Communication control system, switching node, communication control method and communication control program |
| CN104283712A (en) * | 2014-10-13 | 2015-01-14 | 杭州华三通信技术有限公司 | Network equipment and management internet port configuration method for same |
| CN106301660A (en) * | 2016-07-30 | 2017-01-04 | 成都欧飞凌通讯技术有限公司 | The 40G POS association of a kind of high integration turns hardware and realizes structure |
| CN107959643A (en) * | 2017-12-29 | 2018-04-24 | 曙光信息产业(北京)有限公司 | A kind of exchange system and its routing algorithm built by exchange chip |
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- 2003-11-18 CN CN 200310116721 patent/CN1620047A/en active Pending
Cited By (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1794673B (en) * | 2005-12-27 | 2011-11-30 | 王卫亚 | Method of constructing local network using IP protocol |
| CN100461734C (en) * | 2006-12-28 | 2009-02-11 | 杭州华三通信技术有限公司 | Communication equipment with LAN/WAN port switching function and implementation method |
| CN101325551B (en) * | 2008-07-28 | 2010-09-22 | 杭州华三通信技术有限公司 | Method and device for processing message |
| CN102771093A (en) * | 2010-02-22 | 2012-11-07 | 日本电气株式会社 | Communication control system, switching node, communication control method and communication control program |
| CN102771093B (en) * | 2010-02-22 | 2014-12-10 | 日本电气株式会社 | Communication control system, switching node, and communication control method |
| US9047416B2 (en) | 2010-02-22 | 2015-06-02 | Nec Corporation | Communication control system, switching node, communication control method and communication control program including PCI express switch and LAN interface |
| CN102299811A (en) * | 2010-06-24 | 2011-12-28 | 创锐讯通讯技术（上海）有限公司 | Method for remotely managing user side equipment by using local side equipment |
| CN104283712A (en) * | 2014-10-13 | 2015-01-14 | 杭州华三通信技术有限公司 | Network equipment and management internet port configuration method for same |
| CN104283712B (en) * | 2014-10-13 | 2017-10-27 | 新华三技术有限公司 | The network equipment and the management network port collocation method for the network equipment |
| CN106301660A (en) * | 2016-07-30 | 2017-01-04 | 成都欧飞凌通讯技术有限公司 | The 40G POS association of a kind of high integration turns hardware and realizes structure |
| CN107959643A (en) * | 2017-12-29 | 2018-04-24 | 曙光信息产业(北京)有限公司 | A kind of exchange system and its routing algorithm built by exchange chip |
| CN107959643B (en) * | 2017-12-29 | 2021-05-14 | 曙光信息产业(北京)有限公司 | Switching system constructed by switching chip and routing algorithm thereof |
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