CN1619959A - Phase delay circuit and method - Google Patents

Abstract

The invention provides a phase delay circuit, is used for delaying an input signal in order to produce an output signal, the phase delay circuit includes a buffer, is used for buffering the input signal that is input in its input end, in order to produce the output signal at the carry-out terminal; a digital-to-analog converter for converting a digital phase delay value inputted from its input terminal into a control voltage and outputting it; and a variable capacitor for changing the capacitance of the variable capacitor according to the control voltage; wherein the phase delay circuit can change the phase delay between the input signal and the output signal by changing the capacitance value.

Description

Phase delay circuit and method

technical field

The invention provides a phase delay circuit, especially a phase delay circuit capable of phase compensation.

Background technique

In many circuits, such as a clock generator (clock generator) or a radio frequency transmission receiver (RF transceiver), the requirements for the accuracy of the signal phase are quite high. When these signal phases deviate, it will have a considerable impact on the entire system. big impact. As for the multi-phase clock signal generator (multi-phase clock generator), the accuracy of the phase difference between each output signal is also very important. When the phase error increases, the clock jitter of the output clock signal will also increase. , which may lead to serious errors in subsequent circuits for systems that require precise clock signals, such as errors in sampling points of analog-to-digital converters, or increases in bit error rates, etc.

Careful attention is paid to these layout paths that require precise phase accuracy when designing circuits. However, when factors such as temperature, manufacturing process, and supply voltage drift cannot be fully grasped, conventional integrated circuits generally cannot provide accurate phase accuracy. Phase delay, at this time, it is necessary to use an additional mechanism to correct the phase offset.

One of the known phase shifting techniques is to use the charging and discharging effect of the capacitor to perform RC delay on the signal to be transmitted to the next stage. Usually, a plurality of switches are used to control a plurality of capacitors to adjust the capacitance value, and use the Capacitor value and a buffer to provide RC delay to make the phase delay of the signal. Please refer to FIG. 1 , which is a schematic diagram of a phase delay circuit 100 in the prior art. The phase delay circuit 100 includes a plurality of capacitors, a plurality of switches and a buffer for delaying an input signal to generate an output signal. The phase delay circuit 100 utilizes a plurality of switches to adjust the capacitance of a node N of the circuit by turning on or off the switches. When more switches are turned on and the equivalent capacitance of the node N is larger, the input signal The amount of delay will increase.

In order to carry out precise phase delay control on the transmitted signal, it is preferable to make the capacitance and resistance formed by the above-mentioned multiple switches very small compared with the capacitance of these multiple capacitors and the resistance of the buffer. Negligible value. Because if the parasitic capacitance and resistance of the switch are too large, the RC delay of the signal before and after the switch will be affected unpredictablely, which is undesirable in circuit design.

However, with the advancement of the application technology field, the requirement for more precise control of the signal phase delay is increasing day by day, and the value of the capacitor and resistor used to provide the RC delay is getting smaller and smaller. Under such circumstances, generally The switch realized by MOS transistor will face the following problems: on the one hand, in order to reduce the parasitic capacitance value of the switch, the smaller the size of the MOS transistor used for the switch, the better, but on the other hand, in order to make the resistance value of the switch The size of the above-mentioned MOS transistors should be as large as possible. This will cause difficulties in the design of the phase delay circuit 100 .

Contents of the invention

Therefore, the main object of the present invention is a circuit and method for converting the digital phase delay value into a digital control voltage to control a variable capacitor and a buffer to delay an input signal to generate an output signal.

The invention provides a phase delay circuit for delaying an input signal to generate an output signal. The phase delay circuit includes a buffer for buffering the input signal input at its input to generate the output signal at the output; a digital-to-analog converter for converting a digital phase input at its input The delay value is converted into a control voltage output; and a variable capacitor is used to change the capacitance value of the variable capacitor according to the control voltage; wherein by changing the capacitance value, the phase delay circuit can change the input signal and the output Phase delay between signals.

Description of drawings

FIG. 1 is a schematic diagram of a phase delay circuit in the prior art.

FIG. 2 is a functional block diagram of the phase delay circuit of the present invention.

FIG. 3 is a flow chart of the phase delay of the phase delay circuit of the present invention.

Description of reference symbols

100, 200 Phase delay circuit 10, 20 Buffer

11, 12, 13, capacitors 15, 16, 17, 18 switches

14

21 Digital to Analog Converter 22 Variable Capacitor

Detailed ways

The method and structure disclosed in the present invention take FIG. 2 as an example, in order to improve the accuracy of the phase delay circuit by digitally recording the required phase delay value and the assistance of the digital-to-analog converter.

Please refer to FIG. 2 . FIG. 2 is a functional block diagram of a phase delay circuit 200 of the present invention for delaying a signal. The phase delay circuit 200 in FIG. 2 includes a buffer 20 , a digital-to-analog converter 21 and a variable capacitor 22 . The buffer 20 has an input terminal and an output terminal, and is used for buffering the input signal input at its input terminal, so as to generate the output signal at the output terminal, which can be used to receive a clock signal output by a clock signal generator, Or a signal output by a radio frequency transceiver. Digital to Analog Converter (Digital to Analog Converter, DAC for short) 21 has an input terminal and an output terminal, and is used for converting a digital phase delay value input at its input terminal into a control voltage output, which can be used to convert a The input digital phase delay value is converted into a control voltage output. The variable capacitor 22 has two terminals, one of which is electrically connected to the output terminal of the digital-to-analog converter 21, and the other terminal is electrically connected to the output terminal of the buffer 20, and is used to change the capacitance of the variable capacitor 22 according to the control voltage. value. The variable capacitor 22 can be a MOS voltage-controlled capacitor or a P+/N well junction voltage-controlled capacitor (P+/N well junction voltage-controlled capacitor), which is used to change the capacitance of the variable capacitor 22 according to the control voltage value.

It should be noted that the present invention can also be realized by using two sets of the above-mentioned circuits, and the two sets of circuits respectively adjust the phases of the two input signals to adjust the phase difference between the two input signals. The two input signals may be a pair of differential signals, or I/Q signals of a radio frequency receiver (receiver) and a transmitter (transmitter) of the communication system.

FIG. 3 is a flow chart of using the phase delay circuit 200 of the present invention to perform phase delay. The operation process includes the following steps:

Step 200: start;

Step 202: The input terminal of the buffer 20 receives an input signal;

Step 204: The input terminal of the digital-to-analog converter 21 receives a digital phase delay value, and converts the digital phase delay value into a control voltage, and then outputs it at its output terminal;

Step 206: The variable capacitor 22 receives the control voltage, and the control voltage controls the variable capacitor 22 so that the variable capacitor 22 has a capacitance value corresponding to the digital phase delay value;

Step 208: using the variable capacitor 22 and a buffer 20 to delay the input signal to generate the output signal at the output end of the buffer 20; and

Step 210: End the phase delay operation, completing an embodiment of the phase delay process of the present invention.

Since the variable capacitor will reflect different capacitances for different voltages (that is, the capacitance value of the variable capacitor changes with the voltage values at both ends), therefore, if the voltage of the variable capacitor can be controlled at a specific precise Degree, you can get the capacitance of the corresponding resolution. With the current technology, it is not difficult to control the variable capacitor with a digital-to-analog converter, and it is not difficult to subdivide the control voltage to a higher resolution, so the accuracy of the phase delay can be greatly improved. Moreover, since the digital-to-analog converter receives the phase delay value recorded in digital form, more detection methods can be adopted in the phase error detection method of the previous stage.

The above descriptions are only preferred embodiments of the present invention, and all equivalent changes and modifications made according to the claims of the present invention shall fall within the scope of the present invention.

Claims (9)

1. phase-delay network includes:

One buffer is used to cushion an input signal, and exports an output signal;

One digital analog converter is used for exporting a corresponding control voltage according to a digit phase length of delay; And

One variable capacitance couples with this digital analog converter and this buffer respectively, and wherein, the capacitance of this variable capacitance is corresponding with this control voltage;

Wherein by this capacitance of control, this phase-delay network can be adjusted the phase delay of this input signal and this output signal.

2. the method for claim 1, wherein this variable capacitance is a voltage controlled capacitor, this voltage controlled capacitor is a MOS voltage controlled capacitor, or is a P+/N type trap junction type voltage controlled capacitor.

3. the method for a phase retardation, the method includes the steps of:

Produce a corresponding control voltage according to a digit phase length of delay; And

Cushion an input signal, to export an output signal;

Wherein, utilize the capacitance of this control voltage control one variable capacitance, to adjust the phase difference of this input signal and this output signal.

4. method as claimed in claim 3 wherein produces corresponding this control voltage steps according to this digit phase length of delay and is realized by a digital analog converter.

5. method as claimed in claim 3, wherein this variable capacitance is a voltage controlled capacitor, this voltage controlled capacitor is a MOS voltage controlled capacitor, or is a P+/N type trap junction type voltage controlled capacitor.

6. phase-delay network includes:

One first buffer is used to cushion one first input signal, and exports one first output signal;

One first digital analog converter is used for exporting corresponding one first control voltage according to a digit phase length of delay; And

One first variable capacitance couples with this first digital analog converter and this first buffer respectively, and wherein, the capacitance of this first variable capacitance is corresponding with this first control voltage;

One second buffer is used to cushion one second input signal, and exports one second output signal; One second digital analog converter is used for exporting corresponding one second control voltage according to this digit phase length of delay; And

One second variable capacitance couples with this second digital analog converter and this second buffer respectively, and wherein, the capacitance of this second variable capacitance is corresponding with this second control voltage;

Wherein by control this first capacitance or this second capacitance or both, this phase-delay network can adjust this first input signal and this second phase of input signals is poor.

7. method as claimed in claim 6, wherein this first input signal and this second input signal are the pair of differential signal.

8. method as claimed in claim 6, wherein this first input signal and this second input signal are respectively an in-phase signal (I signal) and 1/1st phase signal (Q signal).

9. method as claimed in claim 6, wherein this variable capacitance is a voltage controlled capacitor, this voltage controlled capacitor is a MOS voltage controlled capacitor, or is a P+/N type trap junction type voltage controlled capacitor.