CN1619807B - Substrates including integrated circuit chips and integrated circuits thereon - Google Patents

Abstract

An integrated circuit chip, a packaging structure thereof and a flat panel display device are provided. The integrated circuit packaging structure comprises an integrated circuit chip, an insulating substrate and a film layer. The integrated circuit chip is provided with a chip body and a plurality of metal bumps. The metal bumps are arranged on the first surface of the chip body, and each metal bump is provided with a patterned laminating surface. The insulating substrate is provided with a plurality of electrode pads respectively corresponding to the metal bumps, and each electrode pad is provided with a second surface. The glue film layer is arranged between the integrated circuit chip and the insulating substrate and covers the metal bumps and the electrode pads. In addition, a plurality of electric conductor patterns are arranged on the laminating surface or the corresponding second surface.

Description

Substrates including integrated circuit chips and integrated circuits thereon

technical field

The present invention relates to an integrated circuit chip, its construction structure and a flat display device, in particular to an integrated circuit chip which is suitable for bonding on glass (COG) construction technology without using anisotropic conductive film (ACF) and its Construct structure.

Background technique

Currently common flat panel display devices, such as liquid crystal displays (LCDs) or plasma displays (PDPs), all use semiconductor components such as integrated circuit (IC) chips to control the display of images. In the assembly of IC chips, a Chip-On-Glass (COG) assembly structure is commonly used at present, and its structure is to directly assemble the driver IC chip on the insulating substrate of the flat panel display device.

Please refer to FIG. 1A and FIG. 1B , illustrating the existing IC chip COG assembly structure. As shown in FIG. 1A , a plurality of metal bumps 210 are disposed on the IC chip 20 , and electrode pads 110 corresponding to the metal bumps 210 are disposed on the insulating substrate 10 . When assembling, an anisotropic conductive film (Anisotropic Conductive Film, ACF) 30 containing conductive particles 310 is coated on the insulating substrate 10, and then the IC chip 20 is pressed onto the insulating substrate 10, as shown in FIG. 1B, Appropriate pressure, temperature and time control are applied, so that the insulating substrate 10 and the IC chip 20 are bonded through the anisotropic conductive film 30, and the corresponding metal bump 210 and the electrode pad 110 pass through the conductive particles 310 to generate electricity. sexual conduction. Generally speaking, the protruding lengths of each metal bump 210 are substantially equal, and the pressing surfaces thereof are usually set as a plane, so that it is easier to ensure the uniformity of the pressing.

However, the conductive particles 310 contained in the anisotropic conductive film 30 are not necessarily uniformly distributed, and the density of the conductive particles 310 may be low or high in some areas. The uneven distribution of the conductive particles 310 causes problems.

For example, as shown in FIG. 1C , when the IC chip 20 is bonded to the insulating substrate 10, if the anisotropic conductive film 30 between the metal bump 210 and the electrode pad 110 does not contain conductive particles 310 just like the region A , the impedance between the metal bump 210 and the electrode pad 110 is too large, and the electrical conduction cannot be effectively formed.

In addition, as shown in FIG. 1D, when the IC chip 20 is bonded to the insulating substrate 10, if the conductive particles 310 are densely distributed in a certain area of the anisotropic conductive film 30, that is, as in area B, adjacent metal bumps may be formed. Block 210 generates a short circuit, thereby affecting the transmission of the control signal.

In addition, due to the addition of conductive particles 310, the material cost of the anisotropic conductive film 30 is not low, and the size of the gap between the metal bump 210 and the electrode pad 110 is affected by the particle size of the conductive particles 310 (for example, the conductive particles can be limited by particles with a diameter of 5 microns), it is impossible to set the lines more densely. In addition, the uneven distribution of the above-mentioned conductive particles 310 may not effectively form electrical conduction as shown in FIG. 1C or cause a short circuit as shown in FIG. 1D , but local impedance increase or poor electrical conduction may still occur. Phenomenon.

Contents of the invention

In view of this, an object of the present invention is to propose an integrated circuit chip and its assembly structure, which improves the existing COG assembly technology so that it can be assembled without using an anisotropic conductive film. The problems that occur in the existing COG construction technology can be avoided.

The invention discloses an integrated circuit chip, which includes a chip body, a plurality of metal bumps and a plurality of electrical conductor patterns. The chip body has a first surface, the metal bumps are arranged on the first surface of the chip body, and each metal bump has a patterned bonding surface. A plurality of electrical conductor patterns are respectively arranged on the pressing surface.

In addition, the invention also discloses an integrated circuit assembly structure, which includes an integrated circuit chip, an insulating substrate and an adhesive film layer. The integrated circuit chip has a chip body and a plurality of metal bumps. The metal bumps are disposed on the first surface of the chip body, and each metal bump has a pressing surface. The insulating substrate has a plurality of electrode pads respectively corresponding to the metal bumps, and each electrode pad has a second surface. The adhesive film layer is disposed between the integrated circuit chip and the insulating substrate, and covers the metal bumps and the electrode pads. Wherein, a plurality of electrical conductor patterns are arranged on the pressing surface or the second surface.

In addition, the present invention also discloses a plane display device, which includes a driver IC, a display panel and an adhesive film layer. The driving IC has a chip body and a plurality of metal bumps, the metal bumps are arranged on a surface of the chip body, and each metal bump has a pressing surface. The display panel has a plurality of electrode pads respectively corresponding to the metal bumps, and each electrode pad has a second surface. The adhesive film layer is disposed between the driving integrated circuit chip and the display panel, and covers the metal bumps and the electrode pads. Wherein, a plurality of electrical conductor patterns are arranged on the pressing surface or the second surface.

In each aspect of the present invention above, the electrical conductor pattern can be hemispherical or other shapes suitable for manufacturing, and the diameter of the electrical conductor pattern is generally 3-15 microns.

In addition, the invention also discloses an integrated circuit assembly structure, which includes an integrated circuit chip, an insulating substrate and an adhesive film layer. The integrated circuit chip has a chip body and a plurality of metal bumps. The metal bumps are disposed on the first surface of the chip body, and each metal bump has a bonding surface, wherein a plurality of first electrical conductor patterns are disposed on the bonding surface. The insulating substrate has a plurality of electrode pads respectively corresponding to the metal bumps, and each electrode pad has a second surface, wherein a plurality of second electrical conductor patterns are arranged on the second surface. The adhesive film layer is disposed between the integrated circuit chip and the insulating substrate, and covers the metal bumps and the electrode pads.

In addition, the present invention also discloses a plane display device, which includes a driver IC, a display panel and an adhesive film layer. The driver IC has a chip body and a plurality of metal bumps, the metal bumps are arranged on a surface of the chip body, and each metal bump has a bonding surface, wherein a plurality of first electrical conductors are arranged on the bonding surface pattern. The display panel has a plurality of electrode pads respectively corresponding to the metal bumps, and each electrode pad has a second surface, wherein a plurality of second electrical conductor patterns are arranged on the second surface. The adhesive film layer is disposed between the driving integrated circuit chip and the display panel, and covers the metal bumps and the electrode pads.

In each form of the present invention above, the first electrical conductor pattern and the second electrical conductor pattern can be metal particles or a plurality of grooves correspondingly embedded in the metal particles, and their shapes can be hemispherical or other shapes suitable for manufacturing, And its diameter is generally 3-15 microns is preferred.

In order to make the above and other objects, features and advantages of the present invention more comprehensible, several specific preferred embodiments are specifically cited below and described in detail with accompanying drawings.

Description of drawings

FIG. 1A is a schematic diagram of a conventional bonding-on-glass (COG) assembly structure before bonding;

FIG. 1B is a schematic diagram of the COG assembly structure of FIG. 1A after bonding;

FIG. 1C is a schematic diagram of poor joint of the COG construct structure of FIG. 1A;

Figure 1D is a schematic diagram of a short circuit occurring in the COG structure of Figure 1A;

Fig. 2 is a schematic diagram of the integrated circuit chip structure of the first embodiment of the present invention;

3 is a schematic diagram of an integrated circuit assembly structure according to a second embodiment of the present invention;

4 is a schematic diagram of an integrated circuit assembly structure according to a third embodiment of the present invention;

5 is a schematic diagram of an integrated circuit assembly structure according to a fourth embodiment of the present invention;

FIG. 6 is a schematic diagram of an integrated circuit assembly structure according to a fifth embodiment of the present invention;

FIG. 7 is a schematic diagram of an integrated circuit assembly structure according to a sixth embodiment of the present invention;

FIG. 8 is a schematic diagram of an integrated circuit assembly structure according to a seventh embodiment of the present invention.

Detailed ways

first embodiment

Please refer to FIG. 2 below to illustrate the structure of the integrated circuit chip of the present invention with an embodiment.

As shown in FIG. 2 , the integrated circuit chip of this embodiment includes a chip body 20 , a plurality of metal bumps 210 and a plurality of metal particles 215 serving as a plurality of electrical conductor patterns. The chip body 20 has a first surface, namely the lower surface shown in FIG. 2 . The metal bumps 210 are disposed on the first surface of the chip body 20 , and each metal bump 210 has a patterned bonding surface. The metal particles 215 are used as electrical conductor patterns and are respectively disposed on the bonding surfaces. The shape of the metal particle 215 can be hemispherical, and its diameter is generally 3-15 microns, and it can also be set to an appropriate size according to the circuit requirements of the integrated circuit chip. In this way, the metal particles 215 can replace the conductive particles in the existing COG structure.

second embodiment

Please refer to FIG. 3 again, illustrating the structure of the integrated circuit chip of the second embodiment of the present invention when it is assembled. The integrated circuit assembly structure in FIG. 3 includes an integrated circuit chip 20 , an insulating substrate 10 and an adhesive film layer 40 . The structure of the integrated circuit chip 20 is similar to that shown in FIG. 2 . The first surface of the chip body is provided with a plurality of metal bumps 210, and each metal bump 210 has a patterned bonding surface, and each bonding surface is respectively Hemispherical metal particles 215 are provided as a plurality of electrical conductor patterns. The insulating substrate 10 includes a glass substrate or a plastic substrate, and has a plurality of electrode pads 110 respectively corresponding to the metal bumps 210 , and each electrode pad 110 has a second surface (upper surface). When the pressing surface of the metal bump 210 is respectively pressed on the second surface of the corresponding electrode pad 110, since the hemispherical metal particles 215 are arranged on the pressing surface, each corresponding metal bump 210 and each An electrode pad 110 can be electrically connected through the metal particles 215 as a plurality of electrical conductor patterns. In addition, since the metal particle 215 can produce electrical conduction between the metal bump 210 and the electrode pad 110, the adhesive film layer 40 provided between the integrated circuit chip 20 and the insulating substrate 10 does not need to contain conductive particles, and can The metal bump 210 and the electrode pad 110 are coated with an adhesive film generally, so that the integrated circuit chip 20 and the insulating substrate 10 are closely bonded without using an anisotropic conductive film with high cost.

third embodiment

Please refer to FIG. 4 again, illustrating the structure of the integrated circuit chip according to the third embodiment of the present invention when it is assembled. The integrated circuit assembly structure in FIG. 4 includes an integrated circuit chip 20 , an insulating substrate 10 and an adhesive film layer 40 . The structure of the integrated circuit chip 20 is similar to that shown in FIG. 2 . The first surface of the chip body is provided with a plurality of metal bumps 210, and each metal bump 210 has a patterned bonding surface, and each bonding surface is respectively Hemispherical metal particles 215 are provided as a plurality of first electric conductor patterns. The insulating substrate 10 includes a glass substrate or a plastic substrate, and has a plurality of electrode pads 110 corresponding to the metal bumps 210, each electrode pad 110 has a second surface (upper surface), and is also provided on the second surface as a plurality of electrode pads 110. A plurality of metal particles 115 of the second electrical conductor pattern, and the metal particles 215 disposed on the pressing surface of the metal bump 210 and the metal particles 115 disposed on the second surface of the electrode pad 110 are located at corresponding pressing positions. When the pressing surface of the metal bump 210 is respectively pressed on the second surface of the corresponding electrode pad 110, since the hemispherical metal particles 215 are arranged on the pressing surface of the metal bump 210, and the second surface of the electrode pad 110 The surface is also provided with metal particles 115 that are pressed against each other, so that each corresponding metal bump 210 and each electrode pad 110 can be electrically connected through the metal particles 115 and 215 . In addition, since the metal particles 115 and 215 can produce electrical conduction between the metal bump 210 and the electrode pad 110, the adhesive film layer 40 provided between the integrated circuit chip 20 and the insulating substrate 10 does not need to contain conductive particles. , a general adhesive film can be used to cover the metal bump 210 and the electrode pad 110, so that the integrated circuit chip 20 and the insulating substrate 10 are tightly bonded, without using an anisotropic conductive film with high cost.

Fourth embodiment

Please refer to FIG. 5 again, illustrating the structure of the integrated circuit chip of the fourth embodiment of the present invention when it is assembled. The integrated circuit assembly structure in FIG. 5 includes an integrated circuit chip 20 , an insulating substrate 10 and an adhesive film layer 40 . The structure of the integrated circuit chip 20 is similar to that shown in FIG. 2 . The first surface of the chip body is provided with a plurality of metal bumps 210, and each metal bump 210 has a patterned bonding surface, and each bonding surface is respectively Hemispherical metal particles 215 are provided as a plurality of first electric conductor patterns. The insulating substrate 10 includes a glass substrate or a plastic substrate, and has a plurality of electrode pads 110 corresponding to the metal bumps 210, each electrode pad 110 has a second surface (upper surface), and is also provided on the second surface as a plurality of electrode pads 110. A plurality of metal particles 115 of the second electrical conductor pattern, and the metal particles 215 disposed on the press-fitting surface of the metal bump 210 and the metal particles 115 disposed on the second surface of the electrode pad 110 are located at mutually dislocated engagement positions (relative to each other) wrong). When the pressing surface of the metal bump 210 is respectively pressed on the second surface of the corresponding electrode pad 110, since the hemispherical metal particles 215 are arranged on the pressing surface of the metal bump 210, and the second surface of the electrode pad 110 The metal particles 115 are also dislocated and engaged with each other on the surface. Therefore, each corresponding metal bump 210 and each electrode pad 110 can be electrically connected through the mutual dislocation and engagement of the metal particles 115 and 215 . In addition, since the metal bumps 210 and the electrode pads 110 can be electrically connected through the dislocation engagement of the metal particles 115 and 215, the adhesive film layer 40 provided between the integrated circuit chip 20 and the insulating substrate 10 does not It needs to contain conductive particles, so an adhesive film with general adhesiveness can be used to cover the metal bumps 210 and the electrode pads 110, so that the integrated circuit chip 20 and the insulating substrate 10 are tightly bonded, without using an anisotropic conductive film with high cost. membrane.

fifth embodiment

Please refer to FIG. 6 again, illustrating the structure of the integrated circuit chip according to the fifth embodiment of the present invention when it is assembled. The integrated circuit assembly structure in FIG. 6 includes an integrated circuit chip 20 , an insulating substrate 10 and an adhesive film layer 40 . The integrated circuit chip 20 in FIG. 6 does not adopt the structure of the integrated circuit chip shown in FIG. 2 , but uses a general existing integrated circuit chip. Each metal bump 210 of the integrated circuit chip 20 has a patterned bonding surface, but metal particles are not disposed on each bonding surface, but are only disposed on the second surface of the plurality of electrode pads 110 of the insulating substrate 10 A plurality of metal particles 115 as a plurality of electrical conductor patterns. When the pressing surfaces of the metal bumps 210 are respectively pressed on the second surface of the corresponding electrode pad 110, since the second surface of the electrode pad 110 is provided with metal particles 115 as a plurality of electrical conductor patterns, each corresponding A metal bump 210 and each electrode pad 110 can be electrically connected through the metal particles 115 . In addition, since the metal particle 115 can produce electrical conduction between the metal bump 210 and the electrode pad 110, the adhesive film layer 40 provided between the integrated circuit chip 20 and the insulating substrate 10 does not need to contain conductive particles, so A general adhesive film can be used to cover the metal bump 210 and the electrode pad 110, so that the integrated circuit chip 20 and the insulating substrate 10 are closely bonded, without using an anisotropic conductive film with high cost.

Sixth embodiment

Please refer to FIG. 7 again, illustrating the structure of the integrated circuit chip of the sixth embodiment of the present invention when it is assembled. The integrated circuit assembly structure in FIG. 7 includes an integrated circuit chip 20 , an insulating substrate 10 and an adhesive film layer 40 . The structure of the integrated circuit chip 20 is similar to that shown in FIG. 2 . The first surface of the chip body is provided with a plurality of metal bumps 210, and each metal bump 210 has a patterned bonding surface, and each bonding surface is respectively Hemispherical metal particles 215 are provided as a plurality of first electric conductor patterns. The insulating substrate 10 includes a glass substrate or a plastic substrate, and has a plurality of electrode pads 110 corresponding to the metal bumps 210, each electrode pad 110 has a second surface (upper surface), and a corresponding inlay is provided on the second surface. The plurality of grooves 125 are adapted to the metal particles 215 as the plurality of second electrical conductor patterns. When the pressing surface of the metal bump 210 is respectively pressed on the second surface of the corresponding electrode pad 110, since the hemispherical metal particles 215 are arranged on the pressing surface of the metal bump 210, and the second surface of the electrode pad 110 Corresponding grooves 125 are provided on the surface, therefore, each corresponding metal bump 210 and each electrode pad 110 can be electrically connected through the fitting of metal particles 215 into the grooves 125 . In addition, because electrical conduction can be generated between the metal bump 210 and the electrode pad 110 through the fitting of the metal particle 215 and the groove 125, the adhesive film layer 40 disposed between the integrated circuit chip 20 and the insulating substrate 10 It does not need to contain conductive particles, so an adhesive film with general adhesiveness can be used to cover the metal bumps 210 and the electrode pads 110, so that the integrated circuit chip 20 and the insulating substrate 10 are tightly bonded, without using an anisotropic film with high cost. conductive film.

Seventh embodiment

Please refer to FIG. 8 again, illustrating the structure of the integrated circuit chip of the seventh embodiment of the present invention when it is assembled. The integrated circuit assembly structure in FIG. 8 includes an integrated circuit chip 20 , an insulating substrate 10 and an adhesive film layer 40 . The integrated circuit chip 20 in FIG. 8 does not use the integrated circuit chip shown in FIG. 2 , but uses a general existing integrated circuit chip 20 . Each metal bump 210 of the integrated circuit chip 20 has a patterned bonding surface, but each bonding surface is not provided with metal particles, but only on the second surface of the plurality of electrode pads 110 of the insulating substrate 10 A plurality of metal particles 115 are provided as a plurality of second electrical conductor patterns, and a plurality of grooves 225 as a plurality of first electrical conductor patterns corresponding to the metal particles 115 are provided on the pressing surface of the metal bump 210 . When the pressing surface of the metal bump 210 is respectively pressed on the second surface of the corresponding electrode pad 110, since the second surface of the electrode pad 110 is provided with metal particles 115, the pressing surface of the metal bump 210 is provided with Corresponding to the groove 225 , therefore, each corresponding metal bump 210 and each electrode pad 110 can be electrically connected through the fitting of the metal particle 115 and the groove 225 . In addition, because electrical conduction can be generated between the metal bump 210 and the electrode pad 110 through the fitting of the metal particle 115 and the groove 225, the adhesive film layer 40 disposed between the integrated circuit chip 20 and the insulating substrate 10 It does not need to contain conductive particles, so an adhesive film with general adhesiveness can be used to cover the metal bump 210 and the electrode pad 110, so that the integrated circuit chip 20 and the insulating substrate 10 are tightly bonded, and there is no need to use an anisotropic film with high cost. conductive film.

As mentioned above, in the integrated circuit structure of each embodiment of the present invention, since at least one of the metal bumps 210 and the electrode pads 110 is provided with metal particles 115 and/or 215 as a plurality of electrical conductor patterns, through The metal particles 115 and/or 215 can produce electrical conduction, so there is no need to use an anisotropic conductive film with high cost as the adhesive film for bonding the integrated circuit chip 20 and the insulating substrate 10, and only need to use a general adhesive Membranes save costs. However, the above embodiments do not limit the material of the adhesive film layer, and the anisotropic conductive film or other adhesive films can still be used as the adhesive film layer as required.

In addition, in the integrated circuit structure of the above-mentioned embodiments, since the adhesive film layer 40 does not contain conductive particles, it will not cause poor electrical conduction or short circuit due to uneven distribution of conductive particles as in the existing COG structure. and other phenomena, and the gaps between metal bumps 210 and electrode pads 110 are not limited by size, and can be arranged as denser circuits according to requirements.

In addition, the metal particles 215 as a plurality of electrical conductor patterns are directly formed on the bonding surface of the metal bump 210, which can be manufactured by a semiconductor process or other appropriate processes, and the shape is not limited to hemispherical or granular, and can be made according to the process. The shape allowed to be manufactured can be manufactured, and the electric conductor pattern can be evenly distributed through the control of the process, so that the current stability of the structure can be easily controlled.

In each form of the present invention above, the first electrical conductor pattern and the second electrical conductor pattern can be metal particles or a plurality of grooves correspondingly embedded in the metal particles, and their shapes can be hemispherical or other shapes suitable for manufacturing, And its diameter is generally 3-15 microns is preferred.

The techniques of the various embodiments of the present invention can be suitably applied to any occasions with integrated circuit structures. For example, common flat display devices such as liquid crystal displays or plasma displays can be applied to the integrated circuits described in the above-mentioned embodiments. The assembly structure carries out the driving IC chip packaging, the insulating substrate 10 is used as the display panel of the flat display device, and the integrated circuit chip 20 is used as the driving IC chip of the flat display device.

Although the present invention has been disclosed above with specific preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art can still make various modifications and changes without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention should be defined by the appended claims.

Claims (16)

1. integrated circuit comprises:

One chip body has a lower surface;

A plurality of metal couplings are arranged at this lower surface, and those metal couplings have the stitching surface of a patterning;

One insulated substrate;

A plurality of electronic padses are formed on this insulated substrate the position corresponding to those metal couplings, and the upper surface of those electronic padses have corresponding to or interlace in the pattern of the stitching surface of this patterning; And

One adhesive film is arranged between the lower surface and this insulated substrate of this chip body, and coats those metal couplings and those electronic padses.

2. integrated circuit as claimed in claim 1, wherein the stitching surface of this patterning is shaped as hemisphere.

3. integrated circuit as claimed in claim 2, wherein this hemispheric diameter range is approximately 3 to 15 microns.

4. integrated circuit as claimed in claim 1, wherein this insulated substrate comprises glass substrate or plastic base.

5. integrated circuit as claimed in claim 1, wherein when the upper surface of those electronic padses had pattern corresponding to the stitching surface of this patterning, the pattern of the upper surface of those electronic padses was a plurality of grooves or a plurality of metallic particles.

6. integrated circuit as claimed in claim 1, when wherein the upper surface of those electronic padses had the pattern that interlaces in the stitching surface of this patterning, the pattern of the upper surface of those electronic padses was a plurality of metallic particles.

7. substrate that comprises integrated circuit (IC) chip comprises:

One chip body has a lower surface;

A plurality of metal couplings are arranged at this lower surface, and those metal couplings have the stitching surface of a patterning;

One insulated substrate;

A plurality of electronic padses be formed on this insulated substrate the position corresponding to those metal couplings, and the upper surface of those electronic padses have the pattern corresponding to the stitching surface of this patterning; And

One adhesive film is arranged between the lower surface and this insulated substrate of this chip body, and coats those metal couplings and those electronic padses.

8. the substrate that comprises integrated circuit (IC) chip as claimed in claim 7, wherein the stitching surface of this patterning is shaped as hemisphere.

9. the substrate that comprises integrated circuit (IC) chip as claimed in claim 8, wherein this hemispheric diameter range is approximately 3 to 15 microns.

10. the substrate that comprises integrated circuit (IC) chip as claimed in claim 7, wherein the pattern of the upper surface of those electronic padses is a plurality of grooves or a plurality of metallic particles.

11. the substrate that comprises integrated circuit (IC) chip as claimed in claim 7, wherein this insulated substrate comprises glass substrate or plastic base.

12. a substrate that comprises integrated circuit (IC) chip comprises:

One chip body has a lower surface;

A plurality of metal couplings are arranged at this lower surface, and those metal couplings have the stitching surface of a patterning;

One insulated substrate;

A plurality of electronic padses are formed on this insulated substrate the position corresponding to those metal couplings, and the upper surface of those electronic padses has the pattern that interlaces in the stitching surface of this patterning; And

One adhesive film is arranged between the lower surface and this insulated substrate of this chip body, and coats those metal couplings and those electronic padses.

13. the substrate that comprises integrated circuit (IC) chip as claimed in claim 12, wherein the stitching surface of this patterning is shaped as hemisphere.

14. the substrate that comprises integrated circuit (IC) chip as claimed in claim 13, wherein this hemispheric diameter range is approximately 3 to 15 microns.

15. the substrate that comprises integrated circuit (IC) chip as claimed in claim 12, wherein this insulated substrate comprises glass substrate or plastic base.

16. the substrate that comprises integrated circuit (IC) chip as claimed in claim 12, wherein the pattern of the upper surface of those electronic padses is a plurality of grooves or a plurality of metallic particles.

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