CN1612335A - Improved semiconductor lead carriage - Google Patents

Abstract

A lead frame (100) for integrate circuit chip (301) includes an ultrathin tin layer (104) on copper (103). The copper (103) includes a base metal, or a coating layer on another base metal. A point or annular shape silver joint liner (105A, B) can be selectively provided for supporting the lead joint electric connection (302A, B). The completed integrate circuit component assembled on the lead frame can be selectively encapsulated in an anti-corrosion environment to prolong the weldability storage life.

Description

Improved Semiconductor Lead Frame

technical field

The present invention relates generally to semiconductor devices and manufacturing processes, and more particularly to the materials and fabrication of lead frames for integrated circuit devices.

Background technique

Lead frames for semiconductor devices were invented (US Patent Nos. 3,716,764 and 4,034,027) to simultaneously meet several needs for semiconductor devices and their operation: First, lead frames provide a stable support pad for firmly placing semiconductor chips , usually an integrated circuit (IC) chip. Since the leadframe including the pads is made of an electrically conductive material, the pads can be biased, if desired, to any potential required by the networks involved in the semiconductor device, especially ground potential.

Second, the lead frame provides multiple conductive segments to place multiple electrical conductors near the chip. The remaining gaps between the ("inner") tips of the segments and the conductor pads on the surface of the IC are connected by thin metal wires bonded to the IC contact pads and the leadframe segment, respectively. Clearly, wire bonding means that a reliable bond can be formed at the (inner) segment tip.

Third, the ends of the wire segments remote from the IC chip ("external" tips) need to be electrically and mechanically connected to "other components" or the "outside world", for example to a printed circuit board. In the vast majority of electronic applications, this connection is performed by soldering. Clearly, the soldering technique implies a reliable wetting and soldering contact at the (external) segment tip.

It has become common practice to fabricate monolithic leadframes from thin (approximately 100 to 300 μm) sheet metal. For ease of manufacture, the starting metals generally chosen are copper, copper alloys, iron-nickel alloys (such as the so-called "alloy 42") and Kovar. Etch or stamp the desired leadframe shape from raw sheet metal. With this approach, an individual lead frame segment takes the form of a thin metal strip whose specific geometry is dictated by the design. For most purposes, the length of a typical segment is much longer than its width.

In U.S. Patent 6,245,448 (Abbott, "Leadframe with Reduced Corrosion"), issued June 12, 2001, a palladium-coated leadframe is described that is impervious to corrosion because the electrical forces of the current flow assist the movement of base metal ions to the top surface, where they form corrosion products. This patent describes a sequence of layers consisting of nickel (on top of the base metal), palladium/nickel alloy, nickel and palladium (outermost layer). This technology has been widely accepted by the semiconductor industry on copper-based leadframes.

After assembly on a leadframe, most ICs are typically encapsulated by plastic material in a molding process. Basically, the molding compound (usually an epoxy-based thermosetting compound) bonds well to the leadframe and the device components it encapsulates. The palladium described above as the outermost layer of the leadframe provides excellent adhesion to the molding compound.

Unfortunately, palladium is expensive. Cost pressures in semiconductor manufacturing have led to efforts to reduce the thickness of the palladium layer employed to approximately one third of the previous thickness. At this thinness, palladium does not prevent oxidation of the underlying nickel, which limits its solderability. A method introduced in semiconductor manufacturing uses a thin layer of gold on top of palladium to prevent oxidation. A related example is described in US Patent No. 5,859,471 (Kuraishi et al., "TAB Leadframed Semiconductor Device With Reinforced Outer Leads"), issued January 12, 1999.

However, in these methods, the entire surface of the lead frame is plated with gold. This practice severely limits the adhesion of the lead frame segments to the molding compound and creates a risk of delamination during thermomechanical stress testing. Furthermore, plating the entire leadframe with a thin layer of gold makes it impossible to determine by visual inspection whether a leadframe has a gold surface. But simple checks of this standard are highly desirable as a manufacturing practice. Finally, depositing gold in unnecessary areas is counterproductive to cost-saving efforts.

There thus arises a need for a new low-cost reliable mass-production method for semiconductor leadframes—particularly the widely accepted copper leadframes—that provides all the assembly features expected from leadframes: gold Wire bondability, solderability and adhesion to polymeric compounds. What is further needed is the use of low cost non-hazardous materials. The new lead frame and its manufacturing method should be flexible enough to be used in different semiconductor product families and a wide range of design and assembly variants. Preferably these new inventions can be implemented with an installed base of equipment so that no investment in new manufacturing machinery is required.

Contents of the invention

According to the present invention, there are provided in various forms a lead frame, a semiconductor device and a method of manufacturing a lead frame, including new and improved lead frames.

According to one embodiment of the present invention, there is provided a lead frame for packaging a semiconductor device, which includes: a chip mounting pad for supporting an integrated circuit chip; a plurality of wire segments, the first ends of which are adjacent to the the mounting pad with its second end away from the mounting pad; and each of the chip mounting pad and the plurality of leadframe segments includes a first copper layer and a second tin layer, the first tin layer A second tin layer is formed directly on the copper.

According to another embodiment of the present invention, there is provided a semiconductor device comprising: a lead frame including a chip mounting pad for an integrated circuit chip, and a plurality of lead segments, the plurality of lead the first end of the segment is close to the mounting pad and the second end is away from the mounting pad; the lead frame includes a first copper layer, and a second tin layer formed directly on the on said copper; an integrated circuit chip bonded to said chip mounting pad by a chip attach material; bonding wires connecting said chip to said first ends of said wire segments; an encapsulating material surrounding the chip, the bonding wire, and the first end of the wire segment; and the encapsulating material exposes the second end of the wire segment so that the second end is adapted to be bent for welding to other components.

According to yet another aspect of the present invention, there is provided a method of manufacturing a lead frame for packaging a semiconductor device, comprising the steps of: providing said lead frame, which includes a lead frame for supporting an integrated circuit chip chip mounting pad, and a plurality of wire segments having first ends adjacent to the mounting pad and second ends remote from the mounting pad; covering the lead frame with a first copper layer and covering said copper layer with a second tin layer formed directly on said copper.

The technical advancement represented by this invention, and its aspects, will become apparent from the following description of preferred embodiments of the invention when considered in conjunction with the accompanying drawings and the novel features set forth in the appended claims.

Description of drawings

Fig. 1 is a schematic cross-sectional view of a portion of a lead frame manufactured according to a first embodiment of the present invention.

Fig. 2 is a schematic cross-sectional view of a portion of a lead frame manufactured according to a second embodiment of the present invention.

Fig. 3 is a schematic cross-sectional view of a plastic packaged semiconductor device having a lead frame according to the present invention, soldered to a substrate.

Detailed ways

The present invention provides a pre-plated leadframe with a lower total cost of ownership for use in IC assembly/test houses and semiconductor manufacturers. The present invention provides for the manufacture of a leadframe that has the attributes and functions of a pre-plated leadframe without the use of hazardous or expensive materials. Using copper as the starting material, the present invention eliminates the need for a nickel layer (nickel is on the EPA list of toxic chemicals and is subject to reduction/elimination from future industrial processes) and palladium and/or gold layers (as precious metals). , palladium and gold are expensive and subject to market price movements and supply uncertainty) regular demand. Alternatively, the present invention provides an ultra-thin layer of tin (Sn) on top of copper (Cu), as described below.

As defined herein, the starting material of the leadframe is referred to as the "base metal", denoting the type of metal used to form the basic leadframe structure. Therefore, the term "base metal" is not used in the electrochemical sense (as opposed to "noble metal") or in the structural sense. Base metals include, but are not limited to, alloys such as brass, aluminum, iron-nickel alloys ("Alloy 42"), and Kovar.

Leadframe surfaces must generally meet five requirements in semiconductor assembly:

1) The lead frame must include the outer segment tip with a surface suitable for soldering to other components;

2) The leadframe must include an inner segment tip with a surface suitable for metallurgical bonding to the lead;

3) The leadframe must include outer segment ductility for forming and bending segments;

4) leadframe surfaces must include surfaces suitable for adhesion to polymeric die attach materials and molding compounds; and

5) Lead frame surfaces must include surfaces that are not sensitive to corrosion.

According to the teachings of the present invention, all these needs are met by an ultra-thin layer of tin on copper, with silver dots or rings optionally plated on the tips of the inner segments for wire bonding.

In the embodiment of the invention shown in FIG. 1 , a schematic cross-section of a leadframe portion 100 includes a chip mount pad 101 , and a pair of wire segments, as shown at 102A and 102B. According to this embodiment of the invention, the starting or base metal 103 is copper. The base metal has a sheet-like shape and its thickness is preferably in the range of about 100 to 300 [mu]m; thinner sheets are also possible. Stretching in this thickness range provides the 5 to 15% elongation required in subsequent segment bending and forming operations. Leadframes are stamped or etched from a starting metal sheet.

Continuing with FIG. 1, an ultra-thin layer of tin 104 is attached to the copper base metal 103 by a conventional electroplating process with a thickness in the range of less than about 100 Angstroms. An example of a conventional electroplating process includes the steps of i) soaking with alkali and electrically cleaning the imprinted or etched base metal, ii) activating the base metal with acid and iii) electroplating the ultra-thin tin layer 104 . Proper rinsing is performed between said operations, and proper drying is performed after tinning.

Bond pads in the form of silver (Ag) dots or rings as shown at 105A and 105B are optionally provided at the inner tip of each wire segment to facilitate subsequent wire bond formation to a pad 101 mounted Electrical connections of semiconductor chips. The silver bonding pads 105A, B may be formed by a process of electroplating Ag before the above tin plating and after the activation step. Silver-plating selectivity is achieved by using a reusable rubber mask with a thickness ranging from 1.25 to 2 μm.

Referring to FIG. 2 , an alternative embodiment of the present invention is shown, which includes a portion of a lead frame 200 including lead segments 202A, 202B and chip mounting pad 201 . In this embodiment of the invention, the base metal 203 is not copper but is selected from another lead frame base material such as brass, aluminum, an iron-nickel alloy such as "Alloy 42" or Kovar . As with the copper lead frame described above, the base metal has a sheet-like configuration with a thickness preferably in the range of about 100 to 300 µm; thinner sheets are also possible.

With continued reference to FIG. 2, a thin copper layer 204 is plated on the non-copper base metal 203 by a conventional electroplating process, such as adding copper plating before the selective Ag plating and tin plating steps and after the activation step in the electroplating process described above. , with a thickness in the range of about 50 microns. A tin layer 205 is then electroplated on the copper layer 204 as described above to a thickness in the range of less than about 100 angstroms. Silver bonding (not shown), still preferably in the form of points or rings, may also optionally be located on the inner tip of each wire segment to support a wire bond connection.

Referring now to FIG. 3 , the lead frame portion 100 of FIG. 1 is shown incorporated into a more complete semiconductor chip package 300 . The same elements as in FIG. 1 are denoted by the same reference numerals. Referring to FIG. 3 , a semiconductor chip 301 is shown bonded to the upper surface of the chip pad 103 , for example by a conventional epoxy or polyimide. Lead wires 302A, 302B constitute conventional wire bond connections between electrical contacts on the upper surface of chip 301 and silver bond pads 105A, 105B on wires 102A, 102B, respectively. Chip 301, wire bond wires 302A, 302B and the tips of wires 102A, 102B with silver bonding pads 105A, 105B are all encapsulated in a layer 104 of epoxy, shown at 303, which is suitable for bonding to a leadframe. In a conventional package selected from the group consisting of thermoset-based molding compounds.

With continued reference to FIG. 3 , lead portions 102A and 102B are shown bent into a "gull's wing" shape for electrical connection to the surface of a printed circuit board 306 via solder connections 304A and 304B, respectively. The solder connections 304A, 304B comprise solders such as eutectic tin/lead or various lead-free solders according to so-called tin-silver-copper (SAC) applied by a conventional soldering process (eg convection or infrared reflow).

It is to be understood that lead frame portion 200 may also be incorporated into a larger semiconductor chip package similar to that shown in FIG. Structure.

In yet another embodiment of the present invention, the lead frame embodiments described above with reference to FIGS. 1 and 2 may be encapsulated in an encapsulating material for extended shelf life, the encapsulating material comprising a corrosion inhibitor, wherein Includes antioxidants, which are deposited by evaporation to coat copper active areas. Examples of such packaging materials include tubes, trays and tapes, and reels for assembled semiconductor devices, while examples of such corrosion inhibitors include: benzotriazole (BTA) and tolyltriazole. The advantage of this package is to extend the solderability shelf life of the lead frame.

Thereby a lead frame is provided which does not contain precious metals, such as palladium or gold, nor potentially harmful materials, such as nickel. The lead frame has excellent molding compound adhesion. The ultra-thin nature of the tin layer minimizes or eliminates the common danger of tin "whiskers". When a wire bond connection is made to the lead frame, the tin plating on the lead frame forms a small intersecting metal in the gold wire. Alternatively, as noted above, silver bond pads such as dots or rings can be added to the tin for supporting the wire bonds. Tin remains solderable to copper when the lead frame is soldered to a printed circuit board. In an alternate embodiment, a non-copper base metal is used and a thin layer of copper is electroplated onto the base metal to provide the structure and advantages of the present invention. Complete integrated circuit packages can optionally be packaged in a corrosion-resistant environment to extend the solderability shelf life of the finished device.

Advantages provided by the present invention include but are not limited to: cost savings achieved by avoiding precious metals; avoiding potentially harmful materials such as nickel and lead; a pre-plated low cost finish which exhibits better mold compound adhesion simple lead frame handling; avoidance of tin whiskers; finished product meeting Class 1 moisture sensitivity requirements; and an easily controlled process of fabrication to the desired thickness.

The invention finds application in IC fabrication, especially in high density IC fabrication with higher input/output numbers, and also in the fabrication of low-end, low-cost devices. These ICs can be found in many semiconductor device families including standard linear and logic products, digital signal processors, microprocessors, digital and analog devices, high frequency and high energy devices, and large and small area chip categories. Package types are available in Plastic Dual Inline Package (PDIP), Small Outline Integrated Circuit (SOIC), Square Planar Package (QFP), Thin QFP (TQFP), SSOP, TSSOP, TVSOP and other lead frame based packages.

While this invention has been described with reference to illustrative embodiments, this description is not intended to be construed in a limiting sense. Various modifications and combinations of the described embodiments, as well as other embodiments of the invention, will be readily apparent to those skilled in the art upon reference to the description. As an example, the material of the semiconductor chip may include silicon, silicon germanium, germanium arsenide, or any other semiconductor material used in fabrication.

Claims (22)

1. lead frame that is used to encapsulate a semiconductor device comprises:

A chip is installed liner, is used to support an integrated circuit (IC) chip;

A plurality of lead fragments, its first end near described installation liner and its second end away from described installation liner; And

In described chip installation liner and the described a plurality of lead frame fragment each comprises:

One first bronze medal layer, and

One second tin layer, it is formed directly on the described copper.

2. the lead frame of claim 1, the thickness of the wherein said second tin layer is in the scope less than about 100 dusts.

3. the lead frame of claim 2, the wherein said second tin layer is plated on the described first bronze medal layer.

4. the lead frame of claim 3, the wherein said first bronze medal layer comprises the base metal of described lead frame.

5. the lead frame of claim 3, the wherein said first bronze medal layer covers a kind of base metal of non-copper.

6. the lead frame of claim 3 further comprises a silver-colored joint liner on each of described a plurality of lead frame fragments, be used to support that wire-bonded is bonding.

7. the lead frame of claim 3 is included in the encapsulation, and described encapsulation comprises a kind of corrosion inhibitor that is used for copper.

8. a semiconductor device comprises:

A lead frame, this lead frame comprise that a chip that is used for an integrated circuit (IC) chip installs liner, and a plurality of lead fragment, first end of described a plurality of lead fragments near described installation liner and its second end away from described installation liner;

Described lead frame comprises

One first bronze medal layer, and

One second tin layer, it is formed directly on the described copper;

An integrated circuit (IC) chip, it is adhered to described chip by a kind of chip adhesive material and installs on the liner;

Interconnect a plurality of closing lines of described first end of described chip and described a plurality of lead fragments;

Surround the encapsulating material of described first end of chip, described a plurality of closing lines and described a plurality of lead fragments; And

Described encapsulating material makes outside described second end of described a plurality of lead fragments is exposed to, thereby described second end is suitable for bending, so that be welded on the miscellaneous part.

9. the lead frame of claim 8, the thickness of the wherein said second tin layer is in the scope less than about 100 dusts.

10. the lead frame of claim 9, the wherein said second tin layer is plated on the described first bronze medal layer.

11. the lead frame of claim 10, the wherein said first bronze medal layer comprises the base metal of described lead frame.

12. the lead frame of claim 10, the wherein said first bronze medal layer covers a kind of base metal of non-copper.

13. the lead frame of claim 10 further comprises a silver-colored joint liner on each of described a plurality of lead frame fragments, be used to support that wire-bonded is bonding.

14. make a method that is used for the lead frame of encapsulated semiconductor device for one kind, this method may further comprise the steps:

A lead frame is provided, and this lead frame comprises

A chip installation liner that is used to support an integrated circuit (IC) chip, and

A plurality of lead fragments, its first end near described installation liner and its second end away from described installation liner;

Cover described lead frame with one first bronze medal layer; And

Cover described copper layer with one second tin layer, this second tin layer is formed directly on the described copper.

15. the method for a lead frame of manufacturing of claim 14, the thickness of the wherein said second tin layer is in the scope less than about 100 dusts.

16. the method for a lead frame of manufacturing of claim 15, the step that one second tin layer of wherein said usefulness covers the described first bronze medal layer comprise the described second tin layer is plated on the described first bronze medal layer.

17. the method for a lead frame of manufacturing of claim 15, the wherein said first bronze medal layer comprises the base metal of described lead frame.

18. the method for a lead frame of manufacturing of claim 15, the wherein said first bronze medal layer covers a kind of base metal of non-copper.

19. the method for a lead frame of manufacturing of claim 15 further is included in and forms a silver-colored joint liner on each of described a plurality of lead frame fragments, is used to support that wire-bonded is bonding.

20. the method for a lead frame of manufacturing of claim 15 comprises further with described lead frame the described integrated circuit (IC)-components of finishing is encapsulated in the encapsulation that this encapsulation comprises a kind of corrosion inhibitor to copper.

21. the method for a lead frame of manufacturing of claim 15 further may further comprise the steps:

A semiconductor chip is adhered to described chip to be installed on the liner;

With the electrical pickoff wire-bonded on the described semiconductor chip on described a plurality of lead fragments; And

The described semiconductor chip of encapsulation, described chip are installed liner and described a plurality of wire-bonded in the encapsulation of a protectiveness.

22. the method for a lead frame of manufacturing of claim 21 further comprises each of described a plurality of lead fragments is welded to step on the respective electrical connector of electronic device.

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