CN1612119A - Solid state storage unit safety storage system and method - Google Patents

Abstract

A safe storage system and method of a solid-state memory, the system includes a solid-state memory, a central processing unit and a bus. The solid-state memory includes multiple data blocks, and each data block includes multiple data pages and an error checking page. The data page includes a plurality of data bytes, a redundancy check byte and a redundancy check complement byte. The method can generate a redundancy check code and a redundancy check complementary code for the data of a data page, which are used to perform redundancy check on the data of the data page; and perform parity check on the data of a data block at the same time ; and correct the wrong data bit; and then recover and store the overwritten correct data. The above-mentioned system and method can avoid the irreparable situation caused by overwriting the original correct data when the file data is incorrectly written into the solid-state memory, and restore the overwritten correct data to ensure the correct integrity of the data.

Description

Safe storage system and method for solid-state memory

【Technical field】

The invention relates to a safe storage system and method of a solid-state memory, in particular to a safe storage method capable of recovering overwritten correct data.

【Background technique】

For a storage system, there are two important factors: the ability to read and write data quickly and the ability to access data reliably. At present, a method that is widely used to ensure the reliability of data access is to perform a redundancy check code (CRC) check on the stored data, and generate relevant data by a specific method each time data is written to the storage system. Redundancy check code. The above-mentioned storage system can be a memory product using semiconductor, magnetism, and light as a storage medium, such as an erasable semiconductor read-only memory, including flash memory (Flash Read Only Memory), EEPROM (Electrically Erasable Programmable Read Only Memory) and the like. Flash memory is a solid-state rewritable memory that operates like a hybrid of random access memory and hard disk, suitable for storing data in various devices. Although these memories can save data in the event of a power failure or improper operation, the data stored in the memory may be incomplete, causing the correct data to be overwritten, and the correct integrity of the stored data cannot be guaranteed.

At present, there are many technologies for storing data, such as the No. 5,754,566 patent announced by the United States Patent and Trademark Office on March 19, 1998, named "Method And Apparatus ForCorrecting A Multilevel Cell Memory By Using Interleaving", which provides a method that can be used in A device and method for generating an error correction code (ECC) in a multi-level memory unit, the error correction code is respectively stored in a plurality of data bytes, an error correction code will be generated for each data byte and stored in a in memory cells of N bytes. This method has a high storage cost for some memory with higher storage cost such as flash memory (FLASH ROM), and the ability to check and correct data errors is not strong. Therefore, it is really necessary to propose a new solution that can correctly recover stored data. The present invention provides a set of new solutions to meet the above-mentioned deficiencies in the storage system. This method provides a safe and Reliable storage for overwritten correct data recovery.

【Content of invention】

Aiming at the shortcomings of the prior art, the main purpose of the present invention is to provide a secure storage system and method for solid-state memory. Storage systems generally have some settings or recorded data, even system software, stored in the memory, but in the event of a power outage or improper operation, the data may be incompletely stored in the memory, making the correct data was erased. The present invention is used to avoid the above-mentioned situation, and provides a reliable storage method for recovering overwritten correct data, so as to ensure the correct integrity of the data.

In order to achieve the purpose of the above invention, the present invention provides a safe storage system for solid-state memory, the system includes: a solid-state memory (MEMORY), a central processing unit (CPU) and a bus (BUS), wherein the solid-state memory includes multiple Each memory block has a storage space of 1MByte capacity for storing corresponding data. The data block includes multiple data pages (DATA PAGE) and an error checking page (PARITY CHECK PAGE). Each data page has a storage space of 4KByte capacity, and the data page includes a plurality of data bytes, a redundancy check byte and a redundancy check complementary byte. The redundancy check byte stores a redundancy check code (CRC). The redundancy check complement byte stores a redundancy check complement code (CRC'). The error check page includes a parity byte to store a parity code (PARITY CODE); the central processor can read, write and control the solid-state memory through the bus to generate a redundancy check code for the stored data And store it in the corresponding check code area, and can perform error checking and correction on the corresponding data. Among them, the central processing unit uses the error check page to perform parity check on the data of the memory block, uses the redundancy check to perform error check and correction on the data of each data page, and restores the correct data to ensure the correctness of the data. Integrity: This bus is used to cooperate with the central processing unit to perform corresponding read, write and control operations on the data of the solid-state memory.

The invention also provides a safe storage method of the solid-state memory. It uses a central processing unit to generate redundant check codes, redundant check complementary codes and parity check codes, performs error checks and corrections on the corresponding data, and then performs storage operations to ensure the correct integrity of the data. Comprise the following steps: (a) the central processing unit sums up the data values of each data byte of a data page, and then sums with a redundant additional number to obtain the value of a redundancy check code CRC, and can use the corresponding Algorithm: CRC=(D[001]+D[002]+D[003]+...+D[FFE])+0X94, so that the value of CRC is always equal to "0XFF"; (b) central processing unit computing institute The value of the hexadecimal complement number CRC' of the redundant check code CRC'; (c) the central processing unit reads the data of the data byte of a memory block, generates a parity check code and stores it in an error check In the corresponding parity check byte of the check page, and set the parity check mode; (d) the central processing unit utilizes the redundancy check mode and the parity check mode to simultaneously perform error checking on a horizontal data and a vertical data interleaving ; (e) When the central processing unit detects a data error, it can correct the corresponding erroneous data bit, and use the error checking page to restore the correct data.

Through the above-mentioned system and method, it is possible to perform horizontal and vertical interleaved error checking on the data in the solid-state memory at the same time by using the check methods of parity check and redundancy check, and correct erroneous data bits. Therefore, when the file data is incorrectly written into the solid-state memory (such as power failure or improper operation during writing), the irreparable situation caused by overwriting the original correct data can be avoided, and the overwritten correct data can be restored and stored. , ensuring the correct integrity of the data.

【Description of drawings】

FIG. 1 is a hardware architecture diagram of a secure storage system of a solid-state memory according to the present invention.

Fig. 2 is a schematic diagram of the storage space of the solid-state memory of the secure storage system of the solid-state memory of the present invention.

FIG. 3 is a schematic diagram of the memory block storage space of the solid-state memory in the secure storage system of the solid-state memory of the present invention.

4 is a schematic diagram of the data page storage space of the memory block of the secure storage system of the solid state memory of the present invention.

FIG. 5 is a schematic diagram of data error checking and correction of the secure storage system of the solid-state memory of the present invention.

Fig. 6 is a flow chart of the safe storage method of the solid-state memory according to the present invention.

【Detailed ways】

As shown in FIG. 1 , it is a hardware architecture diagram of the secure storage system of the solid-state memory of the present invention. The secure solid-state memory storage system includes a solid-state memory (MEMORY) 1 , a central processing unit (CPU) 2 and a bus (BUS) 3 . Wherein, solid-state memory 1 can be a flash memory (FLASH ROM), is used for storing data. The central processing unit 2 can read, write and control the data in the solid-state memory 1 through the bus 3, or receive data from an external data source (not shown in the figure) through the bus 3 and store it in the solid-state memory 1 to generate The redundant check code of the stored data is stored in the corresponding check code area, and the corresponding data can be checked and corrected for errors, and the data can be added, complemented, and bit by bit comparison operation. The bus 3 is used to cooperate with the central processing unit 2 to perform corresponding read, write and control operations on the data in the solid-state memory 1 .

As shown in FIG. 2 , it is a schematic diagram of the storage space of the solid-state memory of the secure storage system of the solid-state memory of the present invention. A solid-state memory 1 is logically divided into a plurality of memory blocks (MEMORY BLOCK) 10, and each memory block 10 has a storage space with a capacity of 1MByte for storing corresponding data.

As shown in FIG. 3 , it is a schematic diagram of the memory block storage space of the solid-state memory of the secure storage system of the solid-state memory of the present invention. A memory block 10 of a solid-state memory 1, the memory block 10 has a storage space of 1MByte capacity, which is logically divided into a plurality of data pages (DATA PAGE) 101 and an error checking page (PARITY CHECK PAGE) 102 . Each data page 101 and error check page 102 has a storage space of 4KByte capacity, the data page 101 is used to store multiple data, redundancy check code and redundancy check complementary code; the error check page 102 is used to store Parity check code, which is used to complete the parity check of 1Mbyte data, the parity check can be selected odd (ODD PARITY) check or even (EVENPARITY) check, the error check page 102 can also be used for the recovery of correct data .

As shown in FIG. 4 , it is a schematic diagram of the data page storage space of the memory block of the secure storage system of the solid state memory of the present invention. A data page 101 with a 4KByte storage capacity of a memory block 10 is logically divided into byte addresses 001, 002, 003...FFE, FFF, and the data stored in the addresses are respectively: D[001] , D[002], D[003]... redundancy check complementary byte 1012, redundancy check byte 1011. The redundancy check byte 1011 is used to store a redundancy check code (CRC); the redundancy check complement byte 1012 is used to store a redundancy check complement code (CRC′). Calculate this redundant check code CRC and can adopt corresponding algorithm: CRC=(D[001]+D[002]+D[003]+...+D[FFE])+0X94, and make the value of CRC constant Equal to "0XFF". Among them, D[001], D[002], D[003]...D[FFE] are the data in the storage address 001, 002, 003...FFE respectively, and "0X94" is a redundant Additional digits, representing the hexadecimal number 94. This redundancy check complementary byte 1012 is the value of the hexadecimal complement number CRC' of the redundancy check code CRC calculated by the central processing unit 2, for example, the value of CRC is "0XFF", and the value of CRC' is "0X00". Therefore, the central processing unit 2 checks the correctness of the data according to whether the complementary relationship between the redundancy check code and the redundancy check complementary code is correct or not, and corrects the erroneous data bits. A byte (BYTE) is composed of eight bits (BIT): B1, B2, B3...B8. The address storage space of this bit is used to store the corresponding bit "0" or "1" to form the corresponding data.

As shown in FIG. 5 , it is a schematic diagram of data error checking and correction of the secure storage system of the secure solid-state memory of the present invention. The central processing unit 2 performs a parity check according to the error check page 102 of the memory block 10 of the solid-state memory 1, and the parity check can be an odd (ODD PARITY) check or an even (EVEN PARITY) check. This embodiment uses even parity to describe: when the corresponding data byte contains an odd number of "1", the parity bit is "1"; when the corresponding data byte contains an even number of "1" , the parity bit is "0". Before the data is sent to the central processing unit 2, the parity bit and the corresponding 8-bit data are written into the solid-state memory 1 at the same time. If the parity check detects an even number of "1", the data is considered valid, and the parity bit is removed, and then the 8-bit data is sent to the central processing unit 2 for processing; if the AND bit check detects an odd number of "1", Data is considered invalid and generates a PARITY error. As shown in FIG. 5, if the vertical data (B1, B2, B3...B8) of multiple data pages 101 of one of the memory blocks 10 is summed to obtain an odd number of "1"s per bit (BIT), However, the corresponding bit in the error check page 102 is "0", and the data in the corresponding data page 101 is considered invalid and a PARITY error occurs. Central processing unit 2 determines whether the horizontal data (D[001], D[002], D[002], D[003]...D[FFE]) whether there is an error. Therefore, the parity (PARITY) check and the redundancy check are completed, and the error check of the interleaving of the vertical data and the horizontal data of the solid-state memory 1 is completed, and the corresponding erroneous data is corrected. This horizontal data error check refers to that the central processing unit 2 utilizes the redundancy check code and the redundancy check complementary code of the data page 101 to carry out redundancy check to the horizontal data in the data page 101; The processor 2 performs a parity check on the vertical data in the data block 10 using the parity code in the error check page 102 . In the present embodiment, the error bit "EEROR BIT" is "1", which is the detected error bit, which will be rewritten as "0", and the error check page 102 in the memory block 10 is used to write the correct data. Recovery, in order to achieve the purpose of error checking and correction of data, so as to ensure the correct integrity of data.

As shown in FIG. 6 , it is a flow chart of the safe storage method of the solid-state memory of the present invention. First, the mnemonics used in this figure are explained as follows:

SUM represents the sum of the data of a memory block 10 added by each bit;

CRC, representing the redundancy check code of a data page 101, the algorithm that can be adopted is: CRC=(D[001]+D[002]+D[003]+...+D[FFE])+0x94, It is stored in the address FFF of the redundancy check byte 1011 of the data page 101;

CRC' represents the hexadecimal complement of CRC, which is stored in the address FFE of the redundancy check complement byte 1012 of the data page 101 as a redundancy check complement code of a data page 101;

D[4K-2] represents the data of the 4K-2th data byte address of a data page 101, wherein K=1, 2, . . . , n, n is a natural number.

First, the central processing unit 2 sums each data value of the data page 101 in the memory block 10 of the solid-state memory 1, and then adds a redundant additional number "0X94" to obtain the value of the CRC, and calculates its hexadecimal value. Complement the number to obtain the value of CRC' (step S1). For example, the value of CRC is "0XFF", and whether the value of CRC' is "0X00", then central processing unit 2 judges whether the value of CRC' is equal to the value of D[4K-2] (step S2), if CRC' value Not equal to the D[4K-2] value, then the program turns to each data in the storage block 10 of the solid-state memory 1 by the central processing unit 2 to obtain the SUM value by each bit, and sets the error check page 102 The parity check mode is even check (the present invention adopts even check to describe, step S3). Then judge whether the SUM value is an even number of "1" (step S4). If the SUM value is an odd number of "1", then write "1" in the address of the corresponding bit of the error check page 102, that is, after the central processing unit 2 does the SUM=SUM+1 operation (step S5), then the solid state The wrong data bit in the data page 101 in the memory 1 is corrected and stored (step S7), and the program ends at last; Write "0" in the address, after central processing unit 2 does SUM=SUM+0 operation (step S6), program turns to step S7. In step S2, if CRC' is equal to A[4K-2], the central processing unit 2 sums up the data in the memory block 10 of the solid-state memory 1 to obtain a SUM value for each bit, and sets the error check The parity check method of the page 102 is even check (step S8). Then judge whether the SUM value is an even number "1" (step S9), if the SUM value is an odd number "1", then write "1" in the address of the corresponding bit of the error checking page 102, that is, the central processing unit 2 After doing the SUM=SUM+1 operation (step S10), then the program turns to judge whether the SUM value is equal to "0" (step S12), if the SUM value is not equal to "0", then the central processing unit 2 corrects errors in the solid-state memory 1 The error data bit in the error checking page 102 is corrected and stored (step S13), and the program ends at last; if the SUM value is equal to "0", it means that the error data bit stored in the error checking page 102 has no error data, and there is no need to do it. If correct data is restored, the program goes directly to the end. In step S9, if the SUM value is an even number of "1", then write "0" in the address of the corresponding bit of the error checking page 102, that is, central processing unit 2 does SUM=SUM+0 operation (step S11) Afterwards, then the program turns to the step to judge whether the SUM value is equal to "0" (step S12), and if the SUM value is not equal to "0", then the program turns to the step S13; if the SUM value equals "0", then the program directly ends. Through the above method, the redundancy check and the parity check can be completed to respectively interleave the error check of a horizontal data and a vertical data stored in the solid-state memory 1, and correct the error data bit, thereby completing the covered The correct data recovery storage process ensures the correct integrity of the data.

Claims (13)

1. the safe storage system of a solid-state memory is used to recover covered correct data, it is characterized in that, this system comprises:

One solid-state memory, this solid-state memory is connected in a central processing unit, and it logically is divided into a plurality of memory blocks, and this memory block comprises:

Many data pages, this data page comprise the complementary byte of a plurality of data bytes, a redundancy check byte and a redundancy check; And

One error-checking page or leaf, this error-checking page or leaf comprises a parity byte.

2. the safe storage system of solid-state memory as claimed in claim 1 is characterized in that, the storage space volume of described memory block is a fixed value.

3. the safe storage system of solid-state memory as claimed in claim 1 is characterized in that, the storage space volume of described data page and described error-checking page or leaf is a fixed value.

4. the safe storage system of solid-state memory as claimed in claim 1 is characterized in that, described parity byte is used to store a parity check code.

5. the safe storage system of solid-state memory as claimed in claim 1 is characterized in that, described redundancy check byte is used to store a redundancy check code, and the complementary byte of described redundancy check, is used to store a redundancy check mutual-complementing code.

6. the safe storage system of solid-state memory as claimed in claim 5 is characterized in that, described redundancy check code and described redundancy check mutual-complementing code possess complementary relationship, and it is used for the data of described data page are carried out bug check and correction.

7. the method for secure storing of a solid-state memory is used to recover covered correct data, its feature with, this method may further comprise the steps:

Central processing unit adds the General Logistics Department with the data of each data byte of a data page by each, again with a redundant additional number sue for peace a redundancy check code CRC;

Central processing unit calculates the value of the sexadecimal complement CRC ' of described redundancy check code CRC;

One central processing unit reads the data of the data byte of a memory block, generates in the corresponding parity byte address that a parity check code is stored in an error-checking page or leaf, and sets parity check system;

Central processing unit utilizes redundancy check mode and parity check system to check horizontal data and a longitudinal data are staggered respectively; And

When being checked through an error in data, this central processing unit is promptly revised the corresponding error data bit, utilizes described error-checking page or leaf to carry out the recovery of correct data.

8. the method for secure storing of solid-state memory as claimed in claim 7 is characterized in that, described redundant additional number is sexadecimal number " 0X94 ".

9. the method for secure storing of solid-state memory as claimed in claim 7, it is characterized in that, calculate the value of described redundancy check code CRC, make it be constantly equal to " 0XFF ", respective algorithms can adopt: CRC=(D[001]+D[002]+D[003]+... + D[FFE])+0X94, wherein D[001], D[002], D[003] ... D[FFE] be respectively the 001st, the 002nd, the 003rd ... data in FFE address.

10. the method for secure storing of solid-state memory as claimed in claim 7 is characterized in that, described CRC ' expression redundancy check mutual-complementing code is carried out the redundancy check of the horizontal data of described data page jointly with described redundancy check code.

11. the method for secure storing of solid-state memory as claimed in claim 7 is characterized in that, described correction is meant and changes the numerical value of misdata position " 1 " into " 0 ", or the numerical value " 0 " of misdata position is rewritten as " 1 ".

12. the method for secure storing of solid-state memory as claimed in claim 7 is characterized in that, described error-checking page or leaf is used to finish the parity checking of the longitudinal data of described memory block.

13. the method for secure storing of solid-state memory as claimed in claim 12 is characterized in that, described parity checking can be selected odd or even parity check for use.