CN1610139A - Micro refrigerator and its preparation method - Google Patents

Abstract

The micro refrigerator is used in raising the temperature control of laser device and computer CPU, improving the work efficiency of chip and prolonging their service life. The refrigerator is one multilayer structure including the high temperature area, metal layer, P-type semiconductor, N-type semiconductor, upper metal layer and low temperature area successively from bottom to top. It is prepared with superlattice material Si and Ge and the preparing process includes combined chemical plating process and oxide isolating process to form several stages of micro refrigerator, forming plasma reinforced chemical vapor deposited SiO2 film as protecting layer and chemical copper plating to form metal film in the bonding surfaces between P-type and N-type semiconductors.

Description

Micro refrigerator and its preparation method

Technical field

The invention is a technology for improving the temperature control of laser devices and computer CPUs, improving the heat dissipation inside the chip, thereby improving the working efficiency of the device chip and prolonging the service life. It belongs to the field of advanced manufacturing and automation technology.

Background technique

Currently, thermoelectric materials can form solid-state coolers and generators. Solid-state thermoelectric generators and refrigerators use the Peltier effect of electrons to take away excess heat, and they mainly face the problem of thermoelectric conversion efficiency. The performance index of thermoelectric cooling devices is generally described by the quality coefficient ZT, and its mathematical expression is: ZT=S ² σT/k, where T is the absolute temperature, S is the Seebeck coefficient of the material, and σ is the electrical conductivity , k is the thermal conductivity.

Most of the thermoelectric materials currently used in the industry are bulk materials. For conventional thermoelectric devices, the minimum thickness of the thermal unit is generally around a few millimeters. Currently, bulk thermoelectric coolers generally use Bi ₂ Te ₃ or thermoelectric materials based on it. However, the processing technology of bulk Bi ₂ Te ₃ or its alloys is not compatible with IC (Integrated Circuit) technology. Selecting microstructured thermoelectric materials that are compatible with IC process and have high thermoelectric quality index is the key to design high-performance thermoelectric devices.

For micro-cooling devices, the thickness of the heat unit can be as thin as 1-10 μm, and as thick as 100 μm. Since the micro-device adopts thin-film technology, the contact thermal resistance and contact resistance of the interface become important factors affecting the performance of the device, and the selection of materials also affects the performance of the device. The main challenges faced by this type of microcooler are the selection of thermoelectric materials and their fabrication process. In order to improve the workability of micro-devices, some micro-fabrication processes have been proposed one after another, including electrochemical deposition, electroplating and sputtering to realize metal film formation. When the P-type and N-type thermocouple pairs are formed by electrochemical deposition, the height of the thermocouple pair legs can be flexibly controlled in the range of tens of microns. The disadvantage of this process is that it cannot guarantee the uniformity of the film quality and the purity of the material, which is restricted from the surface. the working efficiency of the device. Thin film electroplating process is used to deposit V and VI compound films to form thermocouples. The difference between this process and the electrochemical deposition process is that the P-type and N-type thermal units are deposited on different substrates, resulting in subsequent The bonding process is very difficult. However, the thermocouple units of P-type and N-type BiTe alloys are formed on the SOI substrate by sputtering film-making process, and the stability of the device is better. As a refrigerator, a temperature difference of about 10K can be formed, and the size of the device can be controlled at 100μm ² ∽1mm ² . However, this process requires strict control of the thickness of the thermoelectric unit. During the bonding process of each substrate, if the unit thickness is different, the device will be separated and an open circuit will be formed. Secondly, the precise positioning of the thermal unit and the metal electrode position is also required. to reduce contact resistance. On the other hand, since the materials used are V and VI compound thin films, the thermoelectric quality index ZT of the system cannot break through the limit of bulk materials, thus limiting the working efficiency of the device.

Contents of Invention

Technical content: In order to overcome the deficiencies in the materials and processing technology of existing thermoelectric refrigerators, the present invention provides a multi-stage micro-refrigerator and its preparation method, which improves the reliability of the system and improves the device The work efficiency brings great convenience to the manufacturing process.

Technical solution: The refrigerator has a multi-layer structure, the lowermost layer is a high-temperature area, and two metal layers are respectively arranged on the high-temperature area, a P-type semiconductor is arranged on one of the metal layers, and a P-type semiconductor is arranged on the other metal layer. The N-type semiconductor is provided with an integral upper metal layer on the P-type semiconductor and the N-type semiconductor, and the upper metal layer is a low-temperature region.

The specific structure of the refrigerator is divided into upper and lower parts; the lowermost layer of the lower part is the Si substrate of the P-type semiconductor, and a buffer layer, that is, an undoped layer of the P-type semiconductor, is arranged on the Si substrate of the P-type semiconductor. On the undoped layer of the P-type semiconductor, the first heavily doped layer of the P-type semiconductor is arranged at intervals, and the superlattice layer of the P-type semiconductor is arranged on the first heavily doped layer of the P-type semiconductor. The second heavily doped layer of P-type semiconductor is provided on the superlattice layer of P-type semiconductor, and the lightly doped layer of P-type semiconductor is provided on the second heavily doped layer of P-type semiconductor; the uppermost layer of the upper part It is a Si substrate of N-type semiconductor, an undoped layer of N-type semiconductor is provided under the Si substrate of N-type semiconductor, and a first heavily doped layer of N-type semiconductor is provided at intervals under the undoped layer of N-type semiconductor. The mixed layer is provided with a superlattice layer of N-type semiconductor under the first heavily doped layer of N-type semiconductor, and a second heavily doped layer of N-type semiconductor is arranged under the superlattice layer of N-type semiconductor. A lightly doped layer of N-type semiconductor is arranged under the second heavily doped layer of N-type semiconductor; the upper part and the lower part intersect and coincide, and the metal film formed by electroless plating is filled in the coincident part. The unit thickness of the refrigerator is in the range of 1-10 μm.

The invention adopts the silicon-germanium superlattice material in III-V group semiconductor materials or IV group semiconductor materials, and at the same time combines the electroless plating process and the oxide isolation process to form a multi-stage miniature refrigerator. Plasma-enhanced chemical vapor deposition (PECVD) silicon dioxide thin film protection layer, silicon dioxide can isolate the current in the P-N direction, and realize a single flow mode of current, thereby avoiding the short circuit problem of the thermoelectric unit in the middle stage and improving the reliability of the system work performance, to achieve array cooling. The electroless plating process is used to form a metal film on the thermoelectric unit, which can achieve the uniformity of the thin film metal and the purity of the material, thereby reducing the contact distribution resistance and improving the working efficiency of the device. At the same time, the electroless plating process does not need to strictly control the temperature of the thermoelectric unit. Thickness, that is, the thickness of the thermoelectric unit can be different during the bonding process, and precise positioning of the thermal unit and the metal electrode is not required in order to reduce the contact resistance. This brings great convenience to the manufacturing process.

The concrete preparation method of the present invention is:

Step 1: Pre-treat the substrate:

The second step: use MBE (molecular beam epitaxy) or MOCVD (metal oxide chemical vapor deposition) method to separate

Do not grow P-type and N-type superlattice films on two silicon substrates, and there are

The covering layer has a buffer layer under the superlattice film, and the bottom is a silicon substrate;

Semiconductor Structure Table Remark Overlay lightly doped layer Heavily doped layer (same doping concentration as superlattice layer) superlattice layer The buffer layer Heavily doped layer (same doping concentration as superlattice layer) Undoped layer (for insulation) Silicon substrate low resistance

Step 3: Etching once: respectively etch on the already grown P-type and N-type semiconductors, etch

To the first heavily doped layer of P-type and N-type semiconductors (that is, the lightly doped layer, the second heavily doped layer and

The superlattice layer is etched away);

Secondary etching: as a photoresist protective layer, using reactive ion etching, etching to P-type and N-type semiconductors

The buffer layer (that is, etch the first heavily doped layer), and then remove the remaining photoresist;

The fourth step: plasma enhanced chemical vapor deposition (PECVD) silicon dioxide film as a protective layer;

Step 5: Plasma bombards the excess silicon dioxide, leaving only the silicon dioxide on the sidewalls of the superlattice:

Step 6: Make a photoresist layer, that is, to protect the bottom surface of the P-type and N-type semiconductors and the sides of both ends with photoresist

layer;

Step 7: Bond the P-type and N-type semiconductors;

Step 8: Plating a thin-film metal layer by electroless plating process, so that the bonding surface between P-type and N-type semiconductors is in contact

Close, uniform coating film;

Step 9: Strip the photoresist.

Beneficial effects: the microstructure material provides a wide space for improving the quality factor ZT, which can realize point cooling and improve the cooling efficiency per unit area, and is made of silicon germanium superlattice material in III-V or IV metal materials Thermoelectric devices are process compatible with microprocessors. Using silicon dioxide as a protective layer can isolate the current in the P-N direction and realize a single flow mode of the current, thus avoiding the short circuit problem of the thermoelectric unit in the middle stage, improving the reliability of the system, and realizing array refrigeration. The metal film formed by the electroless plating process has good consistency, not only the total resistance in series is significantly better than other metal film forming processes, but also the distributed resistance is better than other processes, which can solve the problem of contact resistance. At the same time, the electroless plating process can be used to form a film The selectivity of the metal can be realized to form a metal film selectively, which is conducive to improving the working stability of the multi-stage thermoelectric unit.

The multi-stage solid-state thermoelectric material refrigerator of the present invention uses the Peltier effect of electrons to take away excess heat to improve refrigeration efficiency without strictly controlling the thickness of the thermoelectric unit, that is, the thickness of the thermoelectric unit in the bonding process Thickness can vary. The electroless plating process solves the contact problem between the metal and the semiconductor, improves the consistency of the metal film coverage and reduces the contact resistance.

Description of drawings

Figure 1: Schematic diagram of a refrigerator, schematic diagram of the Peltier effect. In the figure: 1. High temperature area, 2. Metal layer, 3. P-type semiconductor, 4. Upper metal layer, 5. Low temperature area, 6. N-type semiconductor.

Figure 2-1 to Figure 2-11 are schematic diagrams of each step in the preparation steps of the present invention,

Figure 2-1: Schematic diagram of the superlattice structure grown on a silicon substrate,

Figure 2-2: Schematic diagram of the structure after one etching,

Figure 2-3: Schematic diagram of the structure after secondary etching,

Figure 2-4: Schematic diagram of plasma enhanced chemical vapor deposition (PECVD) silicon dioxide protective layer,

Figure 2-5, Figure 2-6: Schematic diagram of plasma bombardment of excess silicon dioxide film,

Figure 2-7, Figure 2-8: Schematic diagram of making photoresist layer,

Figure 2-9: Schematic diagram of P and N type semiconductor bonding,

Figure 2-10: Schematic diagram of the electroless plating process for multi-stage thermoelectric units,

Figure 2-11: Schematic diagram of stripping photoresist,

In the figure: 7. Si substrate of P-type semiconductor, 8. Undoped layer of P-type semiconductor, 9. First heavily doped layer of P-type semiconductor, 10. Superlattice layer of P-type semiconductor, 11.P The second heavily doped layer of the P-type semiconductor, 12. The lightly doped layer of the P-type semiconductor, 13. The silicon dioxide film on the P-type semiconductor, 14. The Si substrate of the N-type semiconductor, 15. The undoped layer of the N-type semiconductor Miscellaneous layer, 16. The first heavily doped layer of N-type semiconductor, 17. The superlattice layer of N-type semiconductor, 18. Silicon dioxide film on N-type semiconductor, 19. The second heavily doped of N-type semiconductor Layer, 20. Lightly doped layer of N-type semiconductor, 21. Photoresist layer on N-type semiconductor, 22. Photoresist layer on P-type semiconductor, 23. Metal thin film formed by electroless plating.

Detailed ways

The invention adopts the combination of the electroless metal plating film forming process and the oxide isolation process to form a multi-stage miniature refrigerator. The refrigerator has a multi-layer structure, and the lowermost layer is a high-temperature area 1, and two metal layers 2 are respectively arranged on the high-temperature area 1, a P-type semiconductor 3 is arranged on one of the metal layers 2, and a P-type semiconductor 3 is arranged on the other metal layer 2. An N-type semiconductor 6 is arranged on it, an integral upper metal layer 4 is arranged on the P-type semiconductor 3 and the N-type semiconductor 6 , and a low-temperature region 5 is arranged on the upper metal layer 4 .

The concrete structure of this refrigerator is divided into upper and lower two parts; Layer 8, the first heavily doped layer 9 of P-type semiconductor is arranged at intervals on the undoped layer 8 of P-type semiconductor, and the first heavily doped layer 9 of P-type semiconductor is provided with the layer of P-type semiconductor Superlattice layer 10 is provided with the second heavily doped layer 11 of P-type semiconductor on the superlattice layer 10 of P-type semiconductor, and is provided with the second heavily doped layer 11 of P-type semiconductor on the second heavily doped layer 11 of P-type semiconductor. Lightly doped layer 12; the uppermost layer of the upper part is the Si substrate 14 of N-type semiconductor, and the undoped layer 15 of N-type semiconductor is provided under the Si substrate 14 of N-type semiconductor, and the undoped layer of N-type semiconductor The first heavily doped layer 16 of N-type semiconductor is arranged at intervals under 15, the superlattice layer 17 of N-type semiconductor is provided under the first heavily doped layer 16 of N-type semiconductor, and the superlattice layer 17 of N-type semiconductor is arranged A second heavily doped layer 19 of N-type semiconductor is provided under the lattice layer 17, and a lightly doped layer 20 of N-type semiconductor is provided under the second heavily doped layer 19 of N-type semiconductor; the upper and lower parts The intersection coincides, and the metal film 23 formed by electroless plating is filled in the joint. The unit thickness of the refrigerator is in the range of 1-10 μm.

Using III-V semiconductor materials or silicon germanium superlattice materials in IV semiconductor materials, the multi-level micro-cooler is formed by combining the chemical copper plating process and the silicon dioxide thin film process. Plasma-enhanced chemical vapor deposition of silicon dioxide film is used as a protective layer, and the bonding surface of P and N-type semiconductors (lightly doped layer of P-type semiconductor, first heavily doped layer and N-type semiconductor) are bonded by electroless copper plating process. Metal film formation is realized between the first heavily doped layer and the lightly doped layer.

Concrete preparation method is:

The first step: Pretreatment of the silicon substrate 7 of the P-type semiconductor and the silicon substrate 14 of the N-type semiconductor: pickling with hydrofluoric acid (HF) first, and then ultrasonic cleaning with deionized water,

The second step: grow on the silicon substrate 7 of the P-type semiconductor by MBE (molecular beam epitaxy). The superlattice layer 10 (Si _0.7 Ge _0.3 /Si) of the P-type semiconductor has a film thickness of 3000 Nano, in this superlattice thin film, it is doped while growing Si _0.7 Ge _0.3 layer, the doping concentration is 6.47×10 ¹⁹ cm ^-3 , and it is not doped when growing Si layer, In one period of the superlattice film, the thickness of Si _0.7 Ge _0.3 is 5 nm, and the thickness of Si is 10 nm.

Above the superlattice film is a layer of Si _0.9 Ge _0.1 film, which is the second heavily doped layer 11 of the P-type semiconductor. The thickness of this film is 250 nanometers, and its doping concentration is 6.47×10 ¹⁹ cm ^-3 , there is a Si _0.9 Ge _0.1 thin film on this layer, that is, the lightly doped layer 12 of P-type semiconductor. The thickness of this thin film is 250 nm, and its doping concentration is greater than or equal to 1×10 ²⁰ cm ^-3 . Below the superlattice film is a Si _0.9 Ge _0.1 layer, which is the first heavily doped layer 9 of the P-type semiconductor. The thickness of this film is 1000 nm, and the doping concentration is 6.47×10 ¹⁹ cm ^-3 . There is also a Si _0.9 Ge _0.1 layer under the layer, that is, the buffer layer 8 of the P-type semiconductor, and the thickness of this layer is 1000 nanometers. In all doping, the doping element we choose is sodium, which is P-type doping.

Also use the MBE method to process an N-type semiconductor on another expensive substrate. The doping element is neodymium. The doping concentration is shown in the table, and its size is the same as that of the P-type doping.

P-type superlattice structure detailed table Material Detailed description Remark SiG layer(12) Si _0.9 Ge _0.1 : doping concentration ≥ 1×10 ²⁰ cm ^-3 Thickness: 300nm SiG layer(11) Si _0.9 Ge _0.1 : doping concentration 6.47×10 ¹⁹ cm ^-3 , thickness 10nm Thickness 250nm P-type superlattice layer(10) Si _0.7 Ge _0.3 : doping concentration 6.47×10 ¹⁹ cm ^-3 , thickness 5nm 200 cycles, total thickness 3000nm Si: no doping, thickness 10nm SiGe layer(9) Si _0.9 Ge _0.1 : doping concentration 6.47×10 ¹⁹ cm ^-3 Thickness 1000nm SiGe layer(8) Si _0.9 Ge _0.1 : no doping Thickness 1000nm Si substrate(7) low resistance low resistance

N-type superlattice structure detailed table Material Detailed description Remark SiG layer(20) Si _0.9 Ge _0.1 : doping concentration ≥ 1×10 ²⁰ cm ^-3 Thickness: 300nm SiG layer(19) Si _0.9 Ge _0.1 : doping concentration 3.42×10 ¹⁹ cm ^-3 , thickness 10nm Thickness 250nm N-type superlattice layer(17) Si _0.7 Ge _0.3 : doping concentration 3.42×10 ¹⁹ cm ^-3 , thickness 5nm 200 cycles, total thickness 3000nm Si: no doping thickness 10nm SiG layer(16) Si _0.9 Ge _0.1 : Doping concentration 3.42×10 ¹⁹ cm ^-3 Thickness 1000nm SiG layer(15) Si _0.9 Ge _0.1 : no doping Thickness 1000nm Si substrate(14) low resistance low resistance

The third step: one etching, etch the already grown P-type and N-type semiconductors in a certain shape, etch to the bottom Si _0.9 Ge _0.1 heavily doped layer, that is, the first layer of P-type semiconductor Doped layer 9, the first heavily doped layer 16 of N-type semiconductor, that is, the top Si _0.9 Ge _0.1 film layer, that is, the second heavily doped layer 11 of P-type semiconductor, the lightly doped layer 12 of P-type semiconductor, N The second heavily doped layer 19 of the N-type semiconductor, the lightly doped layer 20 of the N-type semiconductor, and the superlattice film layer below it, that is, the superlattice layer 10 of the P-type semiconductor, and the superlattice layer 17 of the N-type semiconductor. etched away. The entire etching thickness is 3500 nm.

Secondary etching, as a photoresist protective layer (using negative resist), the thickness is not less than the thickness of the superlattice, harden the film at 120°C for 5 minutes. Reactive ion etching ends at the Si _0.9 Ge _0.1 undoped layer under the superlattice film, that is, the undoped layer 8 of the P-type semiconductor and the undoped layer 15 of the N-type semiconductor, and then removes the remaining photoresist.

Step 4: Plasma Enhanced Chemical Vapor Deposition (PECVD) silicon dioxide protective layer, that is, the silicon dioxide film 13 on the P-type semiconductor and the silicon dioxide film 18 on the N-type semiconductor. The deposition thickness is 3000 Angstroms.

Step 5: Plasma bombards the excess silicon dioxide, leaving only the silicon dioxide on the sidewalls of the superlattice.

Step 6: Make a photoresist protection layer, that is, a photoresist layer 21 on the N-type semiconductor, and a photoresist layer 22 on the P-type semiconductor (use negative glue).

Step 7: Anodic bonding of the P-type and N-type semiconductors, and the P-type and N-type semiconductors are bonded together under the action of an electrostatic field.

The eighth step: adopt the electroless copper plating process between the bonding surfaces of P and N-type semiconductors (the lightly doped layer 12 of the P-type semiconductor, the first heavily doped layer 9 of the P-type semiconductor and the first heavily doped layer 9 of the N-type semiconductor respectively) The bonding surface between the heavily doped layer 16 and the lightly doped layer 20 of the N-type semiconductor) realizes metal film formation.

1. Pretreatment: 1.) Ultrasonic cleaning in water for 5 minutes; 2.) Ultrasonic cleaning in alcohol solution at room temperature; 3.) Ultrasonic cleaning in deionized water; 4.) Use 4% NaOH solution etching; 5.) Ultrasonic cleaning in water; 6.) Invasion in photosensitive solution for ten minutes; 7.) Deionized water cleaning; 8.) Invasion in catalytically active solution for five minutes; 9.) Rinse with deionized water.

2. Electroless copper plating: In the plating solution: HCHO is a reducing agent, and KNaC ₄ H ₄ O ₅ ·4H ₂ O and ethylenediaminetetraacetic acid (EDTA) are complexing agents.

Table 3 Composition of photosensitive solution and catalytic active solution Chemicals concentration photosensitive solution SnCl ₂ ·H ₂ O 16g/l HCl 30g/l catalytically active solution _{PbCl2 PbCl2} HCl HCl

Table 4 The solution composition of electroless copper plating Chemicals concentration operating conditions CuSO ₄ 5H ₂ O 30g/l PH: 12.5 (adjusted by NaOH) KNaC ₄ H ₄ O ₅ 4H ₂ O 50g/l EDTA 10g/l Bath temperature: 30～80℃ HCHO (37%) 30g/l

Step 9: peel off the photoresist layer, that is, the photoresist layer 21 on the N-type semiconductor and the photoresist layer 22 on the P-type semiconductor.

In FIG. 1 , when current flows from the metal layer 4 to the P-type semiconductor 3 , heat will be absorbed at the contact, thereby generating a low-temperature region 5 . Similarly, when the current flows from the N-type semiconductor 6 to the metal layer 4, the contact will also absorb heat, so the end connected with the metal continuously absorbs heat from the surrounding environment, so that the temperature of the surrounding environment drops to form a refrigerator. Instead, a temperature difference across the thermoelectric material will generate an electric current, creating a tiny current generator.

In Fig. 2-11, the current flows from the first heavily doped layer 16 of the N-type semiconductor to the metal film 23 formed by electroless plating, flows to the lightly doped layer 12 of the P-type semiconductor, and flows to the second heavily doped layer of the P-type semiconductor. Layer 11 flows to the superlattice layer 10 of the P-type semiconductor, and then flows to the first heavily doped layer 9 of the P-type semiconductor. Since the buffer layer 8 of the P-type semiconductor is insulating, the current flows to the metal film 23 formed by electroless plating, and then flows to the P-type semiconductor material, so that the current can flow in a single direction and the current can be realized from N→P→N→ P.... Therefore, it can continuously absorb heat from the surrounding environment, so that the surrounding temperature drops, thus forming a multi-stage solid-state refrigerator.

Claims (4)

1, a kind of miniature refrigerator, it is characterized in that this refrigerator is a multi-layer structure, the lowermost layer is a high-temperature zone (1), is respectively provided with two metal layers (2) on the high-temperature zone (1), in which One metal layer (2) is provided with a P-type semiconductor (3), another metal layer (2) is provided with an N-type semiconductor (6), and on the P-type semiconductor (3) and the N-type semiconductor (6) An integral upper metal layer (4) is provided, and a low-temperature region (5) is formed above the upper metal layer (4). 2. The miniature refrigerator as claimed in claim 1, characterized in that the specific structure of the refrigerator is divided into upper and lower parts; the lowermost layer of the lower part is the Si substrate (7) of P-type semiconductor, and the P-type The Si base (7) of the P-type semiconductor is provided with a buffer layer, that is, the undoped layer (8) of the P-type semiconductor, and the first layer of the P-type semiconductor is arranged at intervals on the undoped layer (8) of the P-type semiconductor. The heavily doped layer (9), on the first heavily doped layer (9) of the P-type semiconductor is provided with a P-type semiconductor superlattice layer (10), on the P-type semiconductor superlattice layer (10) A second heavily doped layer (11) of P-type semiconductor is provided, and a lightly doped layer (12) of P-type semiconductor is arranged on the second heavily doped layer (11) of P-type semiconductor; the uppermost layer of the upper part It is a Si substrate (14) of N-type semiconductor, an undoped layer (15) of N-type semiconductor is arranged under the Si substrate (14) of N-type semiconductor, and a phase is formed under the undoped layer (15) of N-type semiconductor. Intervals are provided with the first heavily doped layer (16) of N-type semiconductor, and under the first heavily doped layer (16) of N-type semiconductor, a superlattice layer (17) of N-type semiconductor is provided. A second heavily doped layer (19) of an N-type semiconductor is provided under the superlattice layer (17) of the semiconductor, and a lightly doped layer of the N-type semiconductor is provided under the second heavily doped layer (19) of the N-type semiconductor. layer (20); the upper and lower parts intersect and match, and the metal film (23) formed by electroless plating is filled in the joint. 3. The micro refrigerator as claimed in claim 1, characterized in that the cell thickness of the refrigerator is in the range of 1-10 μm. 4, a kind of preparation method of miniature refrigerator as claimed in claim 1 is characterized in that adopting the silicon-germanium superlattice material in III-V group semiconductor material or IV group semiconductor material, adopts electroless plating process and oxidation simultaneously A multi-stage micro-refrigerator is formed by combining the material isolation process; the silicon dioxide film protective layer is deposited by plasma enhanced chemical vapor phase, and the metal film is formed between the bonding surfaces of P and N-type semiconductors by electroless copper plating process. The preparation method is: The first step: pre-treat the substrate; The second step: grow P-type and N-type superlattice films on two silicon substrates by molecular beam epitaxy or metal oxide chemical vapor deposition, and there is a covering layer on the superlattice film. There is a buffer layer under the film, and the bottom is a silicon substrate; The third step: one etching: respectively etch the grown P-type and N-type semiconductors, etch to the first heavily doped layer of the P-type and N-type semiconductors, that is, the lightly doped layer, The second heavily doped layer and the superlattice layer are etched away: Secondary etching: as a photoresist protective layer, use reactive ion etching, etch to the buffer layer of P-type and N-type semiconductors, that is, the first layer The doped layer is etched away, and then the remaining photoresist is removed; Step 4: Plasma-enhanced chemical vapor deposition of silicon dioxide film as a protective layer; Step 5: Bombard the excess silicon dioxide with plasma, leaving only the silicon dioxide on the sidewall of the superlattice; Step 6: Make a photoresist layer, that is, make the bottom surface of the P-type and N-type semiconductors, and the sides of both ends as a photoresist protective layer; Step 7: Bond the P-type and N-type semiconductors; Step 8: Plating a thin-film metal layer by electroless plating technology, so that the bonding surface between the P-type and N-type semiconductors is in close contact, and the coating film is uniform; Step 9: Strip the photoresist.

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