CN1610114A - A three-dimensional multilayer planar complementary metal oxide semiconductor device structure and its preparation method - Google Patents
A three-dimensional multilayer planar complementary metal oxide semiconductor device structure and its preparation method Download PDFInfo
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Abstract
本发明涉及一种三维互补金属氧化物半导体器件(CMOS)结构及其制备方法。结构上特征是PMOS和NMOS处在不同的平面上，但在同一平面上仍是传统的平面MOS晶体管，是一种CMOS结构。先在体硅或SOI衬底上制备PMOS或NMOS，然后利用化学机械抛光、低温键合和低温剥离工艺在器件层上制备另一层SOI结构，在第二层的SOI结构上制备NMOS或PMOS。如此反复，形成多层MOS结构。NMOS与PMOS之间用层间连线相联，形成三维CMOS结构。采用常规的MOS工艺实现高密度器件集成，工艺方法简单，在同样CMOS数量的情况下，可减少光刻次数，减小器件单元面积，并可以减少金属互联线的数目，提高器件的速度。
The invention relates to a three-dimensional complementary metal oxide semiconductor device (CMOS) structure and a preparation method thereof. The structural feature is that PMOS and NMOS are on different planes, but they are still traditional planar MOS transistors on the same plane, which is a CMOS structure. First prepare PMOS or NMOS on bulk silicon or SOI substrate, then prepare another layer of SOI structure on the device layer by chemical mechanical polishing, low temperature bonding and low temperature lift-off process, and prepare NMOS or PMOS on the second layer of SOI structure . Repeatedly, a multi-layer MOS structure is formed. NMOS and PMOS are connected by interlayer wiring to form a three-dimensional CMOS structure. The conventional MOS process is used to realize high-density device integration, and the process method is simple. In the case of the same number of CMOS, it can reduce the number of photolithography, reduce the unit area of the device, and can reduce the number of metal interconnection lines and increase the speed of the device.
Description
Affiliated field
The present invention relates to a kind of three-dimensional multilayer planar complementary metal oxide semiconductor structure and preparation method thereof.
Background technology
The IC industry is followed the Moor law at present, and the integrated level of device is increasing, and performance doubled the price drop by half in per 18 months.Mainly contain three kinds of methods that improve the device integrated level at present: the characteristic size, increase wafer area, the preparation three-dimensional structure device that reduce device.MOS metal-oxide-semiconductor integrated circuit develop rapidly over the years to 0.13 μ m and even 90nm, has brought earth-shaking variation to semiconductor technology from 0.25 μ m technological development.But be faced with many new problems along with device size reaches the nanometer field, can not meet the demands, need seek new low-K dielectric material or the like as traditional exposure technique.The appearance of therefore new technical problem and high cost make will become more and more difficult from reducing the approach that device feature size improves the device integrated level.Though the technology of " from bottom to top " is also proposed at present, promptly from nano dot, nano wire even atom, molecule, the preparation nano-device, this technology is had got long long way to go from industry.The wafer technology develops into 12 inches from 8 inches, but the increase of wafer size can reduce its rate of finished products.No matter reduce the characteristic size or the increase wafer area of device, every renewal once all needs more exchange device and processing line, and this equipment depreciation to semiconductor factory all causes certain pressure.
The three-dimension device structure just proposed as far back as the 1980s, and had been applied in technology such as memory, as in order to increase capacity area electric capacity being prepared into flute profile; For the integrated level of the static random access memory (SRAM) that improves 6 transistor units will be wherein 2 transistor preparations all the other 4 transistorized above.Owing to be difficult on insulator, prepare monocrystalline silicon, 2 thin-film transistor preparations are on polycrystalline, and when 0.25 μ m technology, obtain bigger commercial profit, but because the existence of crystal boundary makes transistor channel carrier mobility and switch current ratio all lower, when the commodity production that can not meet the demands, and stopped during less than 1.8V of Vdd operating voltage.Lee proposes to adopt annealing process that amorphous silicon is converted into monocrystalline silicon, thus preparation monocrystal thin films transistor (Ga Won Lee, the patent No.: US6,723,589B2).This method can improve the performance of thin-film transistor greatly, but still can not prepare large-area monocrystalline silicon.Proposition PMOS such as S.J.Abou-Samra overlay the 3DMOS on the NMOS, its upper strata monocrystalline silicon layer adopts the method for epitaxial lateral overgrowth, this method can not obtain large-area monocrystalline silicon equally, and treatment temperature is higher, can only obtain two-layer MOS structure (S.J.Abou-Samra, et al., Proc.Of the 8th International Symposium on SOI Technology andDevices, Paris, France, September 1997, PP384-388).Also having a kind of method is the vertical CMOS structure, be about to the MOS structure and stand upside down, source and leakage are placed on upper-lower position, and this method can be decreased to the cellar area of CMOS original 1/4, but the technology of this structure is very complicated, and this structure exists parasitic capacitance (Lamb AC, Riley LS, Hall S, Kunz VD, de Groot CH, Ashburn P, ESSDERC 2001 conference proceedings p347;
Http:// drl.ee.ucla.edu).
In a word, from current 3D CMOS technique, except that special vertical CMOS, the material of preparation thin-film transistor or be polysilicon or be small size monocrystalline silicon.And the CMP technology and be widely used in the technical bonding of SOI and lift-off technology transfer to for large tracts of land monocrystalline silicon provide on the insulating substrate that contains device may.Because the existence of device layer and metal connecting line, K cryogenic treatment becomes a key issue.Commercial at present bonding techniques comprises that it mainly is the commercial SOI substrate of preparation that bonding and back side corrosion (BESOI), smart peeling (Smart-cut) and porous epitaxial silicon layer shift (Eltran) technology, does not need to consider K cryogenic treatment.People's such as Drago Resnik result of study shows that chemically treated two wafer bondings of process are bond strength (Drago Resnik, et al., Sensors and Actuators 80 (2000) 68-76) after 400 ℃ of annealing can reach capacity.In general, dosage is 6 * 10
16Cm
-2Notes hydrogen sheet about 500 ℃, produce and peel off, and the sample exfoliation temperature that boron, hydrogen are annotated altogether is less than 400 ℃ of (T.Hochbauer et al., Journal of Applied Physics, 86 (1999) 4176-4183; In many new, thesis for the doctorate, calendar year 2001).In fact, contain the bonding pad of annotating hydrogen layer or porous silicon layer and under mechanism, can successfully peel off (W.G.En, I.J.Malik, M.A.Bryan et al in room temperature, Proceedings 1998 IEEE International SOIConference, Oct.1998:163).These research work provide technical foundation for low temperature thin film shifts.
Summary of the invention
The purpose of this invention is to provide density three-dimensional CMOS structure of a kind of suitable large-scale production and preparation method thereof.
It is that the number of plies is 2n more than or equal to 2 floor-type structures that the present invention proposes a kind of number of plies, the planar CMOS structure of n 〉=1.In this structure, the three-layer laminated arrangement of cmos layer, and also the NMOS among the CMOS and PMOS are also respectively on different floors.
Described MOS transistor all prepares on the large tracts of land single-crystal semiconductor layer, the preparation of the first floor MOS transistor is on silicon, germanium silicon or strained silicon on body silicon, the insulating barrier, and the above MOS transistor of second floor or second floor prepares strained silicon on germanium silicon or insulating barrier on silicon, the insulating barrier on the insulating barrier.
Described N-channel metal-oxide-semiconductor prepares on different thin film substrate material with the P-channel metal-oxide-semiconductor device.For example N-channel metal-oxide-semiconductor prepares on the strained silicon film substrate, and the preparation of P-channel metal-oxide-semiconductor device is on germanium-silicon thin membrane.
Described three-dimensional planar CMOS structure, it is characterized in that insulating barrier between NMOS and the PMOS comprise silicon dioxide, silicon nitride, aluminium nitride, aluminium oxide or diamond like carbon any one, introduce one deck polysilicon layer in each floor insulating barrier and make heat dissipating layer, around line, form a film oxidation layer simultaneously in order to isolate.
Described three-dimensional planar CMOS structure is characterized in that being linked to each other by interlayer connecting line between NMOS and the PMOS; Line between each CMOS is with tungsten or copper, and copper connecting lines is isolated with low-K dielectric, and the dielectric constant of the low k dielectric of uppermost multilayer interconnection is less than 2, and the dielectric constant of inner each CMOS (Complementary Metal Oxide Semiconductor) device is between 3～2.
Its NMOS and PMOS be on one deck in the described three-dimensional planar CMOS structure, but be still conventional planar technique with the MOSFET on one deck.This structure can improve the integrated level of cmos device greatly on the basis that does not change existing semiconductor process line, shorten the line between the device; In addition,, can not prepare NMOS and PMOS simultaneously at grade,, shorten the process time if both then can not simplify technology at grade because NMOS needs different technology with PMOS.Each layer MOS technology and SOI MOS technology that the present invention proposes are basic identical, all prepare on the single-crystal semiconductor thin film substrate.And the monocrystal thin films substrate is realized by bonding and lift-off technology.Its main processing step comprises: (a) prepare N-channel metal-oxide-semiconductor on body silicon, silicon-on-insulator, germanium silicon or any one substrate of strained silicon.(b) after the ground floor metal oxide semiconductor device structure forms, dielectric in the covering, with cmp method surface of insulating layer is thrown flat, then with the single crystal semiconductor substrate of this substrate and another potting defectiveness layer bonding at room temperature; Peel off behind the bonding, transfer to through single-crystal semiconductor layer on the insulating substrate that contains device; (c) with cmp method that the surface throwing is flat, remove surface impurity, then preparation P-channel metal-oxide-semiconductor device on the second layer; (d) etch fairlead, preparation N-channel metal-oxide-semiconductor and P-channel metal-oxide-semiconductor device interlayer connecting line; (e) after second layer metal oxide semiconductor element structure forms, dielectric in the covering etches the fairlead between the complementary mos device device, and fills out metal lead wire in the hole; With cmp method surface of insulating layer is thrown flat, then with the single crystal semiconductor substrate of this substrate and another potting defectiveness layer bonding at room temperature; Peel off behind the bonding, transfer to through single-crystal semiconductor layer on the insulating substrate that contains device; (f) with cmp method that the surface throwing is flat, remove surface impurity, on the 3rd layer, prepare N-channel metal-oxide-semiconductor then; (g) after three-layer metal oxide semiconductor element structure forms, dielectric in the covering, with cmp method surface of insulating layer is thrown flat, then with the single crystal semiconductor substrate of this substrate and another potting defectiveness layer bonding at room temperature; Peel off behind the bonding, transfer to through single-crystal semiconductor layer on the insulating substrate that contains device; (h) with cmp method that the surface throwing is flat, remove surface impurity, then preparation P-channel metal-oxide-semiconductor device on the 4th layer; (i) etch fairlead, prepare the 3rd layer of N-channel metal-oxide-semiconductor and the 4th layer of P-channel metal-oxide-semiconductor device interlayer connecting line; (j) repeat (a)-(i) step, can prepare the overlaid cmos device; (k) the last multilayer interconnection of preparation.
Among the present invention, the hydrogen in the defective buried regions, boron, helium plasma are introduced by ion implantor, and the semi-conductive thickness of the position of defective buried regions and top layer is by the energy decision of ion implantor.The dosage of hydrogen and helium ion is (1～9) * 10
16Cm
-2, the dosage of boron ion is 5 * 10
15Cm
-2～5 * 10
16Cm
-2Imbedding of porous layer is to adopt earlier electrochemical method to prepare porous silicon, below the epitaxy single-crystal semiconductor layer on the porous silicon substrate again, such single-crystal semiconductor layer with regard to potting porous silicon.
Defect layer of the present invention is a porous silicon, adopts on the porous silicon substrate of electrochemical production single-crystal semiconductor thin films such as epitaxial silicon, again with this epitaxial wafer and the insulating barrier substrate bonding that contains device.
Single-crystal semiconductor thin film more than the 2nd layer or the 2nd layer of the present invention is formed with peeling off by bonding, for adding the strong room temperature bond strength, before bonding substrate surface is carried out chemistry or plasma treatment, and bonding is peeled off the back at long term annealing below 400 ℃.Peel off with low-temperature heat or mechanical means and implement, peel off at the place at defect layer.
In sum, the three-dimensional MOS structure that the present invention proposes has following advantages: 1, can improve the integrated level of device under the situation that does not change existing process conditions, save cost greatly; 2, reduced the line distance and the line number of plies between the device, the line between layer and the layer is if the employing copper connecting lines can use general low-k materials, and not need the polymer of ultralow k value; 3, NMOS and PMOS are prepared on Different Plane, can simplify technology, shorten the process time; 4, NMOS has different requirements with PMOS to substrate under many circumstances, is different to NMOS with the PMOS carrier mobility as strained silicon, and this three-dimensional MOS structure is placed on NMOS and PMOS on the Different Plane, changes backing material neatly as requested.
Description of drawings
Fig. 1 is a three-dimensional multilayer planar CMOS structural representation provided by the invention.Wherein NMOS and PMOS are on different aspects.
Fig. 2 is the process flow diagram of two-layer CMOS structure.
(A) be the ground floor NMOSFET of preparation.Wherein 11 is P type traps, and following substrate can be a body silicon, or SOI; The 12nd, the NMOS gate oxide; The 13rd, the NMOS source region; The 14th, the NMOS drain region; 15 is the NMOS polysilicon gate; The 16th, medium isolation; The 17th, electrode.
(B) be on the ground floor NMOS of preparation, to cover dielectric 21, and then use cmp planarizationization.
(C) be with the substrate shown in Fig. 2 (B) and another substrate bonding that contains defect layer 32.Before bonding, earlier two substrate surfaces are carried out chemical treatment.The 31st, a kind of single-crystal semiconductor thin film layers such as silicon, germanium silicon or strained silicon.The 33rd, silicon substrate.
(D) defect layer 32 is peeled off at low temperatures in the effect of certain calorifics or mechanical force.Semiconductor layer 31 is transferred on the insulating barrier 21.Make a concerted effort in order to improve bonding junction, 400 ℃ of further annealing down.After semiconductor layer 31 carried out CMP polishing, obtain the structure shown in (E).
(F) be preparation second layer MOS structure, this technology and SOI PMOS basically identical on semiconductor layer 31.Wherein 41 is PMOS gate oxides; The 42nd, PMOS drain region, the 43rd, PMOS source region; The 44th, the PMOS polysilicon gate also is the second layer polysilicon layer in the entire device; The 45th, the electrode of each active area.
(G) link with W between two MOSFET.
Fig. 3 is the preparation technology who contains the bubble defect layer in the silicon.
Fig. 3 (A) is injected into hydrogen ion and boron ion in the silicon chip.Form the defect layer 62 shown in Fig. 3 (B).This substrate with contain the insulating substrate bonding of device after, can produce at the defect layer place and peel off, thereby monocrystalline silicon thin film is transferred to the insulating substrate that contains device.(shown in Fig. 2 (C) and 2 (D))
Fig. 4 is the preparation technology who contains the semiconductor chip of bubble defect layer, and wherein, air blister defect layer top is non-Si semiconductor film.
Fig. 4 (A) is an epitaxial semiconductor film 72 on body silicon substrate 71;
Fig. 4 (B) is injected into semiconductor layer with boron, hydrogen ion, or semiconductor layer and body silicon are at the interface; Form the defect layer 73 shown in Fig. 4 C.
Fig. 5 is the preparation technology who contains the semiconductor chip of porous silicon defect layer.
81 is heavy mixed silicon slices among Fig. 5 (A);
Silicon chip 81 is placed on HF and alcoholic solution, adopts anodised method to form the porous silicon 82 shown in Fig. 5 B;
Fig. 5 (C) is an epitaxial semiconductor film 73 on porous silicon, so just formed the semiconductor chip that contains porous silicon layer, this substrate with contain the insulating substrate bonding of device after, can produce at the defect layer place and peel off, thereby semiconductor layer is transferred to the insulating substrate that contains device.(shown in Fig. 2 C and 2D)
Fig. 6 is the three-dimensional multilayer planar CMOS of copper connecting lines.103 and 105 is CMOS of different aspects, and each CMOS is superimposed upon on the nMOS by pMOS and forms.102 and 108 is respectively n layer and n+1 layer Cu line, because the distance between two-layer is shorter, layer can be with general low k dielectric material with the spacer medium 100 and 104 between the layer, and top layer line 107 is then with material 106 isolation of extremely hanging down the k value.
Fig. 7 is the three-dimensional multilayer planar CMOS structure that has added heat-conducting layer.Because general insulating barrier heat conductivility all than silicon difference, in order to prevent that the accumulation of heat causes self-heating effect in the device, adds one deck polysilicon layer 115 between every layer insulating; Around line, form a film oxidation layer simultaneously in order to isolate.
Specific embodiment
Following examples will help to understand the present invention, but not limit content of the present invention.
Embodiment 1:
1. prepare NMOS on P type body silicon substrate, concrete step is as follows: (1) growth 60nm thin oxygen layer (2) deposit silicon nitride 150nm on oxide layer; (3) place photoetching and place B inject; (4) surfaces nitrided silicon and silica protective layer are removed in place oxidation; (5) form gate oxide; (6) polysilicon deposition; (7) polysilicon photoetching; (8) source, drain region are injected; (9) low-temperature oxidation; (10) fairlead photoetching, deposit aluminium; (11) anti-carve aluminium, alloying; (referring to Fig. 2 (A))
2. capping oxidation silicon layer on NMOS carries out planarization with the method for chemico-mechanical polishing, and surperficial r.m.s. roughness is less than 1nm; (referring to Fig. 2 (B))
3. implantation dosage is 5 * 10 on N type body silicon substrate
16Cm
-2Hydrogen ion and dosage be 1 * 10
15Cm
-2The boron ion; (referring to Fig. 3)
4. NMOS substrate and the injection sheet that is coated with silicon oxide layer carried out plasma treatment, after in RCA1 that adjusts and RCA2, cleaning then, bonding in the bonding machine; (referring to Fig. 2 (C)
5. bonding pad was annealed 5 minutes down at 300-400 ℃, bonding pad is peeled off at notes hydrogen layer place.In order to improve bond strength, annealed 4 hours down at 400 ℃;
6. stripper surface is thrown flat with CMP; (referring to Fig. 2 (E))
7. prepare PMOS on second layer monocrystalline silicon, concrete steps are as follows: (1) long thin oxygen 60nm; (2) deposit silicon nitride 150nm on oxide layer; (3) place photoetching and place P inject; (4) surfaces nitrided silicon and silica protective layer are removed in place oxidation; (5) form gate oxide; (6) polysilicon deposition; (7) polysilicon photoetching; (8) source, drain region are injected; (9) low-temperature oxidation.(referring to Fig. 2 (F))
8. etch the fairlead between the two MOS drain electrode, insert tungsten after, the tungsten on surface is removed; (referring to Fig. 2 (G))
9. photoetching aluminum lead hole, deposit aluminium;
10. anti-carve aluminium, alloying.
Embodiment 2:
1. on the germanium silicon substrate, prepare NMOS; (referring to Fig. 2 (A))
2. capping oxidation silicon layer on NMOS carries out planarization with the method for chemico-mechanical polishing, and surperficial r.m.s. roughness is less than 1nm; (referring to Fig. 2 (B))
3. adopt high vacuum chemical gas-phase deposition system epitaxial growth Ge silicon thin film on silicon substrate.Before load sample, soak substrate slice with rare HF, be hydrophobicity until the substrate burnishing surface.Underlayer temperature is 500 ℃, feeds disilane and Germane gas and carries out film growth; (referring to Fig. 4 (A))
4. be 5 * 10 at germanium-silicon thin membrane and silicon substrate interface implantation dosage
16Cm
-2Hydrogen ion and dosage be 1 * 10
15Cm
-2The boron ion, form bubble layer; (referring to Fig. 4 (B) and Fig. 4 (C))
5. NMOS substrate and the injection sheet that is coated with silicon oxide layer carried out plasma treatment, after in RCA1 that adjusts and RCA2, cleaning then, bonding in the bonding machine; (referring to Fig. 2 (C); Ammoniacal liquor among the RCA1: hydrogen peroxide: deionized water=1: 3: 10, hydrochloric acid among the RCA2: hydrogen peroxide: deionized water=1: 1: 5;
6. bonding pad was annealed 5 minutes down at 300-400 ℃, bonding pad is peeled off at notes hydrogen layer place.In order to improve bond strength, annealed 4 hours down at 400 ℃;
7. stripper surface is thrown flat with CMP; (referring to Fig. 2 (E))
8. on second layer germanium-silicon thin membrane, prepare PMOS; (referring to Fig. 2 (F))
9. etch the fairlead between the two MOS drain electrode, insert tungsten after, the tungsten on surface is removed; (referring to Fig. 2 (G))
10. photoetching aluminum lead hole, deposit aluminium;
11. anti-carve aluminium, alloying.
Embodiment 3:
The three-dimensional planar CMOS technology of preparation copper connecting lines.(referring to figure (6))
1. prepare nMOS on p type SOI substrate, concrete steps are identical with SOI NMOS;
2. capping oxidation silicon layer on NMOS carries out planarization with the method for chemico-mechanical polishing, and surperficial r.m.s. roughness is less than 1nm.
3. implantation dosage is 5 * 10 on N type body silicon substrate
16Cm
-2Hydrogen ion and dosage be 1 * 10
15Cm
-2The boron ion.
4. NMOS substrate and the injection sheet that is coated with silicon oxide layer carried out plasma treatment, after in RCA1 that adjusts and RCA2, cleaning then, bonding in the bonding machine.
5. bonding pad was annealed 5 minutes down at 300-400 ℃, bonding pad is peeled off at notes hydrogen layer place.In order to improve bond strength, annealed 4 hours down at 400 ℃.
6. stripper surface is thrown flat with CMP.
7. on second layer monocrystalline silicon, prepare PMOS;
8. the W line for preparing NMOS and PMOS;
9. adopt PECVD or LPCVD to cover siof layer on PMOS, carry out planarization with the method for chemico-mechanical polishing, surperficial r.m.s. roughness is less than 1nm.
10. carve fairlead, insert W, the W with the surface removes with CMP again.
11. preparation Cu electrode covers fluorinated silicon oxide low k dielectric material again on the W lead-in wire, throws flat;
12. on the low k dielectric material, prepare the Cu electrode, and link to each other with following Cu electrode;
13. cover the fluorinated silicon oxide low k dielectric, throw flat;
14. implantation dosage is 5 * 10 on silicon chip
16Cm
-2Hydrogen ion and dosage be 1 * 10
15Cm
-2The boron ion;
15. CMOS substrate and the injection sheet that is coated with siof layer carried out plasma treatment, after in RCA1 that adjusts and RCA2, cleaning then, bonding in the bonding machine;
16. bonding pad was annealed 5 minutes down at 300-400 ℃, bonding pad is peeled off at notes hydrogen layer place.In order to improve bond strength, annealed 4 hours down at 400 ℃;
17. stripper surface is thrown flat with CMP;
18. on the 3rd layer of monocrystalline silicon, prepare NMOS;
19. 1-8 is identical with step, the CMOS of the preparation second layer;
20. etch the fairlead between the two CMOS drain electrode, insert tungsten after, the tungsten on surface is removed;
21. the polymer of the extremely low k value of deposition adopts Damascus technics to prepare copper connecting lines.
Embodiment 4:
Preparation contains the three-dimensional planar cmos device of heat dissipating layer.(referring to figure (7))
1. after having prepared n layer MOS with embodiment 1, insulating layer of silicon oxide in the covering, with chemical Mechanical Polishing Technique throw flat after, with the method deposit spathic silicon of chemical vapour deposition (CVD), depositing temperature is 600 ℃.
2. etch fairlead.
3. after adopting of the lead-in wire aperture oxidation of quick heat treatment method, insert tungsten and polishing at the fairlead place with the polysilicon place.
4. on polysilicon, deposit the skim insulating layer of silicon oxide.
5. prepare n+1 layer MOS with embodiment 1, and line.
Embodiment 5:
Contain the preparation of the semiconductor chip of porous silicon defective buried regions.
1. adopt P type＜100〉silicon chip, resistivity is 0.01-0.02 Ω cm.Electrolyte is 1: 1 HF/ alcoholic solution, and silicon chip connects anode, and Pt is a negative electrode, is 3 ~ 7mA/cm in current density
2Under reacted 5 minutes, form porosity and be about 28%, thickness is about 10 microns porous silicon layer.(referring to Fig. 5 (A) and 5 (B))
2. adopt method epitaxial monocrystalline silicon on the porous silicon substrate of ultra vacuum electron beam evaporation deposition.For the elevated temperature strength that improves porous silicon with stop the B diffusion, before the extension with porous silicon pre-oxidation 1 hour under 350 ℃ of oxygen atmospheres, with HF oxide on surface is removed then.Outer time-delay underlayer temperature is 850 ℃.So just formed the semiconductor chip that contains the porous silicon defect layer.(referring to Fig. 5 (c))
Claims (10)
1. three-dimensional multilayer planar complementary metal oxide semiconductor device structure, it is characterized in that N channel metal oxide semiconductor transistor and P-channel metal-oxide-semiconductor transistor are the floor-type structure, transistor on the same floor is same type a metal oxide semiconductor transistor, is connected by the interlayer metal line between N channel metal oxide semiconductor transistor and the P-channel metal-oxide-semiconductor transistor.
2. by the described three-dimensional multilayer planar complementary metal oxide semiconductor device structure of claim 1, the number of plies that it is characterized in that the floor-type structure is 2n, and n 〉=1.
3. by the described three-dimensional multilayer planar complementary metal oxide semiconductor device structure of claim 1, it is characterized in that the preparation of the first floor metal oxide semiconductor device on silicon, germanium silicon or strained silicon on body silicon, the insulating barrier, the above preparation of second floor or second floor strained silicon on germanium silicon or insulating barrier on silicon, the insulating barrier on the insulating barrier.
4. by the described three-dimensional multilayer planar complementary metal oxide semiconductor device structure of claim 1, it is characterized in that N-channel metal-oxide-semiconductor prepares on different thin film substrate material with the P-channel metal-oxide-semiconductor device; The N-channel metal-oxide-semiconductor preparation is on the strained silicon film substrate, and the preparation of P-channel metal-oxide-semiconductor device is on germanium-silicon thin membrane.
5. by the described three-dimensional multilayer planar complementary metal oxide semiconductor device structure of claim 1, it is characterized in that insulator between N-channel metal-oxide-semiconductor and the P-channel metal-oxide-semiconductor device be in silicon dioxide, silicon nitride, aluminium nitride, aluminium oxide or the diamond like carbon any one; Introduce one deck polysilicon layer in each floor insulating barrier and make heat dissipating layer, around line, form a film oxidation layer in order to isolate.
6. by the described three-dimensional multilayer planar complementary metal oxide semiconductor device structure of claim 1, it is characterized in that the line between each layer complementary mos device is tungsten or copper, isolate by medium with low dielectric constant for copper connecting lines, the dielectric constant of the medium of uppermost multilayer interconnection is less than 2, and the dielectric constant of inner each CMOS (Complementary Metal Oxide Semiconductor) device is between 3～2.
7. the method for preparing three-dimensional multilayer planar complementary metal oxide semiconductor device structure as claimed in claim 1 is characterized in that concrete preparation process is:
(a) on body silicon, silicon-on-insulator, germanium silicon or any one substrate of strained silicon, prepare N-channel metal-oxide-semiconductor;
(b) after the ground floor metal oxide semiconductor device structure forms, dielectric in the covering, with cmp method surface of insulating layer is thrown flat, then with the single crystal semiconductor substrate of this substrate and another potting defectiveness layer bonding at room temperature; Peel off behind the bonding, transfer to through single-crystal semiconductor layer on the insulating substrate that contains device;
(c) with cmp method that the surface throwing is flat, remove surface impurity, then preparation P-channel metal-oxide-semiconductor device on the second layer;
(d) etch fairlead, preparation N-channel metal-oxide-semiconductor and P-channel metal-oxide-semiconductor device interlayer connecting line;
(e) after second layer metal oxide semiconductor element structure forms, dielectric in the covering etches the fairlead between the complementary mos device device, and fills out metal lead wire in the hole; With cmp method surface of insulating layer is thrown flat, then with the single crystal semiconductor substrate of this substrate and another potting defectiveness layer bonding at room temperature; Peel off behind the bonding, transfer to through single-crystal semiconductor layer on the insulating substrate that contains device;
(f) with cmp method that the surface throwing is flat, remove surface impurity, on the 3rd layer, prepare N-channel metal-oxide-semiconductor then;
(g) after three-layer metal oxide semiconductor element structure forms, dielectric in the covering, with cmp method surface of insulating layer is thrown flat, then with the single crystal semiconductor substrate of this substrate and another potting defectiveness layer bonding at room temperature; Peel off behind the bonding, transfer to through single-crystal semiconductor layer on the insulating substrate that contains device;
(h) with cmp method that the surface throwing is flat, remove surface impurity, then preparation P-channel metal-oxide-semiconductor device on the 4th layer;
(i) etch fairlead, prepare the 3rd layer of N-channel metal-oxide-semiconductor and the 4th layer of P-channel metal-oxide-semiconductor device interlayer connecting line;
(j) repeat (a)-(i) step, prepare the overlaid cmos device;
(k) last multilayer interconnection.
8. according to the described three-dimensional complementary metal oxide semiconductor preparation of devices of claim 7 method, it is characterized in that defect layer is to annotate hydrogen layer, boron hydrogen to annotate layer, hydrogen helium altogether and annotate a kind of in layer or the porous silicon altogether, wherein:
(a) hydrogen ion dosage is 1～9 * 10
16Cm
-2
(b) the helium ion dose is 1～9 * 10
16Cm
-2
(c) dosage of boron ion is 5 * 10
15Cm
-2～5 * 10
16Cm
-2
(d) the porous silicon buried regions is to adopt epitaxial silicon on the porous silicon substrate of electrochemical production, and with this epitaxial wafer and the insulating barrier substrate bonding that contains device.
9. by the described complementary mos device preparation method of claim 8, it is characterized in that a kind of in heating or the machinery of method that defect layer peels off.
10. by the described complementary mos device preparation method of claim 8, it is characterized in that the preparation of porous silicon buried regions is:
1. adopt P type＜100〉silicon chip, resistivity is 0.01-0.02 Ω cm, and electrolyte is 1: 1 HF/ alcoholic solution, and silicon chip connects anode, and Pt is a negative electrode, is 3～7mA/cm in current density
2Under reacted 5 minutes, form porosity and be about 28%, thickness is about 10 microns porous silicon layer;
2. adopt method epitaxial monocrystalline silicon on the porous silicon substrate of ultra vacuum electron beam evaporation deposition; Before the extension with porous silicon pre-oxidation 1 hour under 350 ℃ of oxygen atmospheres, with HF oxide on surface is removed then.Outer time-delay underlayer temperature is 850 ℃.
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