CN1610069A - Process for polishing a semiconductor wafer - Google Patents

Abstract

A process is for the simultaneous polishing of the front surface and the back surface of a semiconductor wafer between two rotating polishing plates covered with polishing cloth while a polishing fluid is supplied, the polishing cloth of the lower polishing plate having a smooth surface and the polishing cloth of the upper polishing plate having a surface which is interrupted by channels. The semiconductor wafer lying in a cutout in a carrier plate is held on a defined geometric path. The front surface of the semiconductor wafer, during polishing, is in contact with the polishing cloth of the lower polishing plate. The back surface of the semiconductor wafer, during polishing, is in contact with the polishing cloth of the upper polishing plate.

Description

Method for polishing semiconductor wafer

technical field

The invention relates to a method for polishing a semiconductor wafer, which can obtain an improved nanophase of the polished semiconductor wafer. Such semiconductor wafers are suitable for the semiconductor industry, especially for the production of electronic components.

Background technique

A semiconductor wafer intended to be suitable for making electronic components having a line width of 0.1 micron or less must have a number of specific properties. One of the most important properties is known as the nanophase of semiconductor wafers.

"Semiconductor Equipment and Materials International" (SEMI) defines the term "nanotopology" or "nanotopography" as: the flatness deviation of the entire wafer front (front surface) at a spatial wavelength of 0.2 to 20 mm (side-relative length) and within the "Fitness Area" (FQA: Fixed Fitment Area; the area of the surface that must fulfill the properties required by the product specification). The nanophase is measured by a complete scan of the entire wafer surface and with the overlapping of different sized measurement fields. Surface height variation (peak to valley) was not found to exceed the maximum required across the wafer within these measurement fields. The size of the measurement field depends on the specification, for example, it can be defined as 2×2 square millimeters, 5×5 square millimeters and 10×10 square millimeters.

The final nanophase of the semiconductor wafer is formed by the polishing process. In order to improve the flatness of semiconductor wafers, devices and methods for simultaneously polishing the front and back sides of semiconductor wafers are increasingly advanced and continuously developed.

For example, so-called double-sided polishing has been described in US Pat. No. 3,691,694. According to a specific embodiment of double-sided polishing described in European patent EP 208315 B1, in the presence of a polishing liquid, a carrier disc with a cutting frame (or grooving) of suitable dimensions and made of metal or plastic The semiconductor wafer inside is polished by moving between two rotating polishing discs covered with polishing cloths along a path predetermined by the machine and processing parameters (in expert literature, the carrier disc is also called a template).

For example, German patent DE 10004578 C1 describes the use of a polishing cloth made of homogeneous, porous polymer foam with a hardness of 60 to 90 (Shore A) to perform a double-sided polishing step. This document also discloses that the polishing cloth adhered to the upper polishing disc has a network of grooves and the polishing cloth adhered to the lower polishing disc has a smooth surface without any such texture or structure. The purpose of this measure is, one, to ensure the uniform distribution of the polishing abrasive used in the polishing process; second, to prevent the semiconductor wafer from adhering to the upper polishing cloth when the upper polishing disc is lifted after the polishing work is completed.

To perform double-sided polishing, the semiconductor wafer is placed into a cutting frame within the carrier plate in such a way that the back (or opposite) side of the semiconductor wafer rests on the lower polishing plate. Thus, during polishing, the backside of the semiconductor wafer is polished with a non-textured polishing cloth adhered to the lower polishing plate, and the front side of the semiconductor wafer is polished with a textured polishing cloth adhered to the upper polishing plate. The front side of the semiconductor is the surface on which the electronic components are intended to be fabricated. After the polishing step, the semiconductor wafer is usually transferred into a water bath, for example by means of a vacuum suction device.

This method of the prior art cannot meet the increasing demands on the nanophase of semiconductor wafers that have undergone double-sided polishing for use in new components of future generations. Therefore, the object of the present invention is to provide a method that can produce a semiconductor wafer with an improved nano-phase, so as to meet the requirements of making special demand components.

Contents of the invention

The present invention proposes a method for simultaneously polishing the front and back surfaces of a semiconductor wafer between two rotating polishing discs covered with a polishing cloth under the condition of supplying a polishing fluid, the polishing cloth of the lower polishing disc has a smooth surface, and the upper polishing disc The surface of the polishing cloth of the optical disc is separated by grooves, the semiconductor wafer is located in the cutting frame of a carrier disc and is kept on a defined geometric path, wherein, during the polishing process, the front side of the semiconductor wafer and the polishing of the lower polishing disc The backside of the semiconductor wafer is in contact with the polishing cloth on the upper polishing pad during the polishing process.

The processed starting products are semiconductor wafers separated by known methods from a crystal, for example from a silicon single crystal, cut to length and rounded by grinding, the front and/or rear sides of which have been Processed at the grinding or lapping step. The edges of the semiconductor wafers may also be rounded at some point in the processing sequence by means of an appropriately contoured grinding wheel. Furthermore, following the grinding step, the surface of the semiconductor wafer may also be etched.

According to the invention, in preparation for double-sided polishing, the semiconductor wafer is placed in the cutout of a carrier plate in such a way that its front side rests on the polishing cloth of the lower polishing plate. Thus, during double-sided polishing, the front side of the semiconductor wafer is in contact with the smooth polishing cloth of the lower polishing plate, while the back side of the semiconductor wafer is in contact with the textured polishing cloth of the upper polishing plate. Otherwise, double-sided polishing is carried out in a manner known to those skilled in the art.

The final product obtained by the method is a semiconductor wafer that has been polished on both sides and has a greatly improved nanophase.

In principle, the method according to the invention can be used to produce wafer-shaped objects consisting of materials which can be processed using chemical-mechanical double-sided polishing methods. Such materials are, for example, further processed for use primarily in the semiconductor industry, but are not limited to this particular application, and include, for example: silicon, silicon-germanium, silicon dioxide, silicon nitride, gallium arsenide and other III-V semiconductors. Among them, silicon in the form of a single crystal crystallized by, for example, Zokolasski crystal pulling or floating zone crystal pulling is preferable. Especially silicon with (100), (110) or (111) crystal orientation is more preferred.

The method is especially suitable for producing silicon wafers with a diameter of 200 mm, 300 mm, 400 mm, 450 mm and a thickness ranging from hundreds of microns to several centimeters (especially 400 microns to 1200 microns). The semiconductor wafer can be used directly as a starting material for the production of semiconductor elements, or after a final polishing step according to the prior art and/or coated with several layers (such as a backside sealing layer or a frontside epitaxy formed with silicon or other suitable semiconductor materials) coating) and/or after treatment by means of heat treatment, it can be used for the intended use.

Detailed ways

The method of the present invention will be further described by taking the manufacture of silicon wafers as an example.

In principle, silicon wafers which have been cut with a circular saw or a wire saw and which, depending on the diameter and the type of sawing method, have regions that damage the crystal lattice to a depth of 10 to 40 μm can be directly subjected to the double-sided polishing step according to the invention . However, the sharply defined (with sharp interface) and therefore mechanically highly sensitive wafer edges are preferably rounded off by means of a suitable contoured or profiled grinding wheel before double-sided polishing is carried out. In addition, to improve the geometry and partially remove the damaged crystal layer, the silicon wafer may be subjected to a mechanical grinding step (such as lapping or lapping) to reduce the amount of material removed in the polishing step of the present invention. This can be followed by an etching step in order to remove the crystalline regions of the wafer surface and edges that were inevitably damaged during the machining step and to remove any impurities that may be present, such as metallic impurities adhering to the damaged parts. The etching step can be implemented by wet chemical or plasma treatment of the silicon wafer in an alkaline or acidic etch mixture.

For example, IBM's technical report TR 22.2342 describes a commercially available double-sided polishing machine of suitable size that can be used to carry out the polishing step of the present invention. The polishing machine mainly includes: a lower polishing disc that can rotate freely in a horizontal plane and an upper polishing disc that can rotate freely in a horizontal plane. ) is subjected to material removal polishing on both sides, while a polishing fluid of appropriate chemical composition is continuously supplied.

It is possible to polish only one silicon wafer. However, usually, in order to save cost, it is better to polish a plurality of silicon wafers at the same time, and the actual number depends on the structure of the polishing machine. The silicon wafers are maintained on a geometric path determined by the processing parameters of the polishing machine and the carrier plate with a cutting frame sufficient to hold the silicon wafers during polishing. For example, the carrier disc is brought into contact with the polishing machine by means of pin or involute gearing (via a rotating inner pin or ring and a generally opposing rotating outer pin or ring), so that the carrier disc can be Rotary motion between two polishing discs.

Examples of parameters that affect the path of the silicon wafer with respect to the upper and lower polishing plates during a polishing operation include the size of the polishing plates, the design of the carrier plate, and the rotational speeds of the upper, lower, and carrier plates. If there is always a silicon wafer in the center of the carrier plate, the silicon wafer moves in a circle around the center of the polisher. If many silicon wafers are arranged eccentrically in a carrier plate, the rotation of the carrier plate around its own axis forms a hypocycloidal path. The polishing process of the present invention is preferably a hypocycloidal path. It is especially better to use four to six carrier trays (each carrier tray carries at least three silicon wafers arranged in a circular path at regular intervals) at the same time.

In principle, the carrier plate used in the method according to the invention can be made of any material which has sufficient mechanical stability against the mechanical loads caused by the drive, especially compressive and tensile loads. Furthermore, the material must be free from significant chemical and mechanical attack from the polishing fluids and polishing cloths used in order to ensure adequate service life of the carrier plate and to prevent contamination of the silicon wafers after polishing. In addition, the material must be suitable for producing a highly flat, stress-free, and waviness-free carrier tray of the desired thickness and geometry. In principle, the carrier trays can be made, for example, of metal, plastic, fiber-reinforced plastic or plastic-coated metal. Preferably, the carrier pan is made of steel or fibre-reinforced plastic. More preferably, the carrier pan is made of stainless steel.

The carrier tray has one or more cutout frames, preferably circular, to hold or accommodate one or more silicon wafers. To ensure that the silicon wafers can move freely within the rotating carrier plate, the cutting frame must have a slightly larger diameter than the silicon wafers to be polished. It is better to have a slightly larger diameter of 0.1 to 2 mm, especially more preferably a slightly larger diameter of 0.3 to 1.3 mm. In order to prevent the edge of the wafer from being damaged by the inner edge of the cutting frame in the carrier tray during the polishing process, as suggested in European patent EP 208315 B1, it is better to add a plastic liner with the same thickness as the carrier tray on the inner side of the cutting frame .

As described in German Patent DE 19905737 A1, the thickness of the carrier plate used in the polishing method of the present invention is preferably 400 to 1200 microns, especially depending on the final thickness of the polished silicon wafer. The amount of silicon removed in the polishing step is preferably 5-100 microns, more preferably 10-60 microns, especially 20-50 microns.

In the context of the description for the face-down orientation of the semiconductor wafer, the double-sided polishing step is preferably carried out in a manner known to those skilled in the art. Polishing cloths are commercially available with a wide range of properties. The polishing action is best performed using a commercially available polyurethane ((ie, polyurethane)) polishing cloth with a hardness of 40 to 120 (Shore A). Especially the polyurethane polishing cloth mixed with polyethylene fiber and with a hardness of 60 to 90 (Shore A) is better. In the case of polishing silicon wafers, it is recommended to continuously supply a polishing fluid with a pH of 9 to 12 (especially 10 to 11) containing 1 to 10% by weight (especially 1% by weight) in water. to 5% SiO ₂ , the polishing pressure is preferably 0.05 to 0.5 bar, especially 0.1 to 0.3 bar. The silicon removal rate is preferably 0.1 to 1.5 μm/min, more preferably 0.4 to 0.9 μm/min.

When the polished semiconductor wafer is removed from the lower polishing plate, the semiconductor wafer is preferably placed on a standard processing support for further processing and proper orientation of the surface for subsequent processing steps. Compared to conventional double-sided polishing, in which the semiconductor wafer is polished right side up, the need to rotate the semiconductor wafer by 180° can be avoided if the holder holding the semiconductor wafer is configured to rotate by 180°. The same good effect can be obtained by manual unloading or automatic unloading by robot. Work of the above nature is also conceivable when mounting a semiconductor wafer on the lower polishing plate.

The polished semiconductor wafer can be removed from the lower polishing plate manually or by means of an automatic moving device; in both cases, vacuum suction is preferably used. German Patent DE19958077 A1 (page 6, lines 23 to 30) once described a suitable vacuum suction device. Immediately after removal from the polishing pad, the semiconductor wafer is preferably placed into a liquid bath (especially a water bath). In this way, drying of the polishing abrasive and the formation of marks in the vacuum suction device or, more generally, the moving device are effectively prevented.

After the polishing process is completed, any attached polishing fluid is washed off the silicon wafer and the wafer is dried.

Depending on their further use, the front sides of these wafers may require final polishing according to known techniques, for example with a soft polishing cloth and with the aid of a _SiO2- based alkaline polishing fluid.

example:

The following experimental examples and comparative examples used a commercially available AC 2000P ² -type double-sided polishing machine (manufactured by Peter Walters, Rendsburg, Germany). The polisher is equipped with five stainless chrome steel carrier discs with a lapped surface and a thickness of 720 microns, each carrier disc has six circular cutting frames with an inner diameter of 200.5 mm, which are cut in regular Or arranged at equal intervals on a circular path and lined with polyvinylidene fluoride layer, the polishing machine can simultaneously polish 30 silicon wafers with a diameter of 200 mm per batch. The upper and lower polishing discs were covered with a commercially available polyurethane polishing cloth manufactured by Rodel Corporation under the trade designation SUBA500, 74 (Shore A) hardness, reinforced with polyethylene fibers. The polishing cloth stretched over the lower polishing disc has a smooth surface, and the surface of the polishing cloth stretched over the upper polishing disc has a milled partly circular groove with a width of 1.5 mm and a depth of 0.5 mm. Forming a checkerboard pattern, these grooves are arranged at a pitch of 30 mm.

comparative example

In each case, 30 silicon wafers with an etched surface and a diameter of 200 mm were manually placed face-up into the cutting frame of the carrier tray. During the polishing process, a water-based polishing abrasive (Levasil 200 type, Bayer AG, Leifkusen, Germany) with a fixed SiO _solid content of 3.1% by weight was continuously supplied, and the pH value was adjusted by adding carbonic acid Potassium and potassium hydroxide are set to 11.4. The polishing process was carried out at a pressure of 0.2 bar and at a constant temperature of 38° C. on the upper and lower polishing discs, with a material removal rate of 0.58 μm/min. 15 microns of silicon were removed from each surface of the wafer. After the thickness of the polished wafer had reached 725 micrometers, the supply of the polishing abrasive was stopped and replaced by a stopping agent for 2 minutes. The stop agent used was Glanzox 3600 produced by Japan Fujimi Co., Ltd. with a weight percentage of 1% aqueous solution. After the stop step is terminated, the device is switched on and the silicon wafers in the carrier tray are completely wetted with the stop liquid. The silicon wafers were transferred to racks located in the water bath using a commercially available unloading station manufactured by Peter Walters. These silicon wafers are then dried in a batch cleaning apparatus with a bath sequence of: tetramethylammonium hydroxide (TMAH)/H ₂ O ₂ ; HF/HCl:ozone; HCl and a commercially available commercially available drying unit and operates according to the Marangoni principle. The nanophase of the cleaned wafers was measured on an ADE SQM CR83 device using a measurement field of 2 mm x 2 mm (HCT 2 x 2) and 10 mm x 10 mm (HCT 10 x 10). A total of 1968 silicon wafers were polished and their nanophase phases were subsequently determined.

Experimental example

A total of 2157 silicon wafers having an etched surface and a diameter of 200 mm were processed in a manner similar to that of the comparative example. The only difference from the comparative example is that the silicon wafer placed in the cutting frame of the carrier disk faces down, and then polished along this orientation. The results of the statistical analysis of the obtained nanophase values are shown in the table below. Comparative example: 1968 silicon wafers Experimental example: 2157 silicon wafers measuring field HCT 2×2 HCT 10×10 HCT 2×2 HCT 10×10 average 18.50 40.48 15.24 33.06 standard deviation 4.87 9.65 2.06 5.66

From the above results, it can be seen that if the silicon wafers were polished face down, the nanophase of the silicon wafers could be greatly improved for both sizes of the measurement field.

Claims (3)

1. One kind for have under the situation of polishing fluids in two coated with the rotary finishing dish of polishing cloth between the method at polishing of semiconductor wafers front and the back side simultaneously, the polishing cloth of following polishing disk has a smooth surface, the surface of the polishing cloth of last polishing disk by groove in addition at interval, semiconductor wafer is positioned at the cutting frame of a carrier disk and remains on the geometric path of determining, wherein, in polishing process, the front of semiconductor wafer contacts with the polishing cloth of following polishing disk, and in polishing process, the back side of semiconductor wafer contacts with the polishing cloth of last polishing disk.
2. 2. the method for claim 1 is characterized in that, after polish simultaneously at front and the back side, by means of a vacuum suction apparatus this semiconductor wafers is transferred in the water-bath.
3. 3. method as claimed in claim 1 or 2 is characterized in that, after polish simultaneously at front and the back side, the front of this semiconductor wafer is imposed final polishing.