CN1602370A - Plasma chamber insert ring - Google Patents

Abstract

Methods and apparatuses for reducing electrical arcing currents or electron emissions to a wafer or to components in a plasma chamber are provided. An insert (234) for use in a process chamber having a wafer support is disclosed. The insert comprises a composite member formed of a first material, such as for example, silicon, and a second material (232), such as for example, SiO2, having a greater electrical impedance than the first material. The composite member has a surface (214) which is adapted to be disposed adjacent to the wafer support (215), and which is made of the second material. In one aspect, the process chamber further has an outer member (225) adapted to surround the wafer support. The composite member has a surface (216) which is adapted to be disposed adjacent to the outer member and which is made of the second material. In another aspect, the composite member has a surface (230) which is adapted to be disposed adjacent to a semiconductor wafer (110) and which is made of the second material.

Description

Plasma chamber insert ring

related application

This application claims priority to US Provisional Patent Application No. 60/340,759, filed December 11, 2001, Applicant's Docket No. 4996/ETCH/DICP-PROV.

technical field

The present invention relates to plasma chambers for semiconductor wafer processing systems, and more particularly to improved apparatus and methods for reducing arcing or electron emission in plasma chambers.

Background technique

Plasma chambers for semiconductor wafer processing systems commonly include wafer supports for supporting semiconductor wafers within these chambers. Certain wafer supports are pedestals, usually made of aluminum or stainless steel, with a top flat surface on which a wafer can rest. Other wafer holders include both a base and an electrostatic chuck that is usually used to hold the wafer. An electrostatic chuck (ESC) is generally supported on a base and includes a dielectric layer with embedded electrodes. To create a clamping force between the wafer and the support surface of the chuck, the electrodes are connected to a power source, usually a high voltage DC power source. Wafer holder assemblies are typically placed in the center of processing chambers used to perform chemical vapor deposition (CVD), physical vapor deposition (PVD) or etch processes.

To facilitate efficient application of these processes, the plasma is often formed in the processing chamber near the surface of the processed wafer. To generate such a plasma, a process gas is typically introduced into the process chamber and energy is coupled to the process gas to form the plasma. This energy is typically provided by an antenna or electrode coupled to a radio frequency (RF) power source. For example, in a capacitively coupled two-electrode plasma chamber, RF power can be applied between the grounded chamber wall and the pedestal supporting the ESC.

In one operation, a wafer is placed on the support surface of the ESC, a process gas is introduced into the process chamber, a plasma is generated by coupling plasma generation energy to the process gas, and finally a chucking voltage is applied to the ESC electrodes. Typically, a clamping voltage is applied between the electrode and the grounded chamber wall. Thus, the conducting plasma causes the wafer to have a small voltage drop with respect to the chamber walls across the dark spaces formed between the wafer and the plasma and the plasma and the chamber walls. As a result, charges accumulate on the supporting surface of the dielectric layer and on the wafer surface opposite the supporting surface. The charges on each surface are of opposite polarity. As a result, Coulomb forces attract the charges and keep the wafer on the ESC's supporting surface.

ESCs may include a flex circuit that includes a thin conductive layer, such as copper, sandwiched between upper and lower dielectric layers. The dielectric layer is typically formed of polyimide or some other flexible dielectric material. In some embodiments, the thickness of the flex circuit is between 6-9 mils (0.15-0.23 mm). Laminant-type ESCs are disclosed in more detail in US Patent No. 5,822,171 to Shamouilian et al., assigned to the same assignee as the present invention.

The flexible circuit is often adhered to the top surface of the submount with an adhesive such as phenolic-butyral. The base is usually aluminum but can also be made of other materials such as stainless steel. In some embodiments, the diameter of the flexible circuit is 4-10 mm smaller than the diameter of the handle wafer, such that the wafer completely covers the surface of the ESC. In this way, the wafer protects the ESC from exposure to the plasma.

Other conventional components of the processing chamber that function with the wafer holder may include insulation rings and focus or top rings. In some cases, the insulating ring and top ring are manufactured as a single piece. An insulating ring, usually in the form of a ring, rests on the base and surrounds the ESC. The top ring, also usually annular, rests on the insulating ring and surrounds the ESC and wafer.

In some embodiments, the portion of the wafer that protrudes beyond the edge of the ESC is generally spaced from the focus ring and isolation ring to facilitate proper seating of the wafer on the ESC. However, due to the gaps formed between these components, undesired ESC or susceptor to wafer edge current arcing may occur. Such arcing can cause pitting damage to the edge of the wafer, reducing wafer yield.

Before describing the present invention, the overall operation of an example of a conventional magnetically enhanced plasma chamber will be explained. However, the invention can be used in a variety of plasma chambers. Figure 1 shows a magnetically enhanced, two-electrode, capacitively coupled plasma chamber 100 suitable for etching or chemical vapor deposition (CVD). Plasma can also be generated using inductively coupled coils, electron guns, microwave generators, and other plasma sources.

The vacuum chamber 100 is sealed by a cylindrical side wall 102 , a circular bottom wall 104 and a circular top wall or lid 106 . Cover 106 and bottom wall 104 may be dielectric or metal. An electrically grounded anode electrode 108 is mounted on the bottom of lid 106 . The anode electrode 108 may be perforated as a gas inlet for the process gas into the chamber. Sidewalls 102 may be dielectric or metal. If it is metal, it is preferably a non-magnetic material, such as anodized aluminum, so that it will not interfere with the magnetic field generated by the outdoor electromagnetic coil. If the sidewall is metal, it can be part of the anode.

A semiconductor wafer or workpiece 110 is mounted on a cathode electrode 112 or susceptor, which is located at the lower end of the chamber. A vacuum pump (not shown) evacuates the chamber through exhaust manifold 114 and maintains the total chamber pressure at a level low enough to facilitate plasma generation, typically in the range of 10 mTorr to 20 Torr, the lower end of the pressure range and upper limit are typical pressures for etch and CVD processes, respectively.

An RF power source 116 is connected to the cathode electrode 112 or pedestal through an RF via 117 and a series of coupling capacitors 118 . An RF power source 116 provides an RF voltage between the cathode electrode 112 and the grounded anode electrode 108 which excites the chamber gas into a plasma state. The plasma has a time-averaged positive direct current potential or voltage relative to the cathode or anode electrodes, which accelerates the bombardment of the ionized process gas components against the cathode and/or anode electrodes.

Magnetic enhancement of the plasma is often achieved by a DC magnetic field in the region between the cathode and anode electrodes. The magnetic field direction is transverse to the longitudinal axis of the chamber, ie to the axis extending between the cathode and anode electrodes. Permanent magnets or electromagnets of various configurations can be used to provide this transverse magnetic field. One such structure is the coil pair 120 shown in FIG. 1 , which are disposed on opposite sides of the cylindrical chamber side wall 102 . The two coils 120 are connected in series and in phase with a DC power supply (not shown), so that they generate a transverse magnetic field that is superimposed in the region between the two coils. These fields can be rotated mechanically or electronically, making uniformity easy. The field strength can also vary.

To maximize the speed of a plasma-enhanced semiconductor fabrication process performed within a plasma chamber, it is generally considered preferable to minimize any coupling of RF power to the plasma in the area of the susceptor or cathode electrode 112 rather than directly behind the wafer 110 (i.e., covered) regions where plasma coupling is minimal. In other words, it is generally believed that it is desirable to minimize the coupling of RF power to the sides of the cathode, or to the portion of the upper surface of the cathode around the wafer perimeter if the cathode diameter is larger than the wafer diameter. The ion flow of the plasma sheath is thus concentrated to the cathode surface area of the cathode electrode 112 occupied by the wafer 110 .

For example, FIG. 1 shows a cylindrical dielectric or insulating shield 122 surrounding the sides of the cylindrical cathode electrode 112 , and a dielectric or insulating ring 124 covering a portion of the surface of the cathode tip surrounding the wafer 110 . In chambers for processing silicon (Si) wafers, high purity quartz is typically used as the dielectric material because quartz does not typically release significant amounts of contaminants into the chamber. RF power coupling can be minimized by increasing the thickness of the dielectric and selecting a dielectric material with a low dielectric constant. In this design, the area of the plasma sheath facing the cathode is more aligned with the area of the wafer.

By replacing the insulating ring 124 (FIG. 1) with a modified insulating ring, the spatial uniformity of ion flow over the wafer 110 can be further improved. Referring to FIG. 2, an insulating ring 202 is shown adapted to enclose the ESC 206. The insulating ring 202 has a thinner annular portion 204 adjacent to the edge of the ESC 206 located directly outside the perimeter of the wafer 110. Annular portion 204 is generally thin enough that its electrical impedance is low enough at the frequency of RF power source 116 (FIG. 1 ), typically 13.56 MHz, to allow sufficient RF power from RF power source 116 to pass through annular portion 204. ( FIG. 2 ) is coupled to the plasma to cause the plasma sheath on the wafer surface to extend radially outward over the annular portion 204 .

The silicon insert ring 208 covers the thin portion 204 of the insulating ring 202 and is disposed adjacent to the vertical sidewall 217 of the insulating ring 202 . Insert ring 208 may be made of pure silicon, silicon or polysilicon. It should be noted that these materials are etchable like wafers. (Although made of silicon, it is believed that a very thin film of silicon dioxide (SiO ₂ ) with a thickness of less than 100 Angstroms will naturally form on the surface of the ring 208, which is caused by exposure to oxygen or the atmosphere. Oxidation.) Rings of this configuration tend to provide a more uniform plasma distribution at the edge of the wafer 110. In other words, inserting the ring 208 can increase the effective size of the wafer to the plasma.

Another purpose of the insert ring 208 is to protect the perimeter edge 226 of the ESC 206 from exposure to the plasma, which could cause etch damage to the ESC. Another purpose of the insert ring 208 is to protect the thin portion 204 of the insulating ring 202 from being corroded by the silicon dioxide etching process, since the quartz ring 202 is chemically similar to the silicon dioxide etched on the silicon wafer 110 . In some etching processes, silicon can be etched at least 10 times slower than quartz is etched. When the insert ring 208 begins to become significantly concave due to the etching process, the ring can then be easily replaced. Also, inverting the insert ring 208 after its top surface becomes concave can double its service life.

Insert ring 208 is often made of high purity material to minimize the release of contaminants into the chamber. As for the highest purity, one design uses single crystal silicon with a silicon purity of over 99%. Other designs requiring larger insert rings may use polysilicon material.

Still referring to FIG. 2 , the ESC 206 is mounted on a base or electrode 112. Base 112 is typically aluminum, but could be made of other materials such as stainless steel. Typically, the diameter of the peripheral edge 226 of the ESC 206 is 4 to 10 millimeters smaller than the diameter of the handle wafer 110 such that the wafer 110 completely covers the surface of the ESC 206 and extends beyond the overhanging edge 224. In this way, the wafer 110 protects the ESC 206 from exposure to the plasma.

Top ring 210 is mounted on insulating ring 202 and has a silicon top surface 218 for facing plasma region 220 and removing fluorine radicals from the plasma. The top ring 210 extends above the wafer 110 in height and has a slope away from the wafer 110 . This geometry enhances the electric field component orthogonal to the magnetic field in the region above the edge of the wafer 110 . This can increase the amount of plasma that can be generated at the peripheral portion of the wafer 110 , thereby allowing a more uniform etch rate or deposition rate over the entire surface of the wafer 110 .

The silicon top surface 218 has an inner peripheral edge 222 that is spaced from and surrounds the overhanging wafer edge 224 when the wafer 110 is placed on the ESC 206. The insert ring 208 is adapted to be positioned between the ESC peripheral edge 226 and the inner peripheral edge 222 of the top ring, at a location that sits on the thin portion 204 of the insulating ring 202 .

The overhanging edge 224 of the wafer 110 is generally spaced from the top surface of the insert ring 208 in a parallel, spaced relationship. In this way, a vertical gap 212 is formed between the overhanging edge 224 of the wafer 110 and the insert ring 208 . Gap 212 serves to ensure that the wafer is securely seated on ESC 206, but not on insert ring 208. Additionally, due to manufacturing tolerances, there may be horizontal gaps 214 and 216 separating the ESC perimeter edge 226 from the insert ring 208 and separating the insulating ring vertical sidewall 217 from the insert ring 208 , respectively.

The inventors have recognized that this prior design may create problems related to arcing or electron emission between the wafer 110 and the insert ring 208 . A current path may be established from ESC 206 to the edge of wafer 110 through insert ring 208 and through vertical gap 212 as indicated by vector j- in FIG. 2 . Such current may cause pitting damage to the edge portion of the wafer 110, thereby reducing wafer yield. Arcing or electron emission may occur across the gap 214 between the ESC 206 and the insert ring 208 and the gap 216 between the insulating ring 202 and the insert ring 208, as further shown by the vector j- in FIG. 2 . Because ESC 206 may be positively or negatively charged relative to adjacent components, electron flow may occur in either direction across gaps 212, 214, and 216. However, this flow of electrons may cause pitting damage to rings 202 and 208 . Moreover, such pitting may cause silicon particles to shatter, which may contaminate the wafer 110 .

Figure 3 shows another known design of the ESC and insert structure. Insert ring 208 rests on ledge 219 of ESC 215 . Thin portion 227 of insulating ring 225 has a horizontal upper surface 223 that is intentionally built below shoulder 219 of ESC 215. In this way, a vertical gap 221 is formed between the upper surface 223 and the insert ring 208 . Moreover, the inventors have recognized that arcing or electron emission as indicated by vector j- may pass through vertical gap 221, thus providing yet another source of pitting damage to rings 225 and 208, and yet another possible source of wafer contamination. source of silicon particles.

Contents of the invention

Inserts for use in process chambers with wafer holders are provided herein. Such an insert part comprises a composite part composed of a first material and a second material, wherein the second material has a greater electrical resistance than the first material. The composite member has a surface adapted to be disposed adjacent the wafer support, and in one embodiment, the surface is made of the second material and has a thickness in excess of 100 angstroms.

On the one hand, the processing chamber also has an outer part for enclosing the wafer holder. The other surface of the composite part is adapted to be positioned adjacent the outer part. In one embodiment, this surface is also made of the second material and has a thickness in excess of 100 Angstroms.

ESCs, on the other hand, are suitable for supporting wafers. The composite part has another surface adapted to be positioned adjacent the wafer. In one embodiment, this surface is also made of the second material and has a thickness in excess of 100 Angstroms.

On the other hand, in one embodiment, the second material is SiO ₂ and the first material is SiC, Al ₂ O ₃ , Y ₂ O ₃ , or Si having a purity of at least 99%.

In another embodiment, the outer member includes an insulating ring having vertical sidewalls and a horizontal upper surface. The composite part surface is adapted to be disposed adjacent the vertical side walls or/and the horizontal upper surface.

In another aspect, the wafer holder has a peripheral edge adapted to support a wafer having an overhanging wafer edge that protrudes beyond the peripheral edge of the wafer holder. The composite part surface is adapted to be positioned adjacent the edge of the overhanging wafer.

In another embodiment, the insertion member comprises a generally annular member made of the first material. The member has a generally planar top surface, a generally planar bottom surface, a generally cylindrical outer surface, and a generally cylindrical inner surface. This component is adapted to be placed within the chamber such that at least a portion of the interior surface abuts the peripheral edge of the wafer holder. The component also has a layer of a second material having a thickness greater than 100 Angstroms and an electrical impedance greater than that of the first material. This layer is disposed on one or more of the following surfaces: top surface, bottom surface, outer surface or inner surface.

There are other aspects of the invention. It is therefore to be understood that the foregoing is only a brief summary of some embodiments and aspects of the invention. Further embodiments and aspects of the invention are mentioned below. It should also be understood that many changes may be made to the disclosed embodiments without departing from the spirit or scope of the invention. The foregoing summary is therefore not intended to limit the scope of the invention.

Description of drawings

FIG. 1 is a cross-sectional view of a conventional plasma chamber.

Figure 2 is a cross-sectional view of a known construction of a portion of a plasma chamber apparatus including a wafer, ESC, insert ring and related components.

Figure 3 is an enlarged cross-sectional view of a wafer, ESC, insert ring and related components of a conventional plasma chamber of different designs.

4 is a cross-sectional view of a plasma chamber including an insert ring according to one embodiment of the invention.

5 is an enlarged cross-sectional view of an insert ring and selected other plasma chamber components in accordance with one embodiment of the present invention.

Figure 6a is an enlarged cross-sectional view of an insert ring and selected other plasma chamber components according to another embodiment of the present invention.

Figure 6b is a top view of the insert ring, wafer and outer part of Figure 6a.

7a-7c are enlarged cross-sectional views of insertion rings according to other embodiments of the present invention.

Detailed ways

In the following description, reference is made to the accompanying drawings which form a part hereof, and which illustrate several embodiments of the invention. It is to be understood that other embodiments may be utilized and structural and operational changes may be made without departing from the scope of the present invention.

Figures 4 and 5 illustrate an embodiment of the present invention that reduces or eliminates the aforementioned undesirable arcing or electron emission effects. There is disclosed a new insert ring 228 having a top flat surface 232, which in one embodiment is 6mm wide. A portion of the top surface 232 is adapted to face the portion of the overhanging edge 224 of the wafer 110 in an isolated relationship parallel to each other and separated by the gap 212 . Another portion of the top surface 232 is adapted to be exposed to the plasma region 220 . Insert ring 228 also has a cylindrical inner surface 238 adjacent peripheral edge 226 of ESC 206. The cylindrical outer surface 240 of the insert ring 228 defines a diameter that is smaller than the diameter defined by the vertical side walls 236 of the insulating ring 225 and allows the bottom flat surface 242 of the insert ring 228 to rest on the shoulder 219 of the ESC 215 .

Ring 228 includes a composite member formed from a first material and a second material, where the second material has a greater electrical impedance than the first material. In one embodiment, the body 234 of the ring 228 is made of silicon that is at least 99% pure. A SiO ₂ insulating film is used to form layer 230 on body 234 . In this embodiment, layer 230 has a thickness in excess of 100 angstroms, more preferably in excess of 1000 angstroms, and is preferably disposed on all surfaces, namely top surface 232, interior surface 238, exterior surface 240, and bottom surface 242 of insert ring 228. SiO ₂ is electrically insulating, so layer 230 reduces or eliminates the flow of electrical current or electrons through gaps 212 , 214 , and 216 . Providing layer 230 on bottom surface 242 also serves to reduce the flow of electrons across gap 221 .

Since a portion of the top surface 232 of the insert ring 228 is exposed to the plasma 220, the SiO ₂ layer 230 on this portion can be etched away, or removed relatively quickly. However, the remaining exposed portion of the insert ring 228 is made of silicon, so it is expected that this ring will have the same lifetime as known silicon rings since silicon is the major consumable material. Also, those portions of the _SiO2 layer adjacent to the wafer and ESC, or adjacent to the gaps 214, 216, 221, may not be directly exposed to the plasma, so it is expected that the lifetime of the remaining _SiO2 layer will be increased.

Figures 6a and 6b show another embodiment of the invention used in plasma chambers of different designs. The wafer holder 288 consists of an ESC 290 having a peripheral edge 292 and a base or electrode 294 on which the ESC rests. The electrode 294 has a flange portion 300 and a raised portion 302 on which the ESC 290 is disposed. Placed on the ESC 290 is a semiconductor wafer 296 having a wafer perimeter edge 297 that is larger in diameter than the ESC 290 such that the overhanging edge 298 of the wafer 296 protrudes beyond the ESC perimeter edge 292.

The raised portion 302 adjacent to the wafer 296, ESC 290, and electrode 294 is a generally annular insert ring 304 having a bottom surface 305 that rests on the flange portion 300 of the electrode 294. The insert ring has an outer upper vertical surface 316 and an outer lower vertical surface 320 joined by a horizontal shoulder 322 . Similarly, ring 304 has an inner upper vertical surface 306 and an inner lower vertical surface 308 joined by a horizontal shoulder 310 . Thus, upper inner surface 306 is spaced from wafer peripheral edge 297 ; insert ring shoulder 310 is spaced from overhanging wafer edge 298 ; and lower inner surface 308 is spaced from raised portion 302 of electrode 294 . Top surface 309 of ring 304 is coplanar with top surface 299 of wafer 296 .

As best seen in FIG. 6b , although the inner upper surface 306 of the insert ring 304 is generally cylindrical, it has an inner locating plane 312 that matches the locating plane 314 of the wafer edge 297 . Similarly, while the outer upper surface 316 of the insert ring 304 is generally cylindrical, it also has an outer locating plane 318 that is generally parallel to the inner locating plane 312 .

Referring again to FIG. 6 a , the outer member 324 encloses the insert ring 304 and has an upper inner vertical surface 326 and a lower inner vertical surface 328 joined by a horizontal shoulder 330 . These surfaces are positioned so that they mate with the upper outer surface 316 and the lower outer surface 320 of the insert ring 304 in parallel, spaced relationship.

Insert ring 304 includes a composite component formed from a first material and a second material, where the second material has a greater electrical impedance than the first material. The body 334 of the ring 304 is made of silicon that is at least 99% pure. A SiO ₂ insulating film is used to form layer 332 on body 334 . In the embodiment of FIG. 6a, _SiO2 layer 332 is disposed on all surfaces of insert ring 304, thereby preventing or inhibiting any or all contact between insert ring 304 and outer member 324, ESC 290, electrode 294, and wafer 296. electron flow between them.

While the embodiments of Figures 5 and 6a include layers on all surfaces of the rings 228, 304, it should be appreciated that other embodiments may have layers disposed on portions of the surfaces or only on a portion of the surface or surfaces. Also while the body 234, 334 is made of silicon, other materials may be used. For example, the body may be made of a material such as SiC, Al ₂ O ₃ or Y ₂ O ₃ .

Traditionally in the production of known silicon rings, a layer of _SiO2 will be grown on the outside of the ring. This layer is then removed from the ring by a wet etching process, which smoothes the surface and yields a ring made of relatively pure silicon. In this way, the preparation of the improved insert ring can be accomplished with relative ease. After the wet etch process, a thin film is grown by thermal oxidation, resulting in a _SiO2 layer thicker than the previously removed layer. However, those skilled in the art will recognize that the _SiO2 layer can be placed on the silicon ring by other methods. However, the films obtained by thermal oxidation are of good quality and relatively uniform in thickness. No major changes are necessary to the fabrication process for these improved insert rings; it is expected that adding an oxidation step to the process flow will suffice (and, in cases where coverage of all walls is not desired, surface oxide removal of the other walls of the ring A step of).

The insert ring of FIGS. 5 and 6 a is a composite part formed from a first material and a second material, wherein the material with the greater electrical resistance forms the thin film layers 230 and 332 . However, other embodiments need not include a thin film layer, and may include configurations that differ from the cross-section of the thin film layer. Figure 7a shows a composite component insert ring 244 consisting of a first part 246 made of a first material and a second part 248 made of a second material having a greater electrical impedance than the first material .

Insert ring 244 has a generally rectangular cross-section with a top surface 250 , a bottom surface 252 , an inner surface 254 and an outer surface 256 . The second portion 248 includes the entire inner surface 254 of the insertion ring 228 and a portion of the top surface 250 and a portion of the bottom surface 252, thereby having an inverted "L"-shaped cross-section. The cross-sectional shape of the first portion 246 is an "L" shape complementary thereto such that the first portion 246 and the second portion 248 combined have a generally rectangular cross-section. The width w1 of the second portion 248 at the location where a portion of the bottom surface 252 is formed is approximately 20% of the total width of the bottom surface 252, such that this width is much thicker than the film layer. Similarly, the width w2 of the second portion 248 at the location where a portion of the top surface 250 is formed comprises approximately 45% of the total width of the top surface 250 .

Figure 7b shows a composite component insert ring 258 consisting of a first part 260 made of a first material and a second part 262 made of a second material having a greater electrical impedance than the first material . Insert ring 258 has a generally rectangular cross-section with a top surface 264 , a bottom surface 266 , an inner surface 268 and an outer surface 270 . Both the first portion 260 and the second portion 262 are generally rectangular in cross-section, such that these portions combined generally have a rectangular cross-section. The second portion 262 includes the entire inner surface 268 of the insert ring 258 and a portion of the top surface 264 and a portion of the bottom surface 266 . The width w of the second portion 262 forming part of the top surface 264 and part of the bottom surface 266 is approximately 45% of the total width of these surfaces. As such, second portion 262 comprises a substantial portion of the overall volume of insertion ring 258 .

Figure 7c shows a composite component insertion ring 271 consisting of a first part 272 made of a first material and a second part 274 made of a second material having a greater electrical impedance than the first material . Insert ring 271 has a generally rectangular cross-section with a top surface 276 , a bottom surface 278 , an inner surface 280 and an outer surface 282 . The second portion 274 includes the entire inner surface 280 and the entire bottom surface 278 of the insert ring 271 and a portion of the top surface 276 and a portion of the outer surface 282 . The second portion 274 is rectangular in cross-section with one corner removed, thus forming a shoulder 284 . The first portion 272 is generally rectangular in cross-section and matches the shoulder 284 of the second portion 274 such that the first portion 272 and the second portion 274 are generally rectangular in cross-section when viewed together. Thus, the second portion 274 includes a larger portion of the overall volume of the insertion ring 270 relative to the first portion 272 .

The novel insert rings or components disclosed herein can be used in various types of chambers, including chambers with actuated bottom pedestals or electrodes, such as etch chambers, PVD chambers, and CVD chambers. However, these rings are especially useful in etch chambers where the RF bias to the wafer can be greatest, potentially causing more severe arcing and electron emission problems.

It should be noted that the configuration and geometry of the top ring, insulating ring and insert ring are provided here for illustration purposes only. The new and improved insert rings can be made in other suitable configurations and geometries, where the surfaces directly adjacent to the wafer, wafer holder, insulating ring, or all of these are preferably made of an insulating material, i.e., have a greater impedance than the remainder of the insert ring s material. For example, instead of such an integrated piece, another embodiment of the insert ring could include two pieces, one of which is adjacent to either the wafer or the peripheral edge of the ESC, or both, and made of a high impedance material. The other can be made of a more conductive material.

While the foregoing description refers to specific embodiments of the invention, it should be understood that many changes may be made without departing from its spirit. The claims are intended to cover such changes as fall within the true scope and spirit of the invention. Therefore, all aspects of the presently disclosed embodiments are to be considered as illustrative and not restrictive, with the scope of the invention being indicated by the claims rather than the foregoing description, and therefore within the meaning and equivalents of the claims. All changes in range are included.

Claims (76)

1. An insert for use in a processing chamber with a wafer holder, the insert comprising: A composite part consisting of a first material and a second material having an electrical impedance greater than said first material; the composite member has a first surface adapted to be disposed adjacent the wafer holder; and The first surface is made of the second material and has a thickness exceeding 100 Angstroms. 2. The insert assembly of claim 1, wherein the processing chamber further has an outer member adapted to enclose the wafer holder, and the composite member has a second outer member adapted to be disposed adjacent to the outer member. surface, said second surface is made of said second material and has a thickness exceeding 100 angstroms. 3. The insert member of claim 1, wherein said wafer support is adapted to support a wafer, and said composite member has a second surface adapted to be disposed adjacent to said wafer, said second surface being formed by said The second material is made of a thickness exceeding 100 Angstroms. 4. The insert of claim 1, wherein _said second material is _SiO2 and said first material is one of SiC, _Al2O3 , _{Y2O3 ,} and Si having a purity of at least 99% kind. 5. The insert of claim 2, wherein _said second material is _SiO2 and said first material is one of SiC, _Al2O3 , _{Y2O3 ,} and Si having a purity of at least 99% kind. 6. The insert of claim 3, wherein _said second material is _SiO2 and said first material is one of SiC, _Al2O3 , _{Y2O3 ,} and Si having a purity of at least 99% kind. 7. The insert member of claim 1, wherein the thickness of the second material exceeds 1000 Angstroms. 8. The insert member of claim 2, wherein the thickness of the second material exceeds 1000 Angstroms. 9. The insert member of claim 3, wherein the thickness of the second material exceeds 1000 Angstroms. 10. The insert member of claim 3, wherein said composite member is generally annular. 11. The insert of claim 1, wherein the second material is comprised of a film layer. 12. An insert as claimed in claim 2, wherein said second material consists of a film layer. 13. The insert member of claim 2, wherein said outer member further comprises an insulating ring having vertical side walls and a horizontal upper surface, and said second surface is adapted to be disposed adjacent said vertical side walls and a horizontal upper surface. at the position of one of the surfaces. 14. The insert member of claim 13, wherein said composite member further has a third surface adapted to be disposed adjacent the other one of said vertical sidewall and horizontal upper surface, said third surface Made of said second material, having a thickness exceeding 100 Angstroms. 15. The insert of claim 3, wherein said wafer holder has a peripheral edge, said wafer has an overhanging wafer edge extending beyond said wafer holder peripheral edge, and said second surface is adapted to place adjacent to the edge of the overhanging wafer. 16. The interposer of claim 1, wherein the wafer holder has an electrostatic chuck (ESC), and the first surface is adapted to be disposed adjacent to the ESC. 17. An insert for use in a processing chamber having a wafer holder adapted to support a wafer and an outer member adapted to enclose the wafer holder, the insert comprising: A composite part consisting of a first material and a second material having an electrical impedance greater than said first material; The composite member has features adapted to be positioned adjacent to the wafer holder, the outer member and the the first surface at the location of one of the wafers; and The first surface is made of the second material and has a thickness exceeding 100 Angstroms. 18. An insert member as claimed in claim 17, wherein said composite member has a second surface adapted to be disposed adjacent the other one of said wafer holder, said outer member and said wafer, said The second surface is made of the second material and has a thickness exceeding 100 Angstroms. 19. An insert member as claimed in claim 18, wherein said composite member has a third surface adapted to be disposed adjacent the other one of said wafer holder, said outer member and said wafer, said The third surface is made of the second material and has a thickness exceeding 100 Angstroms. 20. The insert of claim 17, wherein the second material is comprised of a film layer. 21. The insert of claim 18, wherein the second material is comprised of a film layer. 22. The insert of claim 17, wherein said second material is _SiO2 and _said first material is one of SiC, _Al2O3 , _{Y2O3 ,} and Si having a purity of at least 99% kind. 23. The insert of claim 18, wherein said second material is _SiO2 and _said first material is one of SiC, _Al2O3 , _{Y2O3 ,} and Si having a purity of at least 99% kind. 24. The insert member of claim 17, wherein said composite member is generally annular. 25. The insert member of claim 18, wherein the thickness of the second material exceeds 1000 Angstroms. 26. The insert member of claim 18, wherein the thickness of the second material exceeds 1000 Angstroms. 27. The insert member of claim 19, wherein the thickness of the second material exceeds 1000 Angstroms. 28. An insert for use in a processing chamber having a base, the insert comprising: A composite part consisting of a first material and a second material having an electrical impedance greater than said first material; the composite component has a first surface adapted to be disposed adjacent the base; and The first surface is made of the second material and has a thickness exceeding 100 Angstroms. 29. An insert for use in a processing chamber having a wafer holder with a peripheral edge, the insert comprising: a generally annular component made of a first material; The member has a generally planar top surface, a generally planar bottom surface, a generally cylindrical outer surface, and a generally cylindrical inner surface; The component is adapted to be placed in the chamber such that at least a portion of the inner surface is adjacent the peripheral edge of the wafer holder; and The part also has a layer of a second material having a thickness greater than 100 angstroms, the resistance of the second material The layer is more resistant than the first material, and the layer is disposed on one of the top surface, the bottom surface, the outer surface, and the inner surface. 30. The insert of claim 29, wherein said layer is disposed on the other of said top surface, said bottom surface, said outer surface, and said inner surface. 31. The insert of claim 30, wherein said layer is disposed on the other of said top surface, said bottom surface, said outer surface, and said inner surface. 32. The insert of claim 31, wherein said layer is disposed on the other of said top surface, said bottom surface, said outer surface, and said inner surface. 33. The insert part of claim ₂₉ , wherein said first material is one of SiC, _Al2O3 , _{Y2O3 ,} and Si with a purity of at least 99%, and said second material is a purity At least 99% SiO ₂ . 34. The insert part of _claim 30, wherein said first material is one of SiC, _Al2O3 , _Y2O3 and Si with a purity of at least 99%, and said second material is _a purity At least 99% SiO ₂ . 35. The interposer of claim 29, wherein the layer has a thickness in excess of 1000 Angstroms. 36. The interposer of claim 30, wherein the layer has a thickness in excess of 1000 Angstroms. 37. The insert component of claim 29, wherein said wafer holder has an electrostatic chuck (ESC) with a peripheral edge, and said component is adapted to be placed in said chamber such that at least a portion of said inner surface is adjacent the ESC perimeter edge. 38. An insert for use in a processing chamber having a wafer holder with a peripheral edge adapted to support a wafer with an overhanging wafer edge extending beyond the wafer holder perimeter Edges aside, the insert includes: a first part made of one of SiC, Al ₂ O ₃ , Y ₂ O ₃ and Si with a purity of at least 99%; A second part made of _SiO2 ; the first part and the second part are arranged adjacent to each other; The first and second components are adapted to be placed in the chamber such that at least the first a portion of one of the first component and the second component is spaced from the overhanging wafer edge; and The second member is adapted to be positioned in the chamber such that at least a portion of the second member is adjacent to one of the wafer holder peripheral edge and the outrigger wafer edge. 39. A processing apparatus for use in a processing chamber having a fluorine-containing plasma and a wafer holder with a peripheral edge adapted to support a wafer with an overhanging wafer edge extending into the Outside the peripheral edge of the wafer holder, the handling apparatus includes: a top ring having a silicon top surface adapted to face and remove fluorine from the plasma, the silicon top surface having an inner peripheral edge, the an inner peripheral edge adapted to be spaced from and enclose the overhanging wafer edge; and an insert ring adapted to be placed between said wafer holder peripheral edge and said top ring inner peripheral edge, said insert ring having a top _SiO2 surface having a thickness in excess of 100 angstroms, at least a portion of said surface adapted to be placed between The overhanging wafer edge is below and spaced from the overhanging wafer edge and electrically insulates the overhanging wafer edge from the wafer holder. 40. The processing device of claim 39 , wherein a portion of the top _SiO2 surface of the insert ring is adapted to be disposed adjacent an inner peripheral edge of a silicon top surface of the top ring and is exposed to the plasma middle. 41. The processing apparatus of claim 39, wherein said insert ring has an inner cylindrical _SiO2 surface having a thickness in excess of 100 angstroms, adapted to be positioned adjacent a peripheral edge of said wafer holder, and adapted to allow said An insert ring is electrically insulated from the wafer holder. 42. An apparatus for processing semiconductor wafers, comprising: bottom wall; a side wall connected to the bottom wall, the bottom wall and the side wall forming a cavity; a wafer holder disposed in the cavity, the wafer holder having a peripheral edge; a generally annular component made of a first material; The member has a generally planar top surface, a generally planar bottom surface, a generally cylindrical outer surface, and a generally cylindrical inner surface; the member is adapted to be placed in the cavity such that at least a portion of the inner surface is adjacent to a peripheral edge of the wafer holder; and The component also has a layer of a second material having a thickness greater than 100 angstroms, the second material has an electrical impedance greater than that of the first material, the layer is disposed on the top surface, the bottom surface, the outer surface, and on one of the inner surfaces. 43. The device of claim 42, wherein said layer is disposed on the other of said top surface, said bottom surface, said outer surface, and said inner surface. 44. The device of claim 43, wherein said layer is disposed on the other of said top surface, said bottom surface, said outer surface, and said inner surface. 45. The device of claim 44, wherein said layer is disposed on the other of said top surface, said bottom surface, said outer surface, and said inner surface. 46. The apparatus of _claim 42, wherein the first material is one of SiC, _Al2O3 , _{Y2O3 ,} and Si with a purity of at least 99%, and the second material is at least 99% SiO ₂ . 47. The apparatus of _claim 43, wherein said first material is one of SiC, _Al2O3 , _{Y2O3 ,} and Si with a purity of at least 99%, and said second material is at least 99% SiO ₂ . 48. The device of claim 42, wherein the layer is over 1000 Angstroms thick. 49. The interposer of claim 43, wherein the layer has a thickness in excess of 1000 Angstroms. 50. A method of assembling an apparatus for semiconductor wafer processing comprising the steps of: providing a processing chamber having a chamber cavity; providing an electrostatic chuck (ESC) for supporting a wafer in the cavity; and placing an insert component adjacent to the ESC, the insert component comprising: a composite part comprised of a first material and a second material, the second material having a greater electrical impedance than the first material; the composite component has a first surface adapted to be disposed adjacent to one of the ESC and the wafer; and The first surface is made of the second material and has a thickness exceeding 100 Angstroms. 51. The method of claim 50, wherein the composite component has a second surface adapted to be positioned adjacent the other of the ESC and the wafer, and the first surface The two surfaces are made of the second material, and the thickness exceeds 100 angstroms. 52. The method of claim 50, wherein the first surface is comprised of a thin film layer. 53. The method of claim 51, wherein the first and second surfaces are comprised of thin film layers. 54. The method of claim 50, wherein the second _material is _SiO2 and the first material is one of SiC, _Al2O3 , _{Y2O3 ,} and Si having a purity of at least 99% . 55. The method of claim 51, wherein _the second material is _SiO2 and the first material is one of SiC, _Al2O3 , _{Y2O3 ,} and Si having a purity of at least 99% . 56. The method of claim 50, wherein the composite member is generally annular. 57. A method of assembling an apparatus for semiconductor wafer processing comprising the steps of: providing a processing chamber having a chamber cavity; providing a wafer support for supporting a wafer in the cavity, the wafer support having a peripheral edge; and An insert member is positioned adjacent the peripheral edge of the wafer holder, the insert member comprising: a generally annular component made of a first material; The member has a generally planar top surface, a generally planar bottom surface, a generally cylindrical outer surface, and a generally cylindrical inner surface; and The part has a layer of a second material having a thickness greater than 100 angstroms, the second material has a greater electrical impedance than the first material, the layer is disposed on the top surface, the bottom surface, the outer surface, and the on one of the inner surfaces. 58. The method of claim 57, wherein said layer is disposed on the other of said top surface, said bottom surface, said outer surface, and said inner surface. 59. The method of claim 58, wherein said layer is disposed on the other of said top surface, said bottom surface, said outer surface, and said inner surface. 60. The method of claim 59, wherein said layer is disposed on the other of said top surface, said bottom surface, said outer surface, and said inner surface. 61. The method of claim 57, wherein the first material is one of SiC, Al ₂ O ₃ , Y ₂ O ₃ and Si with a purity of at least 99%, and the second material is at least 99% SiO ₂ . 62. The method of claim 58, wherein the first material is one of SiC, Al ₂ O ₃ , Y ₂ O ₃ and Si with a purity of at least 99%, and the second material is at least 99% SiO ₂ . 63. The method of claim 57, wherein the layer thickness exceeds 1000 Angstroms. 64. The method of claim 58, wherein the layer thickness exceeds 1000 Angstroms. 65. A method of processing a semiconductor wafer comprising: providing a processing chamber having a chamber cavity; providing a wafer holder with a peripheral edge adapted to support the wafer in the cavity; An insert member for use in the process chamber is provided, the insert member being generally annular in shape and made of a first material, the insert member also having a generally planar top surface, a generally planar bottom surface, a generally cylindrical shaped outer surface and generally cylindrical inner surface; the insert member is adapted to be placed in the chamber such that at least a portion of the inner surface is adjacent the wafer holder peripheral edge; and The insert part also has a layer of a second material having a thickness greater than 100 Angstroms, the electrical impedance of the second material is greater than that of the first material, and the layer is disposed on the top surface, the bottom surface, and the outer surface and on one of said inner surfaces; and The wafer is placed on the wafer holder. 66. The method of claim 65, wherein said layer is disposed on the other of said top surface, said bottom surface, said outer surface, and said inner surface. 67. The method of claim 66, wherein said layer is disposed on the other of said top surface, said bottom surface, said outer surface, and said inner surface. 68. The method of claim 67, wherein said layer is disposed on the other of said top surface, said bottom surface, said outer surface, and said inner surface. 69. The method of claim 65, wherein the layer thickness exceeds 1000 Angstroms. 70. The method of claim 66, wherein the layer thickness exceeds 1000 Angstroms. 71. An insert for use in a processing chamber adapted to ignite a plasma, said chamber comprising a wafer holder adapted to support a silicon wafer with a perimeter, said chamber further comprising an outer member adapted to enclose said wafer holder , the insert components include: a silicon interposer for providing a silicon-containing surface around the periphery of the wafer, the interposer adapted to protect the wafer holder from contact with the plasma; and insulating means for isolating said interposer means from the flow of electrons between said interposer means and one of said outer part, said wafer holder and said wafer, said insulating means comprising A _SiO2 surface layer over 100 angstroms thick on the insert device. 72. The interposer of claim 71, wherein the _SiO2 surface layer is over 1000 angstroms thick. 73. An apparatus for processing a silicon wafer with a wafer perimeter using plasma, comprising: a processing chamber having a chamber cavity; means for supporting said wafer in said cavity; a silicon interposer for providing a silicon-containing surface around the periphery of the wafer, the interposer being adapted to protect the support from contact with the plasma; Insulating means for isolating said intervening means from the flow of electrons between said intervening means and said supporting means, said insulating means comprising _SiO2 disposed on said intervening means with a thickness exceeding 100 Angstroms surface layer; and means for exciting said plasma. 74. The apparatus as claimed in claim 73, further comprising second insulating means for insulating said interposer means from the electron flow between said interposer means and said wafer, said second insulating means comprising A surface layer of _SiO2 having a thickness greater than 100 Angstroms disposed on the interposer. 75. The apparatus of claim 74, further comprising: an insulating ring adapted to be positioned adjacent the insertion device; and Third insulating means for isolating said insertion means from the flow of electrons between said insertion means and said insulating ring, said third insulating means comprising a thickness greater than 100mm disposed on said insertion means angstroms of the SiO ₂ surface layer. 76. The device of claim 73, wherein the _SiO2 surface layer is over 1000 Angstroms thick.

Images