CN1698198A - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

A semiconductor device includes at least one semiconductor component (3) having a plurality of external connection electrodes (6) formed on a semiconductor substrate (5). An insulating member (14, 14A) is provided on one side of the semiconductor component (3). An upper interconnection (17, 54) has a connection pad portion, which is provided on an insulating plate member (14, 41A) corresponding to the upper interconnection and connected to the external connection electrodes (6) of the semiconductor component (3).

Description

Semiconductor device and manufacturing method thereof

technical field

The present invention relates to a semiconductor device, and more particularly to a semiconductor device belonging to a small semiconductor package called CSP (Chip Scale Package) and a method of manufacturing the same.

Background technique

In recent years, as portable electronic devices typified by cellular phones have been reduced in size, semiconductor devices called CSP (Chip Scale Package) have been developed. In CSP, a passivation film (intermediate insulating film) is formed on the upper surface of a bare semiconductor device having a plurality of connection pads for external connection. Opening portions are formed in the passivation film and correspond to the connection pads. The interconnection is connected to one end side of the connection pad through the opening portion. A columnar electrode for external connection is formed on the other end side of the interconnection. The space between the columnar electrodes for external connection is filled with a sealing material. According to this CSP, when solder balls are formed on columnar electrodes for external connection, the device can be connected to a circuit board having connection terminals by a face-down method. The mounting area can be almost the same size as the bare semiconductor device. CSP thus greatly reduces the size of electronic devices compared to conventional face-up connection methods using wire connections. US Pat. No. 6,467,674 discloses a method in which passivation films, interconnections, external connection electrodes, and sealing materials are formed on a semiconductor substrate in a wafer state in order to increase yield. Solder balls are then formed on the upper surfaces of the external connection electrodes exposed without being covered by the sealing material. Then, the wafer is diced along dicing lines, thereby forming individual semiconductor devices.

Conventional semiconductor devices have a problem that as the degree of integration becomes higher, the number of external connection electrodes increases. As described above, in CSP, external connection electrodes are arranged on the upper surface of a bare semiconductor device. Therefore, the external connection electrodes are usually arranged in a matrix. In a semiconductor device having many external connection electrodes, the size and pitch of the external connection electrodes become particularly small. Due to this drawback, CSP technology cannot be applied to devices having a large number of external connection electrodes relative to the size of bare semiconductor devices. If the external connection electrodes have an extremely small size and pitch, alignment with the circuit board is very difficult. There are also many fatal problems, such as low connection strength, short circuit between electrodes in connection, and stress caused by the difference in linear expansion coefficient between the circuit board and the semiconductor substrate usually formed of a silicon substrate, which causes damage to the external connection electrodes. damage.

Contents of the invention

An object of the present invention is to provide a new semiconductor device and a method of manufacturing the same, which can ensure the required size and pitch of external connection electrodes even if the number of electrodes is increased.

According to one aspect of the present invention, a semiconductor device is provided, including: at least one semiconductor member having a semiconductor substrate and a plurality of external connection electrodes formed on the semiconductor substrate; an insulating plate member disposed on one side of the semiconductor member; and a plurality of upper interconnects having connection pad portions provided on the insulating plate member corresponding to the upper interconnects and electrically connected to external connection electrodes of the semiconductor member.

According to another aspect of the present invention, there is provided a method of manufacturing a semiconductor device, comprising: arranging a plurality of semiconductor components on a substrate, each semiconductor component having a semiconductor substrate and a plurality of connection pads, while separating the semiconductor components from each other, and disposing at least one insulating sheet at a position corresponding to the semiconductor member, heating and pressing the insulating sheet from the upper side of the insulating sheet, thereby melting and solidifying the insulating sheet between the semiconductor members, forming at least one layer of upper interconnection , the upper interconnection has a connection pad portion and is connected to a corresponding one of the plurality of connection pads of one of the plurality of semiconductor components, so that the connection pad portion is provided on the insulating plate corresponding to the upper interconnection, and on the semiconductor The insulating sheet is cut between the members, thereby obtaining a plurality of semiconductor devices in which connection pad portions of upper interconnections are provided on the insulating sheet.

Description of drawings

1 is a cross-sectional view of a semiconductor device according to a first embodiment of the present invention;

Fig. 2 is the sectional view of the initial preparation structure in the example of the manufacturing method of semiconductor device shown in Fig. 1;

Fig. 3 is a cross-sectional view showing a manufacturing step after Fig. 2;

Fig. 4 is a cross-sectional view showing a manufacturing step after Fig. 3;

Fig. 5 is a cross-sectional view showing a manufacturing step subsequent to Fig. 4;

Fig. 6 is a cross-sectional view showing a manufacturing step subsequent to Fig. 5;

Fig. 7 is a cross-sectional view showing a manufacturing step after Fig. 6;

Fig. 8 is a sectional view showing a manufacturing step after Fig. 7;

Fig. 9 is a sectional view showing a manufacturing step after Fig. 8;

Fig. 10 is a cross-sectional view showing a manufacturing step after Fig. 9;

Fig. 11 is a cross-sectional view showing a manufacturing step subsequent to Fig. 10;

Fig. 12 is a cross-sectional view showing a manufacturing step subsequent to Fig. 11;

Fig. 13 is a sectional view showing a manufacturing step after Fig. 12;

Fig. 14 is a sectional view showing a manufacturing step after Fig. 13;

Fig. 15 is a sectional view showing a manufacturing step after Fig. 14;

Fig. 16 is a sectional view showing a manufacturing step after Fig. 15;

17 is a cross-sectional view of a semiconductor device according to a second embodiment of the present invention;

18 is a cross-sectional view of a semiconductor device according to a third embodiment of the present invention;

19 is a cross-sectional view of a semiconductor device according to a fourth embodiment of the present invention;

20 is a cross-sectional view of a semiconductor device according to a fifth embodiment of the present invention;

21 is a cross-sectional view of a semiconductor device according to a sixth embodiment of the present invention;

22 is a cross-sectional view of a semiconductor device according to a seventh embodiment of the present invention;

23 is a cross-sectional view of a semiconductor device according to an eighth embodiment of the present invention;

24 is a sectional view showing predetermined manufacturing steps in the example of the manufacturing method of the semiconductor device shown in FIG. 23;

Fig. 25 is a sectional view showing a manufacturing step after Fig. 24;

26 is a cross-sectional view of a semiconductor device according to a ninth embodiment of the present invention;

27 is a sectional view showing predetermined manufacturing steps in the example of the manufacturing method of the semiconductor device shown in FIG. 26;

Fig. 28 is a sectional view showing a manufacturing step after Fig. 27;

Fig. 29 is a sectional view showing a manufacturing step after Fig. 28;

30 is a cross-sectional view of a semiconductor device according to a tenth embodiment of the present invention;

31 is a cross-sectional view of a semiconductor device according to an eleventh embodiment of the present invention;

32 is a cross-sectional view of a semiconductor device according to a twelfth embodiment of the present invention;

33 is a cross-sectional view of a semiconductor device according to a thirteenth embodiment of the present invention;

34 is a cross-sectional view of a semiconductor device according to a fourteenth embodiment of the present invention;

35 is a cross-sectional view of a semiconductor device according to a fifteenth embodiment of the present invention;

FIG. 36 is a cross-sectional view for explaining manufacturing steps of the semiconductor device shown in FIG. 35;

Fig. 37 is a sectional view showing a manufacturing step after Fig. 36;

Fig. 38 is a sectional view showing a manufacturing step after Fig. 37;

Fig. 39 is a sectional view showing a manufacturing step after Fig. 38;

Fig. 40 is a sectional view showing the manufacturing steps after Fig. 39;

Fig. 41 is a sectional view showing the manufacturing steps after Fig. 40;

Fig. 42 is a sectional view showing the manufacturing steps after Fig. 41;

Fig. 43 is a cross-sectional view showing a manufacturing step subsequent to Fig. 42;

44 is a cross-sectional view of a semiconductor device according to a sixteenth embodiment of the present invention;

45 is a cross-sectional view of a semiconductor device according to a seventeenth embodiment of the present invention;

46 is a cross-sectional view of a semiconductor device according to an eighteenth embodiment of the present invention;

47 is a sectional view for explaining the manufacturing steps of the semiconductor device shown in FIG. 46;

Fig. 48 represents the sectional view of the manufacturing step after Fig. 47;

Figure 49 is a cross-sectional view showing a manufacturing step after Figure 48; and

Fig. 50 is a cross-sectional view showing a manufacturing step subsequent to Fig. 49 .

Detailed ways

(first embodiment)

FIG. 1 is a cross-sectional view of a semiconductor device according to a first embodiment of the present invention. The semiconductor device has a rectangular planar shape and a metal layer 1 made of copper or the like and an insulating layer 2 formed on the lower surface of the metal layer 1 and made of solder resist. The metal layer prevents electrification or light irradiation on the integrated circuit of the silicon substrate 5 (to be described below). The insulating layer 2 protects the metal layer 1 .

The lower surface of semiconductor member 3 , which has a rectangular planar shape and is slightly smaller than metal layer 1 , is connected to the upper surface center portion of metal layer 1 via adhesive layer 4 made of a die-bonding material. The semiconductor member 3 has interconnections, columnar electrodes, and a sealing film (to be described below) and is generally called a CSP. In particular, since a method of forming interconnections, columnar electrodes, and sealing films on a silicon wafer, and then performing dicing to obtain individual semiconductor members 3, as described later, the semiconductor member 3 is specifically called wafer-level CSP (W -CSP). The structure of the semiconductor member 3 will be described below.

The semiconductor member 3 has a silicon substrate (semiconductor substrate) 5 having a rectangular planar shape and connected to the metal layer 1 via an adhesive layer 4 . An integrated circuit (not shown) is formed on the central portion of the upper surface of silicon substrate 5 . A plurality of connection pads (external connection electrodes) 6 made of an aluminum-based metal and connected to an integrated circuit are formed on a peripheral portion of the upper surface of the silicon substrate 5 . An insulating film 7 made of silicon oxide is formed on the upper surface of the silicon substrate 5 and on the connection pads 6 except for the center portion of each connection pad. A central portion of each connection pad 6 is exposed through an opening portion 8 formed in the insulating film 7 .

A protective film (insulating film) 9 made of epoxy resin or polyimide resin is formed on the upper surface of insulating film 7 on silicon substrate 5 . The opening portion 10 is formed in the protective film 9 at a position corresponding to the opening portion 8 of the insulating film 7 . Interconnection 11 made of copper extends from the upper surface of each connection pad 6 exposed through opening portions 8 and 10 to a predetermined portion of the upper surface of protective film 9 .

A columnar electrode (external connection electrode) 12 made of copper is formed on the upper surface of the connection pad portion of each interconnection 11 . A sealing film (insulating film) 13 made of epoxy resin or polyimide resin is formed on the upper surfaces of protective film 9 and interconnection 11 . The upper surface of the sealing film 13 is flush with the upper surface of the columnar electrode 12 . As described above, the semiconductor member 3 of so-called W-CSP includes the silicon substrate 5 , the connection pad 6 , and the insulating film 7 , and further includes the protective film 9 , interconnection 11 , columnar electrode 12 , and sealing film 13 .

A first insulating material (insulating plate member) 14 having a rectangular frame shape is provided on the upper surface of the metal layer 1 around the semiconductor member 3 . The upper surface of the first insulating material 14 is almost flush with the upper surface of the semiconductor member 3 . A second insulating material 15 having a flat upper surface is provided on the upper surfaces of the semiconductor member 3 and the first insulating material 14 .

The first insulating material 14 is commonly referred to as a prepreg and is prepared by, for example, impregnating a thermosetting resin such as epoxy resin into glass fibers. The second insulating material 15 is generally referred to as aggregate material for the aggregate substrate. The second insulating material 15 is composed of a thermosetting resin such as epoxy resin or BT (bismaleimide triazine) resin containing reinforcing materials such as fibers or fillers. In this case, the fibers are preferably made of glass fibers or ammonium aramid fibers. The filler is preferably a silica filler or a ceramic filler.

An opening portion 16 is formed in the second insulating material 15 at a position corresponding to a central portion of the upper surface of the columnar electrode 12 . Upper interconnections 17 made of copper are arranged in a matrix. Each upper interconnection 17 extends to a predetermined portion of the upper surface of the second insulating material 15 from the upper surface of the corresponding one of the columnar electrodes 12 exposed from the upper surface of the insulating material 15 through the opening portion 16 .

An upper insulating film 18 made of solder resist is formed on upper surfaces of upper interconnect 17 and second insulating material 15 . An opening portion 19 is formed in the upper insulating film 18 at a position corresponding to the connection pad of the upper interconnection 17 . Bump electrodes 20 formed of solder balls are formed in and on the opening portion 19 and are electrically (and mechanically) connected to the connection pad portion of the upper interconnection 17 . The protruding electrodes 20 are provided in a matrix on the upper insulating film 18 .

The size of the metal layer 1 is slightly larger than the size of the semiconductor component 3 . The reason is as follows. As the number of connection pads on the silicon substrate 5 increases, the area where the protruding electrodes 20 are provided is slightly larger than the size of the semiconductor member 3 . Thus, the size and pitch of the connection pad portion of upper interconnection 17 (portion in opening portion 19 of upper insulating film 8 ) are formed larger than those of columnar electrodes 12 .

Therefore, the connection pad portions of the upper interconnections 17 arranged in a matrix are mounted not only on the region corresponding to the semiconductor member 3 but also on the region corresponding to the first insulating material 14 provided outside the outer side surface of the semiconductor member 3 . That is, among the protruding electrodes 20 arranged in a matrix, at least the protruding electrodes 20 at the outermost positions are provided around the semiconductor member 3 .

As described above, as a feature of this semiconductor device, the first and second insulating members 14 and 15 are provided around and on the semiconductor member 3 in which not only the connection pad 6 and the insulating film 7 but also the protective film 9 , interconnections 11 , columnar electrodes 12 and sealing film 13 are formed on silicon substrate 5 . Upper interconnection 17 connected to columnar electrode 12 through opening portion 16 formed in second insulating material 15 is formed on the upper surface of second insulating material 15 .

In the above structure, the upper surface of the second insulating material 15 is flat. For this reason, the height positions of the upper surfaces of the upper interconnection 17 and the protruding electrode 20 formed in a later step can be uniform, and the reliability of connection can be improved.

An example of a method of manufacturing a semiconductor device will be described below. First, an example of a method of manufacturing the semiconductor member 3 will be described. In this case, as shown in FIG. 2, an assembly member is prepared in which a connection pad 6 made of aluminum-based metal, an insulating film 7 made of silicon oxide, and an epoxy resin or polyimide resin The produced protective film 9 is formed on the silicon substrate (semiconductor substrate) 5 in a wafer state, and the central portion of the connection pad 6 is exposed through the opening portions 8 and 10 formed in the insulating film 7 and the protective film 9 . In the above structure, an integrated circuit having a predetermined function is formed in a region of the silicon substrate 5 in a wafer state where each semiconductor member is to be formed. Each connection pad 6 is electrically connected to an integrated circuit formed in a corresponding area.

Next, as shown in FIG. 3 , lower metal layer 11 a is formed on the entire upper surface of protective film 9 including the upper surface of connection pad 6 exposed through opening portions 8 and 10 . In this case, the lower metal layer 11a may have only a copper layer formed by electroless plating or only a copper layer formed by sputtering. Alternatively, a copper layer may be formed by sputtering on a thin titanium layer formed by sputtering. This also applies to the lower metal layer of the upper interconnection 17 (to be described later).

Next, a plating resist film 21 is formed and patterned on the upper surface of the lower metal layer 11a. In this case, the patterned resist film 21 has an opening portion 22 at a position corresponding to the formation area of each interconnection 11 . Copper plating is performed using lower metal layer 11 a as a plating current path, thereby forming upper metal layer 11 b on the upper surface of lower metal layer 11 a in each opening portion 22 of plating resist film 21 . Then, the plating resist film 21 is removed.

As shown in FIG. 4, a plating resist film 23 is formed and patterned on the upper surface of the lower metal layer 11a including the upper metal layer 11b. In this case, the patterned resist film 23 has an opening portion 24 at a position corresponding to the formation region of each columnar electrode 12 . Copper plating is performed using lower metal layer 11a as a plating current path, thereby forming columnar electrode 12 on the upper surface of the connection pad of upper metal layer 11b in each opening portion 24 of plating resist film 23 .

Then, the plating resist film 23 is removed. Then, using the pillar electrode 12 and the upper metal layer 11b as a mask, the unnecessary part of the lower metal layer 11a is removed by etching, so that the lower metal layer 11a remains only under the upper metal layer 11b, as shown in FIG. 5 . Each remaining lower metal layer 11a and upper metal layer 11b formed on the entire upper surface of lower metal layer 11a constitute interconnection 11 .

As shown in FIG. 6, a sealing film 13 made of epoxy resin or polyimide resin is formed on the entire upper surface of the protective film 9, columnar electrodes 12, and interconnections 11 by screen printing, spin coating, or die coating. . The thickness of the sealing film 13 is greater than the height of the columnar electrodes 12 . Therefore, in this state, the upper surface of the columnar electrode 12 is covered with the sealing film 13 . The sealing film 13 and the upper surface side of the columnar electrode 12 are appropriately polished, thereby exposing the upper surface of the columnar electrode 12 as shown in FIG. 7 . The upper surface of the sealing film 13 including the exposed upper surface of the columnar electrode 12 is also planarized.

The reason why the upper surface side of the columnar electrode 12 is properly polished is that the height of the columnar electrode 12 formed by plating varies and must be made uniform by removing the variation. In order to simultaneously polish the columnar electrode 12 made of soft copper and the sealing film 13 made of epoxy resin or the like, a grinder having a grindstone of appropriate roughness is used.

As shown in FIG. 8 , adhesive layer 4 is attached to the entire lower surface of silicon substrate 5 . The adhesive layer 4 is made of a die-bonding material such as epoxy or polyimide and bonded to the silicon substrate 5 in a temporarily set state by heating and pressing. Next, the adhesive layer 4 bonded to the silicon substrate 5 is attached to a dicing tape (not shown). After the cutting step shown in FIG. 9, the individual members are peeled off from the cut tape. Thus, a plurality of semiconductor members 3 are obtained, each having an adhesive layer 4 on the lower surface of a silicon substrate 5, as shown in FIG. 1 .

In semiconductor member 3 thus obtained, adhesive layer 4 exists on the lower surface of silicon substrate 5 . Therefore, a very troublesome operation for forming an adhesive layer on the lower surface of the silicon substrate 5 of each semiconductor member 3 after the cutting step is not required. The operation for peeling each semiconductor member from the dicing tape after the dicing step is much simpler than the operation for forming an adhesive layer on the lower surface of the silicon substrate 5 of each semiconductor member 3 after the dicing step.

An example will be described below in which the semiconductor device shown in FIG. 1 is manufactured using the semiconductor member 3 obtained by the method described above. First, as shown in FIG. 10 , a substrate 31 is prepared. The substrate 31 is so large that a plurality of copper foils constituting the upper surface side of the metal layer 1 as shown in FIG. 1 are sampled, which will be described later. The substrate 31 has a rectangular planar shape, particularly approximately a square planar shape, but its shape is not limited thereto. The copper foil is attached to the upper surface of the substrate 31 via an adhesive layer 32 .

The substrate 31 may be made of an insulating material such as glass, ceramics, or resin. In this case, a substrate made of aluminum is used as an example. Regarding the size, the thickness of the substrate 31 made of aluminum is about 0.4 mm, and the thickness of the copper foil 1 a is about 0.012 mm. The substrate 31 is used because the copper foil 1a is too thin and cannot be used as a substrate. The device copper foil 1a is used as an antistatic member in the manufacturing step.

Next, the adhesive layer 4 bonded to the lower surface of the silicon substrate 5 of the semiconductor member 3 is bonded to a plurality of predetermined portions of the upper surface of the copper foil 1a. During this bonding process, the adhesive layer 4 is finally set by heat and pressure. Two first insulating plate pieces 14a and 14b each having opening portions arranged in a matrix are aligned and stacked on the upper surface of the copper foil 1a between the semiconductor member 3 and the outside of the semiconductor member 3 at the outermost position. The second insulating plate member 15a is placed on the upper surface of the first insulating plate member 14b. The semiconductor member 3 may be provided after stacking and disposing the two first insulating plate pieces 14a and 14b.

The first insulating plate members 14a and 14b each having a matrix shape can be obtained in the following manner. A thermosetting resin such as epoxy is infused into the fiberglass. Thermosetting resins are semi-cured in order to prepare prepregs in sheet form. A plurality of rectangular opening portions 33 are formed in the prepreg by die-cutting or etching. In this case, in order to obtain flatness, each of the first insulating plate members 14a and 14b must be a plate-shaped member. However, the material need not always be a prepreg material. Thermosetting resins or thermosetting resins in which reinforcing materials such as glass fibers or silica fillers are dispersed may also be used.

The second insulating plate part 15a is preferably made of aggregate material, but is not limited thereto. As the aggregation material, a thermosetting resin such as epoxy resin or BT resin in which silica filler and semi-cured are mixed can be used. However, as the second insulating sheet member 15a, the above-mentioned prepreg material or a material containing no filler or only a thermosetting resin can be used.

The size of the opening portion 33 of the first insulating plate members 14 a and 14 b is slightly larger than that of the semiconductor member 3 . For this purpose, a gap 34 is formed between the first insulating sheet parts 14 a , 14 b and the semiconductor component 3 . The length of the gap 34 is, for example, approximately 0.1-0.5 mm. The total thickness of the first insulating plate parts 14 a and 14 b is greater than the thickness of the semiconductor component 3 . The first insulating sheet members 14a and 14b are thick enough to fill the gap 34 when the first insulating sheet members are heated and pressed, as will be described later.

In this case, first insulating plate members 14a and 14b having the same thickness are used. However, the first insulating plate substrates 14a and 14b may have different thicknesses. The first insulating sheet may comprise two layers, as described above. However, one or three or more layers may also be included. The thickness of the second insulating plate member 15a corresponds to or is slightly greater than the thickness of the second insulating material 15 to be formed on the semiconductor member 3 in FIG. 1 .

Next, the first insulating sheet members 14a and 14b and the second insulating sheet member 15a are heated and pressed using a pair of heating/pressurizing plates 35 and 36 shown in FIG. Thus, the molten thermosetting resin in the first insulating sheet parts 14a and 14b is pressed to fill the gap 34 between the first insulating sheet parts 14a, 14b and the semiconductor member 3, as shown in FIG. Through the subsequent cooling treatment, the thermosetting resin is semi-cured while adhering to the semiconductor member 3 and the copper foil 1a between them. In this way, as shown in FIG. 11 , the first insulating material 14 made of thermosetting resin containing a reinforcing material and bonded to the substrate 31 is formed on the outside of the semiconductor member 3 and the semiconductor member 3 located at the outermost position. on the upper surface of the copper foil 1a between them. Furthermore, a second insulating material 15 made of a thermosetting resin containing a reinforcing material is formed on the upper surfaces of the semiconductor member 3 and the first insulating material 14 .

In this case, as shown in FIG. 7 , in a wafer state, the columnar electrodes 12 in each semiconductor member 3 have a uniform height. In addition, the upper surface of the sealing film 13 including the upper surface of the columnar electrode 12 is planarized. For this reason, in the state shown in FIG. 11 , the plurality of semiconductor members 3 have the same thickness.

In the state shown in FIG. 11 , heating and pressurization are performed, while serving as a pressure limiting surface, a virtual plane higher than the upper surface of the semiconductor member 3 is defined by the diameter of a layer of reinforcing material such as silica filler. The second insulating material 15 on the semiconductor component 3 acquires a thickness equal to the diameter of the reinforcing material (eg silica filler). When the open-ended (open) flat press is used as a press with a pair of heating/pressurizing plates 35 and 36, excess thermosetting resin in the insulating sheet members 14a, 14b, 15a is squeezed out of the pair of heating/heating plates 35 and 36. 36.

The upper surface of the second insulating material 15 is a flat surface because it is pressed on the upper side by the lower surface of the heating/pressurizing plate 36 . Therefore, a polishing step to planarize the upper surface of the second insulating material 15 is not required. Even if the copper foil 1a has a relatively large size, eg, about 500×500mm, the second insulating material 15 can be easily planarized at one time with respect to the plurality of semiconductor members 3 provided on the copper foil 1a.

The first and second insulating materials 14 and 15 are composed of a thermosetting resin containing reinforcing materials such as fibers or fillers. For this reason, stress due to shrinkage during curing of the thermosetting resin can be reduced compared to a structure composed only of the thermosetting resin. This also prevents the copper foil 1a from bending.

In the manufacturing steps shown in FIG. 11, heating and pressurization may be performed by separate devices. That is, for example, pressurization may be performed only from the upper surface side while heating the lower surface of the semiconductor member 3 with a heater. Alternatively, heating and pressure can be performed in separate steps.

When the manufacturing steps shown in FIG. 11 are completed, the first and second insulating materials 14 and 15, the semiconductor member 3, and the copper foil 1a are integrated together. They stay only as strong as needed. Next, the substrate 31 and the adhesive layer 32 are peeled or removed by polishing or etching. This processing is performed in order to reduce the load in dicing (to be described later) and to reduce the thickness of the semiconductor device as a product. In the manufacturing step shown in FIG. 10, when the insulating sheet members 14a, 14b, and 15a are temporarily cured and temporarily bonded to the upper surface of the copper foil 1a by temporary contact bonding, it is possible to pass this step after this step by polishing or Etching lifts or removes the substrate 31 and the adhesive layer 32 .

Then, as shown in FIG. 12 , opening portion 16 is formed in second insulating material 15 at a position corresponding to the central portion of the upper surface of columnar electrode 12 by laser machining of irradiating second insulating material 15 with a laser beam. Then, epoxy oil stains generated in the opening portion 16 are removed by degreasing treatment as required.

As shown in FIG. 13 , upper interconnection forming layer 17 a is formed on the entire upper surface of second insulating material 15 including the upper surface of columnar electrode 12 exposed through opening portion 16 . At the same time, a metal film 1b is formed on the lower surface of the copper foil 1a. In this case, the upper interconnection forming layer 17a and the metal film 1b each include, for example, a lower metal layer formed of a copper layer formed by electroless plating and an upper metal layer formed on the surface of the lower metal layer. Yes, the upper metal layer is formed by performing copper electroplating using the lower metal layer as a plating current path.

When the upper interconnection forming layer 17a is patterned by photolithography, an upper interconnection 17 is formed at a predetermined position on the upper surface of the second insulating material 15, as shown in FIG. In this state, upper interconnection 17 is connected to the upper surface of columnar electrode 12 through opening portion 16 in second insulating material 15 . The copper foil 1 a and the metal film 1 b formed on the lower surface thereof form a metal layer 1 .

As shown in FIG. 15 , an upper insulating film 18 made of a solder resist is formed on the entire upper surface of the second insulating material 15 including the upper interconnect 17 by screen printing or spin coating. In this case, upper insulating film 18 has opening portion 19 at a position corresponding to the connection pad portion of upper interconnection 17 . Furthermore, an insulating layer 2 made of a solder resist is formed on the lower surface of the metal layer 1 by spin coating. Subsequently, the protruding electrode 20 is formed in and on the opening portion 19 and connected to the connection pad portion of the upper interconnect 17 .

As shown in FIG. 16, when the upper insulating film 18, the first and second insulating materials 14 and 15, the metal layer 1 and the insulating layer 2 are cut between adjacent semiconductor members 3, a semiconductor device as shown in FIG. 1 is obtained .

In the semiconductor device thus obtained, the upper interconnection 17 to be connected to the stud-on electrode 12 of the semiconductor member 3 is formed by electroless plating (or sputtering) and electroplating. For this reason, electrical connection between each upper interconnection 17 and the corresponding columnar electrode 12 of the semiconductor component 3 can be reliably ensured.

In the above-described manufacturing method, a plurality of semiconductor members 3 are provided on the copper foil 1 a via the adhesive layer 4 . For a plurality of semiconductor members 3, the first and second insulating materials 14 and 15, the upper interconnection 17, the upper insulating film 18, and the protruding electrode 20 can be formed at one time. Thereafter, the semiconductor structure is separated, thereby obtaining a plurality of semiconductor devices. Therefore, the manufacturing steps can be simplified. Furthermore, as seen from the manufacturing steps shown in FIG. 12, a plurality of semiconductor members 3 can be conveyed together with the copper foil 1a. This also simplifies the manufacturing steps.

In the above manufacturing method, as shown in FIG. 10 , the CSP type semiconductor member 3 having the interconnection 11 and the columnar electrode 12 is bonded to the copper foil 1 a via the adhesive layer 4 . Compared with the case where, for example, a standard semiconductor chip having connection pads 6 and insulating film 7 on silicon substrate 5 is bonded to copper foil 1a, and interconnections and columnar electrodes are formed on the sealing film formed around the semiconductor chip, Reduced costs.

For example, assume that the copper foil 1a has an almost circular shape of a predetermined size before dicing, such as a silicon wafer. In this case, if the interconnection and the columnar electrodes are formed on the sealing film formed around the semiconductor chip bonded to the copper foil 1a, the processing area increases. In other words, since low-density processing is performed, the number of processed wafers per cycle is reduced. This reduces yield and increases costs.

In contrast, in the above-described manufacturing method, the CSP type semiconductor member 3 having the interconnection 11 and the columnar electrode 12 is bonded to the copper foil 1a via the adhesive layer 4, and then build-up is performed. Although the number of processes increases, efficiency improves because high-density processes are performed until the columnar electrodes 12 are formed. For this reason, the total cost can be reduced even taking into account the increase in the number of processes.

In the above-described embodiments, the protruding electrodes 20 are arranged in a matrix and correspond to the entire surface of the semiconductor member 3 and the first insulating material 14 around it. However, the protruding electrodes 20 may be arranged only on the regions corresponding to the first insulating material 14 around the semiconductor member 3 . The protruding electrode 20 may be formed not always around the semiconductor member 3 but on one to three of the four sides of the semiconductor member 3 . In this case, the first insulating material 14 does not have to have a rectangular frame shape, and may be provided only on one side where the protruding electrode 20 is to be formed.

(second embodiment)

17 is a cross-sectional view of a semiconductor device according to a second embodiment of the present invention. This semiconductor device differs from the semiconductor device shown in FIG. 1 in that it has no insulating layer 2 .

In manufacturing the semiconductor device according to the second embodiment, insulating layer 2 is not formed on the lower surface of metal layer 1 in the manufacturing steps shown in FIG. 15 . After the protruding electrodes 20 are formed, the upper insulating film 18 , the first and second insulating materials 14 and 15 , and the metal layer 1 are cut between adjacent semiconductor members 3 . Thus, a plurality of semiconductor devices shown in FIG. 17 are obtained. The plurality of semiconductor devices thus obtained can be thin because there is no insulating layer 2 .

(third embodiment)

18 is a cross-sectional view of a semiconductor device according to a third embodiment of the present invention. This semiconductor device can be obtained by omitting the formation of metal layer 1b on the upper surface of copper foil 1a in the manufacturing steps shown in FIG. 13 and the formation of insulating layer 2 in the manufacturing steps shown in FIG. 15 .

(fourth embodiment)

19 is a cross-sectional view of a semiconductor device according to a fourth embodiment of the present invention. Such a semiconductor device can be obtained by omitting the formation of metal layer 1b on the lower surface of copper foil 1a in the manufacturing steps shown in FIG. 13 and omitting the formation of insulating layer 2 in the manufacturing steps shown in FIG.

(fifth embodiment)

20 is a cross-sectional view of a semiconductor device according to a fifth embodiment of the present invention. This semiconductor device differs from the semiconductor device shown in FIG. 1 in that it has neither metal layer 1 nor insulating layer 2 .

In manufacturing the semiconductor device according to the fifth embodiment, for example, in the manufacturing steps shown in FIG. 15 , the formation of insulating layer 2 on the lower surface of metal layer 1 is omitted. After the protruding electrodes 20 are formed, the metal layer 1 is removed by polishing or etching. Subsequently, the upper insulating film 18 and the first and second insulating materials 14 , 15 are cut between adjacent semiconductor members 3 . Thus, a plurality of semiconductor devices shown in FIG. 20 are obtained. The semiconductor device thus obtained can be very thin since it has no metal layer 1 and no insulating layer 2 .

(sixth embodiment)

21 is a cross-sectional view of a semiconductor device according to a sixth embodiment of the present invention. Such a semiconductor device can be obtained in the following manner. For example, in the state shown in FIG. 19, the metal layer 1 is removed by polishing or etching. Then, the lower surface side of the silicon substrate 5 including the adhesive layer 4 and the lower surface side of the first insulating material 14 are appropriately polished. Next, the upper insulating film 18 and the first and second insulating materials 14, 15 are cut between adjacent semiconductor members 3, thereby obtaining a semiconductor device. The semiconductor devices thus obtained can be much thinner.

Or, before forming the protruding electrodes 20, remove the metal layer 1 (if necessary, the side of the lower surface of the silicon substrate 5 including the adhesive layer 4 and the side of the lower surface of the first insulating material 14) by polishing or etching. are also properly polished). Then, the protruding electrodes 20 are formed, and the upper insulating film 18 and the first and second insulating materials 14 and 15 are cut between adjacent semiconductor members 3 .

(seventh embodiment)

22 is a cross-sectional view of a semiconductor device according to a seventh embodiment of the present invention. This semiconductor device differs from the semiconductor device shown in FIG. 1 in that it has no metal layer 1 and no insulating layer 2, but has a substrate 31 instead.

In manufacturing the semiconductor device according to the seventh embodiment, in the manufacturing steps shown in FIG. 10 , the formation of the adhesive layer 32 and the copper foil 1 a on the upper surface of the substrate 31 is omitted. The semiconductor member 3 is bonded to the upper surface of the substrate 31 via the adhesive layer 4 formed on the lower surface thereof. Nothing is formed on the lower surface of the substrate 31 . After the protruding electrodes 20 are formed, the upper insulating film 18 , the first and second insulating materials 14 , 15 , and the substrate 31 are cut between adjacent semiconductor members 3 . Thus, a plurality of semiconductor devices shown in FIG. 22 are obtained.

(eighth embodiment)

23 is a cross-sectional view of a semiconductor device according to an eighth embodiment of the present invention. This semiconductor device differs from the semiconductor device shown in FIG. 1 in that a lower interconnection 41 is formed on the lower surface of the adhesive layer 4 and the first insulating material 14 and is connected to the upper interconnection 17 through a vertical electrical connection portion 43, Wherein the vertical electrical connection portion 43 is formed on the inner surface of the through hole 42 formed at a predetermined position of the first and second insulating materials 14 and 15 formed around the semiconductor member 3 .

In manufacturing the semiconductor device according to the eighth embodiment, for example, after the manufacturing steps shown in FIG. 11 , the substrate 31 , the adhesive layer 32 , and the copper foil 1 a are removed by polishing or etching. Next, as shown in FIG. 24 , an opening portion 16 is formed in the second insulating material 15 at a position corresponding to the center portion of the upper surface of the columnar electrode 12 by laser processing. Further, via holes 42 are formed at predetermined positions of the first and second insulating materials 14 and 15 provided around the semiconductor member 3 .

As shown in FIG. 25 , copper electroless plating and copper electroplating are successively performed to form upper interconnection forming layer 17 a on the entire upper surface of second insulating material 15 including the upper surface of columnar electrode 12 exposed through opening portion 16 . Furthermore, a lower interconnection forming layer 41 a is formed on the adhesive layer and the entire lower surface of the first insulating material 14 . Then, the vertical electrical connection portion 43 is formed on the inner surface of the through hole 42 .

Next, the upper interconnection forming layer 17a and the lower interconnection forming layer 41a are patterned by photolithography. For example, as shown in FIG. 23, the upper interconnection 17 is formed on the upper surface of the second insulating material 15, the lower interconnection 41 is formed on the lower surface of the adhesive layer 4 and the first insulating material 14, and is electrically connected vertically. Portion 43 remains on the inner surface of through hole 42 .

Next, it will be described with reference to FIG. 23 . An upper insulating film 18 made of a solder resist and having an opening portion 19 is formed on the upper surface of the second insulating material 15 including the upper interconnection 17 . Furthermore, a lower insulating film 44 made of solder resist is formed on the entire lower surface of the first insulating material 14 including the lower interconnection 41 . In this case, the vertical electrical connection portion 43 is filled with solder resist. Next, the protruding electrodes 20 are formed, and the upper insulating film 18 , the first and second insulating materials 14 , 15 , and the lower insulating film 44 are cut between adjacent semiconductor members 3 . Thus, a plurality of semiconductor devices shown in FIG. 23 are obtained.

(ninth embodiment)

Fig. 26 is a sectional view of a semiconductor device according to a ninth embodiment of the present invention. This semiconductor device is different from the semiconductor device shown in FIG. 23 in that the lower interconnection 41 is formed of a copper foil 1a and a copper layer 41a formed on the lower surface of the copper foil 1a, and the vertical electrical connection portion 43 forms a via hole 42. without forming any gaps.

In manufacturing the semiconductor device according to the ninth embodiment, for example, in the manufacturing step shown in FIG. Part 16, as shown in Figure 27. Further, via holes 42 are formed at predetermined positions of the first and second insulating materials 14 , 15 provided around the semiconductor member 3 . In this case, the copper foil 1 a is formed on the entire lower surfaces of the adhesive layer 4 and the first insulating material 14 . Therefore, the lower surface side of the through hole 42 is covered with the copper foil 1a.

As shown in FIG. 28 , copper plating is performed using the copper foil 1 a as a plating current path, thereby forming a vertical electrical connection portion 43 on the upper surface of the copper foil 1 a in the through hole 42 . In this case, the upper surface of the vertical electrical connection portion 43 is preferably almost flush with the upper plane of the through hole 42 or at a slightly lower position.

Next, as shown in FIG. 29 , copper electroless plating and copper electroplating are continuously performed so that the second electrode including the upper surface of the columnar electrode 12 exposed through the opening portion 16 and the upper surface of the vertical electrical connection portion 43 in the through hole 42 The upper interconnection forming layer 17a is formed on the entire upper surface of the insulating material 15 . Further, a lower interconnection forming layer 41a is formed on the entire lower surface of the copper foil 1a. Then, using the same manufacturing steps as in the eighth embodiment, a plurality of semiconductor devices shown in FIG. 26 are obtained.

(tenth embodiment)

30 is a cross-sectional view of a semiconductor device according to a tenth embodiment of the present invention. This semiconductor device differs from the semiconductor device shown in FIG. 1 in that it does not have the second insulating material 15 .

In manufacturing the semiconductor device of the tenth embodiment, after the manufacturing steps shown in FIG. 11 , the substrate 31 and the adhesive layer 32 are removed. Furthermore, the second insulating material 15 is removed by polishing. In this case, when the second insulating material 15 is removed by polishing, if the upper surface side of the sealing film 13 including the columnar electrode 12 and the semiconductor member 3 and the upper surface side of the first insulating material 14 are lightly polished, then there will be no problem.

Subsequent manufacturing steps are the same as those of the first embodiment. However, in the tenth embodiment, as shown in FIG. 30 , upper interconnection 17 is formed on the upper surfaces of semiconductor member 3 and first insulating material 14 and connected to the upper surface of columnar electrode 12 . An upper insulating film 18 having an opening portion 19 is formed on the upper interconnection 17 . The protruding electrode 20 is formed in and on the opening portion 19 and connected to the connection pad portion of the upper interconnection 17 . Although not shown, if the columnar electrodes 12 are arranged in a matrix, it is of course possible to introduce the upper interconnection 17 between the columnar electrodes 12 .

(eleventh embodiment)

Fig. 31 is a cross-sectional view of a semiconductor device according to an eleventh embodiment of the present invention. This semiconductor device is obtained by removing the second insulating material 15 by polishing in FIG. 23, as in the tenth embodiment.

(twelfth embodiment)

Fig. 32 is a sectional view of a semiconductor device according to a twelfth embodiment of the present invention. This semiconductor device is obtained by removing the second insulating material 15 by polishing in FIG. 26, as in the tenth embodiment.

(thirteenth embodiment)

In the above-described embodiments, for example, as shown in FIG. 1 , the upper interconnection 17 and the upper insulating film 18 each including one layer are formed on the second insulating material 15 . However, the present invention is not limited thereto. It is also possible to form the upper interconnection 17 and the upper insulating film 18 each including two or more layers. For example, like the thirteenth embodiment of the present invention shown in FIG. 33 , each of upper interconnection 17 and upper insulating film 18 may have two layers.

More specifically, in this semiconductor device, the first upper interconnection 51 is formed on the upper surface of the second insulating material 15 and is connected to the upper surface of the columnar electrode 12 through the opening portion 16 formed in the second insulating material 15. surface. A first upper insulating film 52 made of epoxy resin or polyimide resin is formed on the upper surface of the second insulating material 15 including the first upper interconnection 51 . The second upper interconnection 54 is formed on the upper surface of the first upper insulating film 52 and is connected to the upper surface of the connection pad portion of the first upper interconnection 51 through the opening portion 53 formed in the first upper insulating film 52 . .

A second upper insulating film 55 made of a solder resist is formed on the upper surface of the first upper insulating film 52 including the second upper interconnection 54 . The second upper insulating film 55 has an opening portion 56 at a position corresponding to the connection pad portion of the second upper interconnection 54 . The protruding electrode 20 is formed in and on the opening portion 56 and connected to the connection pad portion of the second upper interconnection 54 . In this case, only the copper foil 1 a is formed on the lower surface of the adhesive layer 4 and the first insulating material 14 .

(fourteenth embodiment)

For example, in FIG. 16 , the resulting member is cut between semiconductor members 3 adjacent to each other. However, the present invention is not limited thereto. The resulting components may be cut for every two or more semiconductor components. For example, as in the fourteenth embodiment of the present invention, as shown in FIG. 34, the resulting member is cut for every three semiconductor members 3, thereby obtaining a multi-chip module type semiconductor device. In this case, the three semiconductor components 3 may be of the same type or of different types.

In the above-described embodiments, the semiconductor member 3 and the first insulating material 14 are formed in a state in which the lower surface of the semiconductor member 3 is supported by the substrate 31 . After the second insulating material 15 is formed on the semiconductor member 3 and the first insulating material 14, the substrate 31 is removed. The substrate 31 does not remain in the completed semiconductor device. However, an organic material such as an epoxy-based material or a polyimide-based material or a thin plate formed of a thin metal film may also be used as the material of the substrate 31 . After forming the upper interconnection 17 and the upper insulating film 18, the substrate 31 is cut together with the upper insulating film 18, the second insulating material 15, and the first insulating material 14 after forming the protruding electrodes 20 as required, thereby leaving the substrate 31 As a base component of semiconductor devices. In this case, the base may be diced after forming interconnections and the like on the surface of the substrate 31 on the opposite side to the mounting surface of the semiconductor member 3 .

In the first to fourteenth embodiments described above, the semiconductor device is basically manufactured by forming an insulating film while supporting the lower surface of each semiconductor member 3 by the substrate 31 .

However, a semiconductor device can be manufactured by forming insulating films and interconnections while supporting the upper surface of each semiconductor member 3 by the substrate 31 . This method will be described in detail below.

(fifteenth embodiment)

The semiconductor device according to the fifteenth embodiment shown in FIG. 35 represents an embodiment manufactured by the latter method. Note that the purpose of this embodiment is to show that not only the structure shown in FIG. 35 can be obtained by the latter method but also a semiconductor device having one of the structures according to the first to fourteenth embodiments described above can be manufactured by the latter method. This is explained below in the appropriate steps.

The semiconductor device shown in FIG. 35 is different from the semiconductor devices of the first to fourteenth embodiments in that the lower surface of the semiconductor member 3 is directly bonded to the insulating layer 2 without interposing any adhesive layer. The insulating layer 2 is formed on the lower surface of the semiconductor member 3 by printing or spin coating, which will be described later.

A method of manufacturing a semiconductor device according to a fifteenth embodiment will be described below.

Using the steps shown in FIGS. 2-7, the interconnection 11 and the sealing film 13 are formed on the silicon substrate 5 in a wafer state so that the interconnection 11 and the sealing film 13 are flush with each other.

In this state, without forming any adhesive layer on the lower surface of the silicon substrate 5, dicing is performed, thereby obtaining a plurality of semiconductor members 3 as shown in FIG. 35, as shown in FIG.

As shown in Fig. 37, a substrate 31 is prepared. The substrate 31 has a plurality of semiconductor devices corresponding to those shown in FIG. 35 . The substrate 31 is made of metal such as aluminum, and has a rectangular planar shape, more preferably, an almost square planar shape, but the shape is not limited thereto. The substrate 31 may be made of an insulating material such as glass, ceramics, or resin.

The second insulating plate member 15 a is bonded to the entire upper surface of the substrate 31 . The second insulating plate part 15a is preferably made of aggregate material, but the present invention is not limited thereto. As the aggregation material, a thermosetting resin such as epoxy resin or BT resin mixed with silica filler and semi-cured can be used. However, as the second insulating sheet member 15a, the above-mentioned prepreg material or a material containing no filler or only a thermosetting resin may be used. The thermosetting resin is semi-set by heating and pressing, and the second insulating plate member 15 a is bonded to the entire upper surface of the substrate 31 .

The semiconductor member 3 shown in FIG. 36 is turned upside down and disposed on a plurality of predetermined positions on the upper surface of the second insulating plate member 15a in a face-down state. The semiconductor member 3 is heated and pressed to temporarily cure the thermosetting resin in the second insulating sheet 15 a so that the lower surface of the second insulating sheet 15 a is temporarily bonded to the upper surface of the substrate 31 .

Two first insulating plate members 14a and 14b each having opening portions arranged in a matrix are aligned and stacked on the upper surface of the second insulating plate member 15a between the semiconductor members 3 and disposed at the outermost position between the outside. The first insulating plate members 14a and 14b are obtained as follows. Infuse the fiberglass with a thermosetting resin such as epoxy. Thermosetting resins are semi-cured in order to prepare sheet-like prepregs. A plurality of rectangular opening portions 33 are formed in the prepreg by die-cutting or etching.

In this case, in order to obtain flatness, each of the first insulating plate members 14a and 14b must be a plate member. However, the material need not always be a prepreg material. Thermosetting resins or thermosetting resins in which reinforcing materials such as glass fibers or silica fillers are dispersed may also be used.

The size of the opening portion 33 of the first insulating plate members 14 a and 14 b is slightly larger than that of the semiconductor member 3 . For this purpose, a gap 34 is formed between the first insulating sheet parts 14 a and 14 b and the semiconductor component 3 . The length of the gap 34 is, for example, approximately 0.1-0.5 mm. The total thickness of the first insulating plate parts 14 a and 14 b is greater than the thickness of the semiconductor component 3 . The first insulating plate members 14a and 14b are thick enough to sufficiently fill the gap 34 when the first insulating plate members are heated and pressurized, which will be described later.

In this case, the first insulating plate members 14a and 14b having the same thickness are used. However, the first insulating plate parts 14a and 14b may have different thicknesses. The second insulating sheet may comprise two layers, as described above. However, one layer or three or more layers may be included. The thickness of the second insulating plate member 15a corresponds to or is slightly greater than the thickness of the second insulating material 15 to be formed on the semiconductor member 3 in FIG. 35 .

Next, the second insulating sheet member 15a and the first insulating sheet members 14a and 14b are heated and pressed by using a pair of heating/pressurizing plates 35 and 36, as shown in FIG. Thus, the molten thermosetting resin in the first insulating sheet parts 14a and 14b is pressed to fill the gap 34 between the first insulating sheet parts 14a, 14b and the semiconductor member 3, as shown in FIG. Through the subsequent cooling treatment, the thermosetting resin is cured while being bonded to the semiconductor member 3 . In this way, as shown in FIG. 38 , the second insulating material 15 made of a thermosetting resin containing a reinforcing material is formed and adhered to the upper surface of the substrate 31 . Furthermore, the semiconductor component 3 is bonded to the upper surface of the second insulating material 15 . In addition, a first insulating material 14 made of a thermosetting resin containing a reinforcing material is formed and bonded on the upper surface of the second insulating material 15 .

In this case, as shown in FIG. 36, in the wafer state, the columnar electrodes 12 in each semiconductor member 3 have a uniform height. In addition, the upper surface of the sealing film 13 including the upper surface of the columnar electrode 12 is planarized. For this reason, in the state shown in FIG. 38, the plurality of semiconductor members 3 have the same thickness.

In the state shown in FIG. 38 , heating and pressurization are performed while as a pressure limiting surface, a virtual plane higher than the upper surface of the semiconductor member 3 is defined by the diameter of the reinforcing material such as silica filler. The second insulating material 15 underneath the semiconductor component 3 acquires a thickness equal to the diameter of the reinforcing material (eg silica filler). When the open-end (open) flat press is used as a press with a pair of heating/pressurizing plates 35 and 36, the excess thermosetting resin in the insulating plate members 14a, 14b and 15a is squeezed out of the pair of heating/pressurizing plates 35 and 36.

As a result, the upper surface of the first insulating material 14 becomes flush with the upper surface of the semiconductor member 3 . The lower surface of the second insulating material 15 is flat because the surface is adjusted by the upper surface of the heating/pressurizing plate 35 on the lower side. Therefore, the polishing step of planarizing the upper surface of the first insulating material 14 and the lower surface of the second insulating material 15 does not have to be performed. Even if the substrate 31 has a relatively large size, eg, about 500×500 mm, the first and second insulating materials 14, 15 can be easily planarized at one time with respect to a plurality of semiconductor members 3 disposed on the substrate 31 .

The first and second insulating materials 14 and 15 are composed of a thermosetting resin containing reinforcing materials such as fibers or fillers. For this reason, stress due to shrinkage during curing of the thermosetting resin can be reduced compared to a structure composed only of the thermosetting resin. This also prevents the substrate 31 from warping.

In the manufacturing steps shown in FIG. 38, heating and pressurization may be performed by separate devices. That is, for example, pressurization may be performed only from the upper surface side while heating the lower surface of the semiconductor member 3 with a heater. Alternatively, heating and pressure can be performed in separate steps.

When the manufacturing steps shown in FIG. 38 are completed, the semiconductor member 3 and the first and second insulating materials 14 and 15 are integrated. They stay only as strong as needed. Next, the substrate 31 is peeled or removed by polishing or etching. This processing is performed in order to reduce the load in dicing (to be described later) and to reduce the thickness of the semiconductor device as a product.

Next, the resulting member shown in FIG. 38 in which the semiconductor member 3 and the first and second insulating materials 14, 15 are integrated is turned upside down and placed in a face-up state. As shown in FIG. 39, an opening portion 16 is formed in the second insulating material 15 at a position corresponding to the central portion of the upper surface of the columnar electrode 12 by laser machining in which the second insulating material 15 is irradiated with a laser beam. Then, epoxy oil stains generated in the opening portion 16 are removed by degreasing treatment as required.

As shown in FIG. 40 , upper interconnection forming layer 17 a is formed on the entire upper surface of second insulating material 15 including the upper surface of columnar electrode 12 exposed through opening portion 16 . In this case, the upper interconnection forming layer 17a includes a lower metal layer formed of, for example, a copper layer formed by electroless plating, and an upper metal layer formed on the surface of the lower metal layer. The upper metal layer is formed by performing copper electroplating using the lower metal layer as a plating current path.

When the upper interconnection forming layer 17a is patterned by photolithography, an upper interconnection 17 is formed at a predetermined position on the upper surface of the second insulating material 15, as shown in FIG. 41 . In this state, upper interconnection 17 is connected to the upper surface of columnar electrode 12 through opening portion 16 in second insulating material 15 .

As shown in FIG. 42, upper insulating film 18 made of solder resist is formed on the entire upper surface of second insulating material 15 including upper interconnection 17 by screen printing or spin coating. In this case, upper insulating film 18 has opening portion 19 at a position corresponding to the connection pad portion of upper interconnection 17 . Furthermore, insulating layer 2 made of solder resist is formed on silicon substrate 5 and the lower surface of first insulating material 14 by printing or spin coating. Subsequently, the protruding electrode 20 is formed in and on the opening portion 19 and connected to the connection pad portion of the upper interconnection 17 .

As shown in FIG. 43, when the upper insulating film 18, the first and second insulating materials 14 and 15, and the insulating layer 2 are cut between adjacent semiconductor members 3, a semiconductor device as shown in FIG. 35 is obtained.

In the semiconductor device thus obtained, the upper interconnection 17 to be connected to the stud-on electrode 12 of the semiconductor member 3 is formed by electroless plating (or sputtering) and electroplating. For this reason, electrical connection between each upper interconnection 17 and the corresponding columnar electrode 12 of the semiconductor component 3 can be reliably ensured. In the state shown in FIG. 41, when the insulating layer 2 with the metal layer 1 is bonded with an adhesive layer, instead of forming the insulating layer 2 on the lower surface of the silicon substrate 5 and the first insulating material 14, the result shown in FIG. 1 shows the semiconductor device according to the first embodiment. It should be fully understood that the semiconductor device according to any one of the second to fourteenth embodiments other than the first embodiment is also available, although specific description is omitted.

In the above-described manufacturing method, the plurality of semiconductor members 3 are provided on the second insulating plate member 15 a on the substrate 31 . For a plurality of semiconductor members 3, the first and second insulating materials 14 and 15 may be formed at one time. After that, the substrate 31 is removed. Then, for a plurality of semiconductor members 3 , upper interconnection 17 , upper insulating film 18 , and protruding electrode 20 are formed at one time. After that, the semiconductor member is separated, thereby obtaining a plurality of semiconductor devices. Therefore, the manufacturing steps can be simplified.

Furthermore, as seen from the manufacturing steps shown in FIG. 38, even if the substrate 31 is removed, a plurality of semiconductor members 3 can be conveyed together with the first and second insulating materials 14 and 15. This also simplifies the manufacturing steps. Furthermore, in the above-described manufacturing method, as shown in FIG. 37, the semiconductor member 3 is bonded to the substrate 31 via the second insulating plate member 15a. Therefore, no process for forming a bond difference is required. When removing the substrate 31, only the substrate 31 has to be removed. This also simplifies the manufacturing steps.

In the above-described manufacturing method, the protruding electrodes 20 are arranged in a matrix and correspond to the entire surface of the semiconductor member 3 and the first insulating material 14 around it. However, the protruding electrode 20 may be provided only on an area of the first insulating material 14 corresponding to the periphery of the semiconductor member 3 . The protruding electrodes 20 may not all surround the semiconductor member 3 but only surround one to three sides among the four sides of the semiconductor member 3 . In this case, the first insulating material 14 does not have to have a rectangular frame shape and may be provided only on one side where the protruding electrode 20 is to be formed.

(Sixteenth embodiment)

Fig. 44 is a cross-sectional view of a semiconductor device according to a sixteenth embodiment of the present invention. This semiconductor device differs from the semiconductor device shown in FIG. 35 in that it does not have the insulating layer 2 .

In the manufacture of the semiconductor device according to the sixteenth embodiment, in the manufacturing steps shown in FIG. 42 , insulating layer 2 is not formed on silicon substrate 5 and the lower surface of first insulating material 14 . After the protruding electrodes 20 are formed, the upper insulating film 18 , and the first and second insulating materials 14 and 15 are cut between adjacent semiconductor members 3 . Thus, a plurality of semiconductor devices shown in Fig. 44 were obtained. The semiconductor device thus obtained can be very thin since it has no insulating layer 2.

(seventeenth embodiment)

Fig. 45 is a cross-sectional view of a semiconductor device according to a seventeenth embodiment of the present invention. Such a semiconductor device can be obtained by, for example, properly polishing the silicon substrate 5 and the lower surface side of the first insulating material 14 in the state shown in FIG. insulating film 18 and first and second insulating materials 14 and 15 . The semiconductor device thus obtained can be thinner.

Before the protruding electrodes 20 are formed, the insulating layer 2 may be removed by polishing or etching (if necessary, the silicon substrate 5 and the lower surface side of the first insulating material 14 may be properly polished). Then, the protruding electrodes 20 may be formed, and the upper insulating film 18 and the first insulating material 14 may be cut between adjacent semiconductor members 3 .

(eighteenth embodiment)

Fig. 46 is a sectional view of a semiconductor device according to an eighteenth embodiment of the present invention. This semiconductor device is different from the semiconductor device shown in FIG. 35 in that the second insulating material 15A is provided on the upper surface of the semiconductor member 3, and the first insulating material 14A is provided on the insulating layer surrounding the semiconductor member 3 and the second insulating material 15A. on the upper surface of layer 2.

In the manufacture of the semiconductor device according to the eighteenth embodiment, after the manufacturing step shown in FIG. , as shown in Figure 47.

Next, as shown in FIG. 48 , a cutting step is performed, thereby obtaining a plurality of semiconductor members 3 . However, in this case, the first insulating plate member 15A is bonded to the upper surface of the sealing film 13 including the upper surface of the semiconductor member 3 . The semiconductor member 3 thus obtained has a plate-shaped first insulating plate member 15A on its upper surface. Therefore, a very troublesome operation for adhering the first insulating sheet 15A to the upper surface of each semiconductor member 3 after the cutting step is not required.

As shown in FIG. 49, the semiconductor member 3 shown in FIG. 48 is turned upside down and set in a state of facing downward, so that the first insulating sheet member 15A bonded to the lower surface of the semiconductor member 3 is formed by using a first insulating sheet of appropriate viscosity. The member 15A is bonded to a plurality of predetermined positions on the upper surface of the substrate 31 . Heat and pressure are applied to temporarily cure the thermosetting resin in the first insulating plate member 15A so that the lower surface of the first insulating plate member 15A is temporarily bonded to the upper surface of the substrate 31 . In addition, the lower surface of the semiconductor member 3 is temporarily bonded to the upper surface of the first insulating plate member 15A. The two first insulating plate pieces 14 a and 14 b each having an opening portion 33 are aligned and stacked on the upper surface of the substrate 31 between the semiconductor components 3 and between the outside of the semiconductor component 3 disposed at the outermost position.

Also in this case, the size of the opening portion 33 of the first insulating plate members 14 a and 14 b is slightly larger than that of the semiconductor member 3 . To this end, a gap 34 is formed between the first insulating plate parts 14 a and 14 b and the semiconductor member 3 including the first insulating plate part 15A. The length of the gap 34 is, for example, approximately 0.1-0.5 mm. The total thickness of the first insulating plate parts 14a and 14b is greater than the thickness of the semiconductor member 3 including the first insulating plate part 15A. The first insulating sheet members 14a and 14b are thick enough to sufficiently fill the gap 34 when the first insulating sheet members are heated and pressed, as will be described later.

Next, the first insulating sheet member 15A and the first insulating sheet members 14 a and 14 b are heated and pressed using a pair of heating/pressurizing plates 35 and 36 , as shown in FIG. 50 . Thus, the molten thermosetting resin in the first insulating sheet parts 14a and 14b is squeezed to fill the gap 34 between the first insulating sheet parts 14a, 14b and the semiconductor member 3 including the first insulating sheet part 15A, as shown in FIG. 49. Through the subsequent cooling process, the thermosetting resin is cured while being bonded to the semiconductor member 3 and the substrate 31 therebetween.

In this way, as shown in FIG. 50 , second insulating material 15A made of thermosetting resin containing reinforcing material is formed and bonded to a plurality of predetermined positions on the upper surface of substrate 31 . Furthermore, the semiconductor member 3 is bonded onto the upper surface of the second insulating material 15A. Further, a first insulating material 14 composed of a thermosetting resin containing a reinforcing material is formed and adhered to the upper surface of the substrate 31 between the semiconductor member 3 and the outside of the semiconductor member located at the outermost position. Using the same manufacturing steps as in the fifteenth embodiment, the semiconductor device shown in Fig. 46 is obtained.

In the above-described embodiments, the semiconductor member 3 has the interconnection 11 and the columnar electrode 12 as external connection electrodes in addition to the connection pads 6 . The present invention can also be applied to a semiconductor member 3 which has only the connection pad 6 as an external connection electrode or the connection pad 6 and the interconnection 11 having the connection pad portion.

As has been described above, according to the present invention, at least some of the connection pad portions of the uppermost upper interconnection are provided on the first insulating material formed on one side of the semiconductor member. For this reason, even if the number of connection pad portions of the uppermost upper interconnection increases, the required size and pitch can be secured.

Claims (45)

1, a kind of semiconductor device, its spy just is being to comprise:

At least one semiconductor component (3) has a Semiconductor substrate (5) and is formed on a plurality of external connecting electrodes (6) on the Semiconductor substrate;

Be arranged on insulation plate on semiconductor component (3) one sides (14,14A); With

A plurality of upper interconnect (17,54) with a plurality of connection pads part, wherein connection pads partly is arranged on insulation plate (14,14A) and goes up and corresponding upper interconnect, and is electrically connected to the external connecting electrode (6) of semiconductor component (3).

2, semiconductor device according to claim 1 is characterized in that comprising a plurality of semiconductor components (3).

3, semiconductor device according to claim 1 is characterized in that semiconductor component (3) comprises at least one connection pads (6), is connected to the column external connecting electrode (12) of connection pads (6) and is formed on external connecting electrode (12) diaphragm seal (13) on every side.

4, semiconductor device according to claim 1, the plate that it is characterized in that insulating (14,14A) is mainly by making by the material for preparing with the thermosetting resin impregnation of fibers.

5, semiconductor device according to claim 1 is characterized in that insulating material (15) is formed between insulation plate (14) and the upper interconnect (17) and insulate between plate (14) and the semiconductor component (3).

6, semiconductor device according to claim 5 is characterized in that insulating material (15,15A) is a plate.

7, semiconductor device according to claim 5 is characterized in that the upper surface of insulating material (15,15A) is smooth.

8, semiconductor device according to claim 1 is characterized in that also comprising top dielectric film (18,52), covers the connection pads part part in addition of upper interconnect (17,54).

9, semiconductor device according to claim 8 is characterized in that solder ball (20) is formed on each connection pads part of upper interconnect (17,54).

10, semiconductor device according to claim 1 is characterized in that metal level (1,1a) is formed on the lower surface of semiconductor component (3) and insulation plate (14,14A).

11, semiconductor device according to claim 10 is characterized in that insulating barrier (2) is formed on the lower surface of metal level (1).

12, semiconductor device according to claim 10 is characterized in that metal level (1,1a) has metal forming at least.

13, semiconductor device according to claim 12 is characterized in that metal forming is a Copper Foil.

14, semiconductor device according to claim 1, it is characterized in that lower interconnect (41) is formed on the lower surface at least of insulation plate (14,14A), and upper interconnect (17) and lower interconnect (41) are connected by the vertical electrical connections (43) that is formed in the plate (14) that insulate.

15, semiconductor device according to claim 1, the plate (14) that it is characterized in that insulating has the sandwich construction of a plurality of insulation plates (14a, 14b).

16, semiconductor device according to claim 1 is characterized in that insulating material (15A) is formed between insulating element (14A) and the upper interconnect (17), and the upper surface of insulation plate (14A) and the upper surface flush of insulating material (15A).

17, a kind of method, semi-conductor device manufacturing method comprises:

A plurality of semiconductor components (3) are set on substrate (31), wherein each semiconductor component has a Semiconductor substrate (5) and a plurality of connection pads (6), simultaneously semiconductor component is separated from each other and the insulation plate (14) that at least one has opening portion (33) is set on the position of corresponding semiconductor component (3);

From the upside heating and the pressurization insulation plate (14) of insulation plate (14), thereby the plate (14) that will insulate melts and is solidificated between the semiconductor component;

Form one deck upper interconnect (17,54) at least, this upper interconnect has connection pads part and is connected on corresponding of a plurality of connection pads (6) of one of a plurality of semiconductor components (3), so that to should connection pads partly being placed on the insulation plate (14) upper interconnect; With

Cutting insulation plate (14) between semiconductor component (3), thus a plurality of semiconductor device obtained, and wherein the connection pads of upper interconnect (17,54) partly is arranged on the insulation plate (14).

18, method, semi-conductor device manufacturing method according to claim 17 is characterized in that semiconductor component (3) comprises connection pads (6), is connected to the column external connecting electrode (12) of connection pads (6) and is formed on external connecting electrode (12) diaphragm seal (13) on every side.

19, method, semi-conductor device manufacturing method according to claim 17 is characterized in that insulation plate (14) is cut into and makes each semiconductor device comprise a plurality of semiconductor components (3) when cutting insulation plate (14).

20, method, semi-conductor device manufacturing method according to claim 17 is characterized in that removing substrate (31) at cutting insulation plate (14) before.

21, method, semi-conductor device manufacturing method according to claim 17 is characterized in that cutting insulated substrate (14) afterwards, removes substrate (31).

22, method, semi-conductor device manufacturing method according to claim 17 is characterized in that carrying out being provided with when heat/pressure is handled the pressure limit surface.

23, method, semi-conductor device manufacturing method according to claim 17, the size that the size of the opening portion (33) of plate (14) that it is characterized in that insulating is a bit larger tham semiconductor component (3).

24, method, semi-conductor device manufacturing method according to claim 23 is characterized in that being arranged on the thickness of the thickness of the insulation plate (14) on the substrate (31) greater than semiconductor component (3).

25, method, semi-conductor device manufacturing method according to claim 17, the plate (14) that it is characterized in that insulating are mainly by constituting by the material for preparing with the thermosetting resin impregnation of fibers.

26, method, semi-conductor device manufacturing method according to claim 17 is characterized in that also being included in the step that forms insulating material (15) between (14) and the upper interconnect (17).

27, method, semi-conductor device manufacturing method according to claim 26 is characterized in that insulating material (15) is a plate.

28, method, semi-conductor device manufacturing method according to claim 17 is characterized in that also being included in and semiconductor component (3) and insulation plate (14) is set before on the substrate (31), goes up the film (1a) that formation will be removed from substrate (31) at substrate (31).

29, method, semi-conductor device manufacturing method according to claim 28 is characterized in that film (1a) mainly is made of metal.

30, method, semi-conductor device manufacturing method according to claim 28 is characterized in that cutting film (1a) with insulation plate (14) when cutting insulation plate (14).

31, method, semi-conductor device manufacturing method according to claim 28 is characterized in that being provided with semiconductor component (3) and insulation plate (14) afterwards on film (1a), make the temporary transient curing of insulation plate (14).

32, method, semi-conductor device manufacturing method according to claim 31 is characterized in that removing substrate (31) after temporary transient curing.

33, method, semi-conductor device manufacturing method according to claim 28 is characterized in that removing substrate (31) afterwards, goes up at film (1a) and forms another film (1b, 2).

34, method, semi-conductor device manufacturing method according to claim 28 is characterized in that film (1a) is a metal forming, and described another film (1b) is a metal forming.

35, method, semi-conductor device manufacturing method according to claim 28 is characterized in that described another film (2) mainly made by insulating material.

36, a kind of method, semi-conductor device manufacturing method is characterized in that described another film (1b, 2) is to form by piling up a plurality of layers of being made by different materials.

37, method, semi-conductor device manufacturing method according to claim 33 is characterized in that when cutting insulation plate (14), cutting insulation plate (14), film (1a) and described another film (1b, 2).

38, method, semi-conductor device manufacturing method according to claim 17 is characterized in that when cutting insulation plate, cutting insulation plate (14), and while cutting substrate (31) is so that semiconductor device has substrate (31).

39, method, semi-conductor device manufacturing method according to claim 17 is characterized in that also comprising the step that forms top dielectric film (18,55), and this top dielectric film (18,55) covers the connection pads part part in addition of upper interconnect (17,54).

40,, it is characterized in that the connection pads that also is included in upper interconnect (17,54) partly goes up the step that forms solder ball (20) according to the described method, semi-conductor device manufacturing method of claim 39.

41, method, semi-conductor device manufacturing method according to claim 17, it is characterized in that also being included in formation through hole (42) in the insulation plate (14), form lower interconnect (41) and form vertical electrical connections (43) on the lower surface of insulation plate (14) in through hole (42), wherein vertical electrical connections (43) connects upper interconnect (17) and lower interconnect (41).

42,, it is characterized in that removing substrate forming through hole (42), lower interconnect (41) and vertical electrical connections (43) before according to the described method, semi-conductor device manufacturing method of claim 41.

43, method, semi-conductor device manufacturing method according to claim 17, it is characterized in that this method also is included in substrate (31) and goes up formation top dielectric film (15a), and semiconductor component (3) is arranged on the top dielectric film (15a), form one and top dielectric film (15a) facing surfaces simultaneously, on this surface, form described connection pads.

44,, it is characterized in that semiconductor component (3) comprises connection pads (6), is connected to the column external connecting electrode (12) of connection pads (6) and is formed on external connecting electrode (12) diaphragm seal (13) on every side according to the described method, semi-conductor device manufacturing method of claim 43.

45,, it is characterized in that insulating element (14) is arranged on the top dielectric film (15a) according to the described method, semi-conductor device manufacturing method of claim 43.

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