CN1697595A - Ball Grid Array Package Substrate Structure - Google Patents

Abstract

A through hole configuration method for chip connection region on signal layer of ball grid array package substrate comprises: a metal ball grid pad array composed of a plurality of metal ball grid pads; and a through hole array composed of a plurality of through holes and arranged in a staggered way with the metal ball grid array. Wherein, the outermost periphery of the through hole array comprises at least two through hole rings for transmitting signals or connecting power supply to the chip. And two adjacent through holes on each through hole ring are separated by the distance of at least two metal ball grid pads. Therefore, the corresponding grounding layer is provided with a plurality of heat dissipation channels, so that heat energy generated during the operation of the semiconductor chip can be quickly conducted out through the heat dissipation channels, and the transmission of signal quality and power quality is facilitated.

Description

Ball Grid Array Package Substrate Structure

technical field

The invention relates to a ball grid array packaging substrate, especially a ball grid array packaging substrate with heat dissipation planning.

Background technique

There are various types of semiconductor packages, and the advent of Ball Grid Array (BGA) semiconductor packages can provide high-density electronic components (Electronic Components) and electronic circuits (Electronic Circuits) A sufficient number of input/output connections (I/O Connections) has become the mainstream of packaged products. Due to the continuous evolution of process technology, the number and density of solder balls arranged in a matrix to connect input/output terminals on BGA semiconductor packages have been greatly increased. Typical BGA semiconductor packages often have millions of active and passive components. source element.

However, as the functions of chips made by semiconductor integrated circuits continue to grow, the density of components per unit area increases rapidly. In order to accommodate more components, it is conceivable that the line width must continue to shrink, which will lead to an increase in impedance. Heat generated during operation It is quite considerable, if the heat energy generated by the operation of the chip cannot be effectively released, the reliability and service life of the semiconductor chip will be significantly affected.

The ball grid array package substrate of the prior art is shown in Figure 1. In order to reduce mutual interference during signal transmission, usually the design of each conductor pattern layer of the multilayer board also integrates the relevant signal layer (signal plane layer) 2 and ground layer (ground layer) plane layer) 4 and power plane layer (power plane layer) 6 are separated, and the conductor pattern layer or wire layer is separated by insulating layer materials 8 and 10, such as glass fiber, FR4, epoxy resin, etc., and the signal layer contains a The chip landing area 14 (shown in FIG. 2 ) is used to provide the ball grid array package chip landing.

Generally speaking, the through holes in the chip connection area 14 are arranged in an array. Please refer to FIG. 2 , which is a layout diagram of the ground plane of the BGA package substrate. In the substrate wiring design, at least the outermost through holes where the chip landing area 14 is located are mainly designed to transmit signals and connect power supplies, and are not connected to the ground layer, while the inside of the chip landing area 14 is used as a power supply or The signal connection for grounding, which will be formed in the ground layer of the substrate, and the outermost ring of through holes around the chip landing area 14 must be made into discarded holes 12 (electrically not connected), because the through holes are treated when they are insulated In the process, there will be some errors when etching the copper foil around the through-holes. In the current situation where the through-holes are too densely arranged, it is easy to cause the adjacent copper foils to be etched together, resulting in chip contact areas. The inner and outer parts are separated by abandoned holes, so that the heat dissipation path becomes broken or even cut off.

And because the lines in the chip connecting area are very dense, a lot of heat will be generated during the operation of the chip, but because of its heat dissipation path to the outside, it is equivalent to being blocked by the abandoned holes in the outermost circle of the chip connecting area, so that Heat energy cannot be quickly dissipated laterally through the ground layer, which can easily cause damage to components. The densely arranged multiple abandoned holes 12 will also reduce the relatively effective GND signal loop area (channel) of the chip, which affects signal quality (especially high-speed signals).

As shown in FIG. 3 , the positions of the through holes thereon correspond to the positions of the through holes in the ground layer of the BGA package substrate in FIG. 2 . Since the through holes in the outermost circle of the chip landing area 14 are mainly designed to transmit signals and connect power supplies, most of the discarded holes 12 densely arranged in the outermost circle of the chip landing area in Figure 2 are shown in Figure 3 Conductive holes for electrical connection.

Contents of the invention

The present invention provides a method for disposing through holes in the chip contacting area of a ball grid array package substrate, which is used to improve the heat dissipation of the semiconductor chip on the substrate, and to improve the signal quality and power quality of the semiconductor chip during operation without increasing any cost. The effective utilization rate of the ball grid array package substrate can be improved.

The through-hole configuration method of the chip connection area on the signal layer of the ball grid array package substrate of the present invention includes: a metal ball grid pad array, which is composed of a plurality of metal ball grid pads; and a through-hole array, which is composed of a plurality of the through-holes And it is alternately arranged with the metal ball grid array. The outermost periphery of the through-hole array includes at least two through-hole rings for transmitting signals or connecting power to the chip. And wherein two adjacent through-holes on each through-hole ring are separated by at least two distances of the metal ball grid pads.

The arrangement of the through holes in the chip connection area on the ground layer of the ball grid array package substrate of the present invention includes: a conductive hole array, which is composed of a plurality of conductive holes; at least two predetermined position circles of the through holes are located on the periphery of the conductive hole array, wherein Each circle of predetermined positions of the through holes contains a plurality of abandoned holes. Wherein each of the predetermined position circle of the through hole is spaced apart by at least one distance between the two adjacent discarded holes.

In the manufacturing process of the ball grid array package substrate, the present invention first plans the position of the through hole, so that it has multiple heat dissipation channels and increases the heat dissipation space, so as to help the heat energy generated during the operation of the semiconductor chip to be quickly conducted through the channels. , It also contributes to the transmission of signal quality and power quality.

Description of drawings

1 is a schematic cross-sectional view of a ball grid array package substrate;

2 is a layout diagram of a ground layer of a ball grid array package substrate in the prior art;

3 is a layout diagram of a power supply layer of a ball grid array package substrate in the prior art;

FIG. 4 is a layout diagram of a chip connection area of a signal layer of a ball grid array package substrate according to an embodiment of the present invention;

5 is a layout diagram of a ground layer of a ball grid array package substrate according to an embodiment of the present invention;

6 is a layout diagram of a power supply layer of a ball grid array package substrate according to an embodiment of the present invention; and

FIG. 7 is a layout diagram of a ground layer of a ball grid array package substrate according to another embodiment of the present invention.

Explanation of reference signs

2 signal layer 4 ground layer

6 power layer 22 through-hole array

24 Metal Ball Grid Pad Array 44+ Channels

More than 12 abandoned holes (electrically disconnected)

More than 38 conductive holes

40, 42 Predetermined position rings for through holes

8, 10 Dielectric layer 14, 34 Chip placement area

16, 36 metal layers

22a, 22b through hole position

Detailed ways

In view of the disadvantages of the prior art, the method provided by the present invention adjusts the arrangement of the through holes in the chip mounting area to improve the heat dissipation circuit, thereby effectively solving the above problems.

The first embodiment of the present invention is a chip landing area in a signal layer of a ball grid array package substrate. As shown in FIG. 4 , the chip connection area 34 includes a through hole array 22 and a metal ball grid pad array 24 , wherein the metal ball grid pad array is staggered with displacement (1/2u, 1/2v) relative to the through hole array. In the first embodiment of the present invention, the outermost two circles of the through-hole array 22 are the adjacent through-holes of the outermost circle of the through-hole array where the chip mounting area 34 is located, and are displaced in terms of the lower part of FIG. 4 ( 1u, 1v) or (-1u, 1v). That is, the adjacent through-hole positions 22a are moved to the outside of the outermost circle, forming the arrangement relationship of the through-hole positions 22b as shown in FIG. 4 .

In the present invention, the outermost circle of the through-hole array includes at least two through-hole circles for transmitting signals or connecting power. And wherein, two adjacent through-holes on the through-hole circle for transmitting signals or connecting power are separated by at least two metal ball grid pads. In addition, the remaining through-holes on the through-hole array are used for grounding or power supply. The signal transmission between the chip and the substrate is electrically connected to the conductive pattern of the power layer, the ground layer, and the conductive pattern outside the chip connection area of the signal layer by filling the through hole with conductive material, which is called a conductive hole.

Please refer to FIG. 5 , which is a layout diagram of the ground layer of the BGA package substrate according to an embodiment of the present invention. In Fig. 5, a chip connection area 34 corresponding to the upper signal layer is arranged in the metal layer 36 in the center of the ground layer to be electrically connected to a chip; due to the outermost two circles of the chip connection area on the signal layer If the arrangement of the through-holes is changed as described above, the arrangement of the outermost two circles of through-holes on the ground layer on the substrate will also be changed correspondingly. Abandoned holes are formed on the through hole predetermined position circles 40 and 42 of the chip connection area 34 .

Therefore, the outermost circle of the chip landing area on the ground layer includes at least two circles of predetermined positions of through holes corresponding to the through hole circles of the chip landing area on the signal layer. And the distance between two adjacent discarded holes on the predetermined position circle of each through hole is at least the distance of one conductive hole, so that a plurality of channels 44 can be formed to provide the heat dissipation space of the ground layer. As shown in FIG. 5 , in the first embodiment of the present invention, the discarded holes on one predetermined position circle of through holes on the ground layer are arranged in parallel with the discarded holes on the other predetermined position circle of through holes.

Due to the change of the coordination mode of the outermost two circles of through-holes in the chip-connecting area, the heat dissipation circuit that was originally blocked by dense abandoned holes in the prior art and becomes broken or even cut off will be effectively improved. Most of the heat in the contact area can quickly achieve the effect of lateral heat dissipation through the multiple channels 44, and the problem of heat accumulation and affecting its reliability can be solved. Another effect of the plurality of channels 44 is to increase the loop area, reduce the possibility of being blocked by the abandoned holes during signal transmission, and improve signal quality, especially high-speed signals.

Certainly, when the arrangement of the outermost two circles of through holes in the chip connection area on the signal layer has been changed as described above, the arrangement of the outermost two circles of through holes on the power layer on the substrate will also be correspondingly changed. Please refer to FIG. 6 , which is a layout diagram of the power layer of the BGA package substrate. Since the outermost two circles of through holes in the chip connection area 34 are preset to transmit signals and connect power sources, most of the discarded holes arranged in shifts in FIG. 5 are electrically connected in FIG. 6 Conductive hole.

As shown in FIG. 7 , the second embodiment of the present invention is a ground layer of the BGA package substrate. In the center of the ground layer, a chip connection area 34 corresponding to the upper signal layer is disposed in the metal layer 36 for electrically connecting to a chip. In the middle of the chip connecting area 34 is a conduction hole array 38 including a plurality of conduction holes, and the outermost circle includes at least two through hole predetermined position circles 40 and 42 corresponding to the through hole circle of the signal layer. Among them, the abandoned holes on the predetermined positions 40 and 42 of the through holes are arranged in the manner shown in FIG. Purpose. The distance between two adjacent abandoned holes on the predetermined position circle of each through hole is at least the distance of one conductive hole.

According to the first embodiment and the second embodiment of the present invention, similarly, the discarded holes on different through-hole circles in the ground layer may be partially arranged in parallel, and partially arranged in a zigzag shape.

The above is only a preferred embodiment of the ball grid array semiconductor package structure with planned arrangement of guide hole positions of the present invention, and it is not intended to limit the scope of the present invention. Anyone skilled in the art will not violate the spirit of the present invention. All modifications made should belong to the scope of the present invention, so the protection scope of the present invention should be based on the appended claims.

Claims (10)

1. A through-hole arrangement structure in a chip connection area on a signal layer, wherein the chip connection area is used to electrically connect a chip, and the structure includes: a metal ball grid pad array consisting of a plurality of metal ball grid pads; and a through-hole array, which is alternately arranged with the metal ball grid array, and is composed of a plurality of through-holes, Wherein the outermost periphery of the through-hole array has a first through-hole ring and a second through-hole ring for transmitting signals or connecting power to the chip. 2. The through-hole arrangement structure of claim 1, wherein the two adjacent through-holes on the first and second through-hole circles are separated by at least two distances of the metal ball grid pad. 3. The arrangement structure of through holes according to claim 1, wherein the through holes on the first through hole ring and the through holes on the second through hole circle are parallel and symmetrical to each other. 4. The arrangement structure of through holes according to claim 1, wherein the through holes on the first through hole circle and the through holes on the second through holes form an approximately zigzag arrangement. 5. The arrangement structure of through-holes according to claim 1, wherein the through-holes on the first through-hole ring and the through-holes on the second through-holes are partially arranged in parallel and partially arranged in a staggered manner. 6. A through-hole arrangement structure in a chip landing area on a ground layer, wherein the chip landing area is used to electrically connect a chip, and the structure includes: A conductive hole array, consisting of a plurality of conductive holes; A first through-hole predetermined position ring, located on the periphery of the conductive hole array, including a plurality of first abandoned holes; and A second through-hole predetermined position circle is located on the periphery of the first through-hole predetermined position circle, and includes a plurality of second discarded holes. 7 . The arrangement structure of through-holes in chip landing area on ground layer as claimed in claim 6 , wherein the two adjacent discarded holes on the predetermined position circle of the first and the second through-holes are separated by at least one distance of the conductive hole. 8 . 8. The arrangement structure of through-holes in the chip landing area on the ground layer according to claim 6, wherein the first ditch hole on the first through-hole predetermined position circle and the second through-hole predetermined position circle are mutually mutually parallel arrangement. 9. The arrangement structure of through-holes in the chip landing area on the ground layer as claimed in claim 6, wherein the first ditch holes on the first through-hole predetermined position circle are interlaced with the second through-hole predetermined position circles Arranged to form an approximate zigzag arrangement to serve as a heat dissipation space. 10. The arrangement structure of through-holes in the chip landing area on the ground layer according to claim 6, wherein the abandoned holes on different predetermined positions of the through-holes are partially arranged in parallel and partially arranged in a staggered manner.

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