CN1672128A - Method and apparatus for accessing multiple vector elements in parallel - Google Patents

Abstract

Vector processing is a suitable technique for processing applications with a large computational demand. Vector processors provide high-level operations that work on vectors (i.e., linear arrays of numbers). Vector operations can be made faster than sequences of scalar operations on the same number or data item. A typical application in which vector processing can be used is in the field of audio and video processing. Vector memory systems have a large data width, which allows a complete vector of data elements to be retrieved in one memory access using a single memory address. These data elements can then be processed in parallel. However, when using a vector memory system, problems of vector alignment and ordering of a set of vector elements may occur. The present invention provides an improved method for vector alignment and ordering of vector elements in a computer system comprising a Processor (PROC) and a multi-port memory (MEM), which results in better performance. The first step includes passing the base memory address to an Address Configuration Unit (ACU). Next, a set of memory addresses is defined by an Address Configuration Unit (ACU) using a base memory address and configuration instructions for configuring the address configuration unit. Finally, the vector is transmitted to or from the multi-port memory (MEM) using the set of memory addresses.

Description

Method and apparatus for accessing multiple vector elements in parallel

technical field

The invention relates to a computer system comprising:

processor;

A multi-port memory that is accessible by the processor.

The invention further relates to a method for transferring vectors in said computer system.

Furthermore, the invention relates to a computer program for implementing said method.

Background technique

Vector processing is a suitable technique for processing applications with heavy computational demands. Vector processors provide high-level operations that work on vectors, that is, linear arrays of numbers. A vector processor pipelines operations on individual elements of a vector. Pipelining includes not only arithmetic operations, but also memory accesses and effective address calculations. Additionally, most high-end vector processors allow multiple operations to be performed simultaneously, creating parallelism between operations on different elements. Vector instructions have several important properties. First, the computation of each result is independent of the computation of previous results, which allows for very deep pipelines without any data hazards. Second, vector instructions are equivalent to executing an entire loop, which reduces instruction bandwidth requirements. Third, memory access overhead is reduced because the complete vector is retrieved in a single access rather than data elements. This allows vector operations to be faster than sequences of scalar operations on the same number or data item. A typical application where vector processing can be used is the field of audio and video processing.

Vector memory systems have a large data width, which allows a complete vector of data elements to be retrieved with a single memory address in one memory access. These data elements can then be processed in parallel. However, several problems can occur when retrieving data from a vector memory system. First, the problem of vector alignment is related to reading data from a vector memory system that straddles a vector boundary. In that case, it is possible to retrieve data by requesting the contents of two memory addresses (ie, two vectors), and then transfer the requested data to the new vector. Second, problems arise when a set of vector elements is required in a different order than the order in which they were stored. In case vectors are required to have ordered groups of elements stored in different vectors, the contents of these vectors must be retrieved, requiring at least two memory accesses followed by selection of the appropriate data elements. US Patent 5,933,650 describes a method for alignment and ordering of vector elements. In the alignment of vector elements, one vector is loaded from memory location into a first register and the other vector is loaded from memory location into a second register. Determines the starting byte of the first byte of the specified aligned vector. Next, a vector is extracted from the first register and the second register, starting from the first bit in the first byte of the first register, successively through the bits in the second register. Finally, the extracted vector is copied into a third register so that the third register contains elements aligned for vector processing. In the order of the vector elements, the first vector is loaded from the memory location into the first register, and the second vector is loaded from the memory location into the second register. Then, a subset of elements is selected from the first register and the second register. The elements from the subset are then copied into the elements in the third register in a particular order suitable for subsequent vector processing.

The disadvantage of the alignment and sorting method of vector elements in the prior art is that more than one read access to the vector memory system is required, which increases the overhead of obtaining vector data. Furthermore, additional hardware is required, eg for temporary storage of vectors from which elements have to be selected for vector alignment or vector sorting.

Contents of the invention

It is an object of the present invention to provide an improved method for vector alignment and vector element ordering, which results in better performance of the vector processor.

This object is achieved with a method for transmitting vectors, characterized in that said method comprises the following steps:

passing the memory base address to the address configuration means;

defining a set of memory addresses by means of address configuration means using a memory base address and configuration instructions for configuring the address configuration means;

The set of memory addresses is used to transfer vectors to/from the multi-port memory.

The method allows a complete vector to be transferred to or from a multi-ported memory with a single memory base address. Being able to transfer data elements of a vector to or from any location in memory increases flexibility and avoids problems related to vector alignment and vector element ordering. Furthermore, the use of a multi-port memory in combination with the address configuration means reduces the instruction width. A complete vector can be transferred with a single memory base address, however every memory address used by a multi-ported memory should be present in the instruction. For certain types of processors, such as very large instruction word processors, code size reduction is an important issue.

According to the present invention, a computer system is characterized in that the computer system further comprises address configuration means, wherein the address configuration means is designed to define a set of memory addresses, and wherein said multi-port memory is designed to use the set of memory addresses. Complete vectors can be transferred to and from the multi-ported memory with one memory base address, which reduces memory overhead and improves computer system performance.

Preferred embodiments of the invention are defined in the dependent claims. A computer program for implementing the method for transmitting vectors according to the invention is defined in claim 8 .

An embodiment of the computer system according to the invention is characterized in that:

The address configuration device includes: a plurality of register files configured by configuration instructions, and a plurality of address calculation units for calculating memory address groups;

The register file is accessible by an address calculation unit;

The address calculation unit is coupled to a multi-port memory.

The configuration command configures a plurality of register files, and these register files can save this configuration until the next configuration command is executed. In between, this configuration can be used repeatedly, for example during a cycle of executing instructions.

An embodiment of the computer system according to the invention is characterized in that the configuration instruction comprises a set of offsets each combined with a memory base address defining the second memory address. The offset group can be directly loaded into multiple register files and used by multiple address calculation units, which improves the performance of the address configuration device.

Description of drawings

The features of the described embodiments will be further clarified and described with reference to the accompanying drawings:

Fig. 1 shows a schematic diagram of a computer system according to the present invention.

Figure 2 shows a schematic diagram of a memory system with multi-port memory and address configuration means.

Detailed ways

Fig. 1 shows a block diagram of a computer system comprising a processor PROC, an address configuration unit ACU, a multi-port memory MEM and a system bus SB. The processor PROC, the address configuration unit ACU and the multi-port memory MEM are all coupled together via the system bus SB. During execution of an instruction, the processor PROC may issue an operation to access the multi-ported memory MEM in order to read or write a vector with data elements. Before reading or writing a group of data elements from the multi-port memory MEM, the address configuration unit ACU should be configured by configuration instructions issued by the processor PROC. The configuration instructions configure the address configuration unit ACU so that it can use the memory base address to calculate a set of memory addresses specific to the set of data elements to be retrieved from the multi-ported memory MEM. The configuration of the address calculation unit ACU remains unchanged until the next configuration command is issued. After configuring the address configuration unit ACU, the processor issues a read operation including the memory base address, and the memory base address is sent to the address calculation unit ACU. Subsequently, the address calculation unit ACU calculates a set of memory addresses. These memory addresses are sent via the system bus SB to the multi-port memory MEM, followed by reading data elements from the multi-port memory MEM. These data elements are sent to the processor PROC as a single vector and made available for further processing. If the processor PROC issues a write operation, it sends the memory base address to the address configuration unit ACU. The address configuration unit ACU calculates a set of memory addresses and sends the set of memory addresses to the multi-port memory MEM via the system bus SB. The data elements are also sent to the multi-port memory MEM via the system bus SB. In the next step, the data elements are written to the multi-port memory MEM. Before the next write or read operation, it may be necessary to issue a new configuration command depending on the desired set of memory addresses. For example, if a set of data elements that must be read requires the same set of memory addresses and applies the same memory base address, then the configuration command does not have to be repeated. It is also not necessary to issue new configuration commands when a different memory base address is used, but the desired configuration of the address configuration unit ACU remains the same.

Fig. 2 shows a block diagram of a memory system MS comprising an embodiment of a multi-port memory MEM and an address configuration unit ACU. The multi-port memory MEM includes: RAM memory, four data input ports DatIn, four address ports Addr and four data output ports DatOut. The address configuration unit ACU includes: an address port AddIn, four address calculation units AU, four register files RF and four data input ports DatIn. In this embodiment, the data input Datln is a shared data input port for both the address configuration unit ACU and the multi-port memory MEM. The address input port AddrIn is coupled to the address calculation unit AU, which in turn is coupled to its corresponding address port Addr of the multi-port memory MEM. The data input port DatIn is coupled to the register file RF. The register file RF is accessible by the address calculation unit AU.

The multi-port memory MEM supports commands for reading and writing data. Data can be read from the RAM memory via the data output port DatOut by using the address port Addr. The four data elements read from the data output port DatOut can be combined into one vector. A set of four data elements can be written to the multi-port memory via the data input port DatIn and using the address port Addr for memory addressing.

The address configuration unit ACU supports configuration instructions that specify a set of offsets relative to a memory base address. When a configuration command is executed, an offset value is written to each register file RF via the corresponding data input port DatIn. Subsequently, the address calculation units AU fetch the offset value from their corresponding register file RF and store this value internally.

In case the processor PROC issues a read operation to the memory system MS, it provides the memory base address at the address port Addrln. The address calculation unit AU obtains the value of the memory base address from the address input port AddrIn, and increases their corresponding offset value. The address calculation unit AU sends the obtained memory address group to the corresponding address port Addr, and then sends a read command to the multi-port memory MEM. The resulting set of data elements is provided at the data output port DatOut of the multi-port memory MEM. The processor PROC can also issue a write operation to the storage system MS in order to write a set of data elements to the RAM memory. The address port AddrIn receives the memory base address. The address calculation unit AU calculates a set of memory addresses using the memory base addresses and their corresponding offset values. The obtained memory address group is sent to the corresponding address port Addr of the multi-port memory MEM. The data elements are sent to the data input port DatIn of the multi-port memory MEM. Subsequently, a write command is issued to the multi-port memory MEM and the data elements are written into the RAM memory.

In other embodiments, the configuration instruction may include sending a set of commands to the address configuration unit AU for calculating the offset group.

Using appropriate configuration instructions, the set of offsets received by the register file RF is combined with the memory base address in such a way that the address calculation unit AU can define an arbitrary set of memory addresses. Using this set of memory addresses, a group of data elements can be simultaneously written into the multi-port memory MEM or retrieved from the multi-port memory MEM simultaneously. Thus, the memory system MS functions as a vector memory system, which has the advantage of allowing a set of data elements to be retrieved from an arbitrary memory location using a memory base address. Furthermore, the memory system MS has the advantage over multi-ported memories that by using one memory address a set of data elements can be addressed without requiring a set of memory addresses from an external source. As a result, the instruction width can be reduced, which is of particular concern for very large instruction word processors where code size reduction is an important issue.

It should be noted that the above-mentioned embodiments illustrate rather than limit the invention, and that those skilled in the art will be able to design many alternative embodiments without departing from the scope of the appended claims. In the claims, any reference signs placed between parentheses shall not be construed as limiting the claim. The word "comprising" does not exclude the presence of other elements or steps than those listed in a claim. The word "a" or "an" preceding an element does not exclude the presence of a plurality of such elements. The invention can be implemented by means of hardware comprising several distinct elements, by means of a suitably programmed computer. In a device claim enumerating several means, several of these means can be embodied by one and the same item of hardware. The mere fact that certain measures are recited in mutually different dependent claims does not indicate that a combination of these measures cannot be used to advantage.

Claims (8)

1. A method for transmitting a vector in a computer system, said computer system comprising: processor; multi-ported memory accessible by the processor, It is characterized in that the method comprises the following steps: passing the memory base address to the address configuration means; defining a set of memory addresses by means of address configuration means using a memory base address and configuration instructions for configuring the address configuration means; Vectors are transferred to/from the multi-port memory using the set of memory addresses. 2. The method of claim 1, wherein: The address configuration device includes: a plurality of register files configured by configuration instructions, and a plurality of address calculation units for calculating the memory address group; The register file is accessible by an address calculation unit; The address calculation unit is coupled to a multi-port memory. 3. The method of claim 1, wherein: The configuration instructions include a set of offsets, each offset combined with a memory base address to define a second memory address. 4. A computer system comprising: processor; a multi-port memory accessible by the processor, It is characterized in that the computer system further includes: an address configuration device, wherein the address configuration device is designed to define a group of memory addresses using a memory base address and configuration instructions for configuring the address configuration device, and wherein the multiple Port memories are designed to use the set of memory addresses. 5. The computer system of claim 4, wherein: The address configuration device includes: a plurality of register files configured by configuration instructions, and a plurality of address calculation units for calculating the memory address group; The register file is accessible by an address calculation unit; The address calculation unit is coupled to a multi-port memory. 6. The computer system of claim 4, wherein: The configuration instructions include a set of offsets, each offset combined with a memory base address to define a second memory address. 7. The computer system according to claim 4, wherein: said multi-port memory and address configuration means are both included in a memory system. 8. A computer program comprising computer program code means for instructing a computer system to perform the steps of the method as claimed in claim 1.

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