CN1663101A - Power factor calibrating circuit having variable switching frequency - Google Patents

Abstract

A power factor correction (PFC) circuit includes a pulse width modulator operating in response to a clock signal (CLK) for switching a coil current (ICOIL) over a charging period (TCHG) to correct a power factor at a node. The coil current discharges over a discharging period (TDSCHG) to develop an output voltage (VOUT) at an output. An oscillator generates the clock signal to have a clock period (TCLK) longer than the sum of the charging and discharging periods, thereby operating in a discontinuous mode, and has an input for sensing the input signal to modify the clock period.

Description

Power factor calibration circuit and method for switching frequency change

technical field

The present invention relates generally to integrated circuits, and more particularly to integrated power factor correction circuits.

Background technique

Lighting fixtures, as well as other electrical systems, have low power factor because they only draw current around the peak voltage of the alternating current (AC) source, rather than throughout the alternating cycle. For all consumers in a given distribution network, voltage peaks occur at the same time, resulting in an aggregation effect that causes grid generators to carry high currents near the voltage peaks, and little or no current at other times . This load causes harmonic distortion of the mains voltage, high neutral currents in the three-phase distribution network, and can cause erratic operation of equipment operating on the source. In order to avoid this line distortion, local utility companies have to expand their power distribution network, which requires a large amount of capital investment.

Some governments have attempted to alleviate this problem by requiring system manufacturers to include power factor correction (PFC) in certain electrical systems. For example, the European IEC 1000-3-2 specification requires the addition of PFCs to lighting systems as well as certain other electrical equipment. PFC is usually implemented by a PFC circuit that switches the supply current through a coil at a frequency much higher than the supply frequency, then discharges the coil current to a capacitor through a blocking diode, thereby creating a direct current (DC) supply voltage, This DC voltage is rectified and used to power the device or system. The switching of the current is controlled such that the average value of the coil current is proportional to the AC supply voltage, ie in phase and substantially sinusoidal. This approach can achieve a power factor of .995 or better, or even the ideal 1.0.

A significant portion of existing PFC circuits operate in continuous conduction mode, where a new switching cycle begins before the previous cycle's coil current discharges to zero. Continuous conduction mode PFC systems require high performance coils and blocking diodes with fast recovery times in order to maintain efficient power transfer. However, high-performance coils and blocking diodes are costly, which increases the manufacturing cost of continuous conduction mode PFC systems. In addition, these systems typically operate at a fixed switching frequency, resulting in high peak energy, requiring an expensive filter to suppress the resulting electromagnetic interference (EMI).

Other PFC systems operate in critical or boundary conduction mode, where a new switching cycle begins just as the coil current reaches zero. Boundary conduction mode circuits can provide high power factor, but they operate over a wide range of switching frequencies, requiring complex and expensive filters to suppress EMI. Also, under low power conditions, the switching frequency is so high that the propagation delay through the PFC circuit reduces the achievable power factor.

Other PFC circuits operate in a discontinuous mode in which the coil current is allowed to drop to zero for a period of time during each switching cycle. These systems can be set to switch at a fixed frequency, narrowing the EMI spectrum and allowing the use of narrowband EMI filters. However, like continuous conduction mode PFC circuits, these systems generate high peak radiated energy at a single frequency, which is difficult to reject even with narrowband filters.

There is therefore a need for a PFC circuit and method that can switch within a controlled range, thereby reducing the cost of filtering EMI in electrical systems.

Description of drawings

Fig. 1 shows a schematic diagram of the principle of a power factor calibration (PFC) circuit;

Figure 2 shows a timing diagram showing the working waveform of the PFC circuit;

Figure 3 shows a schematic diagram of a part of the PFC circuit containing an oscillator;

Fig. 4 shows a schematic diagram of the principle of the oscillator in the first alternative embodiment;

Figure 5 shows a schematic diagram of the principle of an oscillator in a second alternative embodiment;

Figure 6 shows a circuit diagram of a PFC circuit in an alternative embodiment; and

Fig. 7 shows a circuit diagram of a PFC circuit in another alternative embodiment.

Detailed ways

In the figures, elements with the same reference number have similar functions.

FIG. 1 shows a schematic diagram of a power factor calibration (PFC) circuit 100 for calibrating the power factor of an alternating current (AC) power supply operating with a sinusoidal AC voltage VAC while supplying a load 28 provide a load current I _LOAD . The PFC circuit 100 is controlled by the PFC control circuit 10, and the circuit operates in a discontinuous mode with a supply voltage of V _CC =12.0 volts. The PFC circuit 100 contains an electromagnetic interference (EMI) filter 15, a capacitor 19, a Diode bridge 20 , resistors 16 - 18 and 45 , an inductor or coil 25 , a blocking diode 26 and an output capacitor 27 . PFC circuit 100 generates a direct current (DC) output voltage V _OUT at output node 30 .

In summary, the PFC circuit 100 provides a high power factor for an AC power source by calibrating the power factor at the input node 32 operating on the input voltage V _IN obtained by rectifying VAC. In effect, PFC circuit 100 utilizes feedback to create a resistive load at node 32 and the negative terminal of bridge 20, which in the embodiment shown in FIG. 1 operates at ground potential. Therefore, the average value of the current flowing through node 32, as well as the AC supply, is in phase with V _IN .

Specifically, PFC circuit 100 functions as a step switching regulator in which resistors 16-17 act as a voltage divider to establish a value of V _OUT that is boosted to a level higher than the peak voltage of VAC . In one embodiment, the root mean square (RMS) value of VAC is about 220V, the frequency is about 50 Hz, and the output voltage V _OUT generated by the PFC circuit 100 has a value of about 400V DC. In some regions, the RMS value of VAC is about 110 volts and the frequency is about 60 Hz, so the PFC circuit 100 generates a DC voltage V _OUT of about 230 volts. The dimensions, breakdown voltage, etc. of the components of the PFC circuit 100 can be appropriately selected so that a system with V _OUT set at about 400 volts DC can be operated from any AC power source in the world. Such systems are known as global power systems. The typical range for VAC is plus or minus twenty percent in most areas.

In an alternate embodiment, the PFC circuit 100 is configured to combine the power factor correction function with a voltage regulator in a single stage circuit that produces a V _OUT that is lower than the peak VAC voltage. For example, resistors 16-17 may be selected such that PFC circuit 100 provides a V _OUT voltage of, say, 5 volts.

The EMI filter 15 is a low-pass filter that passes the low-frequency components of VAC while suppressing the high-frequency switching signals generated by the PFC circuit 100 . In one embodiment, EMI filter 15 is configured to suppress signal components above one kilohertz.

Diode bridge 20 is a standard full wave bridge rectifier, this circuit rectifies the line voltage VAC and produces a rectified sine wave input voltage V _IN at node 32 which has a frequency twice the frequency of VAC Or about 100 hertz, which has a peak voltage of about 310 volts. Capacitor 19 is connected across diode bridge 20 to further reduce VAC noise.

Coil 25 has a typical inductance of L ₂₅ =100.0 microhenries and has a low equivalent series resistance for high efficiency operation.

The PFC control circuit 10 includes a transistor 29 , a pulse width modulation (PWM) control circuit 31 and an oscillator 35 .

PWM control circuit 10 receives a clock signal CLK from oscillator 35 and issues a series of pulses, called drive signal V _DRIVE , which switch transistor 29 . Resistors 16 and 17 act as a voltage divider which divides the output voltage V _OUT to produce a feedback signal V _FB at input 36 . In one embodiment, the PWM control circuit 31 compares the feedback voltage V _FB with an internally generated reference voltage to modulate the width of the V _DRIVE pulse. Therefore, when the load 28 draws an increased load current I _LOAD to discharge the capacitor 27 and decrease the output voltage V _OUT , the level of the feedback voltage V _FB decreases accordingly. In response, PWM control circuit 31 increases the width of the V _DRIVE pulse, which increases the charge transferred from coil 25 to capacitor 27, thereby regulating V _OUT to its specified level. Thus, the PWM control circuit 31 is arranged such that if the load current I _LOAD is constant with respect to the frequency of V IN (or about 120 Hz), then the width of the V _DRIVE pulse remains constant for one cycle of V _IN . In one embodiment, the PFC control circuit 10 is adapted to be integrated onto a semiconductor die to form an integrated circuit.

Transistor 29 is a high current n-channel MOSFET that switches the coil current I _COIL through coil 25 . In one embodiment, transistor 29 is a power transistor capable of switching I _COIL peaks above 2 amps. Transistor 29 typically has a large gate capacitance above 500 picofarads. Transistor 29 is shown integrated on a semiconductor die together with other components of PFC control circuit 10, but it could also be implemented as a separate discrete device.

The coil current I _COIL includes a charging current component I _CHG and a discharging current component I _DSCHG . The time during which transistor 29 is turned on is referred to as charging period T _CHG , during which charging current I _CHG flows through coil 25 and transistor 29 , thereby storing magnetic energy in coil 25 . If the load current I _LOAD is constant, then T _CHG is also constant throughout the V _IN cycle. When the transistor 29 is turned off, the stored magnetic energy flows from the coil 25 through the blocking diode 26 into the capacitor 27 in the form of a discharge current I _DSCHG , and forms an output voltage V _OUT at the node 30 . The time during which the discharge current I _DSCHG flows is called the discharge period T _DSCHG , and this time period will vary with the peak value of the charge current I _CHG and the voltage of V _IN .

The oscillator 35 is configured as a voltage controlled oscillator having an input 39 for sensing an input current I _{IN derived from an input voltage V IN .} Input 39 operates near ground potential, so that I _IN is equivalent to V _IN /R ₁₈ , where R ₁₈ is the resistance of resistor 18 . Since V _IN has the waveform of a rectified sine wave, I _IN also has the waveform of a rectified sine wave and thus can represent V _IN . One output provides a clock signal CLK at a frequency that varies depending on I _IN . In one embodiment, the magnitude of I _IN is chosen such that the clock signal CLK varies in a range of less than two to one, which is well below the switching frequency range of critical conduction mode PFC circuits, whose frequency spectrum is often Spanning a range of twenty to one or even greater. In one embodiment, oscillator 35 generates CLK at a nominal frequency of about 40 kilohertz, which can vary from about 30 kilohertz to about 50 kilohertz.

The controlled switching frequency range of CLK reduces the peak EMI radiation at any single frequency, while creating a limited spectrum of EMI radiated energy, so that the EMI filter 15 can be arranged in a less complex and costly form such that The overall cost of the PFC circuit 100 is reduced. The nominal operating frequency of CLK can be selected such that when it operates at the highest frequency value corresponding to the input current I _IN , the period of CLK is still low enough for the PFC circuit 100 to operate in discontinuous mode, i.e. Say, in this mode, I _COIL is zero for a non-zero period of a switching cycle.

The switching cycle of the PFC control circuit 10 is initiated by the clock signal CLK, the duty cycle of which is much shorter than the cycle of V _IN , so in any particular switching cycle, a substantially constant voltage V _IN appears across the coil 25 . Therefore, the charging current I _CHG increases linearly with a slope approximately equal to V _IN /L, and reaches a peak value I _PEAK =T _CHG *V _IN /L. Similarly, the slope of the discharge current I _DSCHG is approximately equal to (V _OUT −V _IN )/L, and its duration T _DSCHG =L*I _PEAK /(V _OUT −V _IN ). Thus, the total time that I _COIL is non-zero is given by:

${\mathrm{<span\; class="notranslate">\; 1</span>}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span>\mathrm{<span\; class="notranslate">\; T</span>}}_{\mathrm{<span\; class="notranslate">\; COIL</span>}}<span\; class="notranslate">\; =</span>{\mathrm{<span\; class="notranslate">\; T</span>}}_{\mathrm{<span\; class="notranslate">\; CHG</span>}}<span\; class="notranslate">\; +</span>{\mathrm{<span\; class="notranslate">\; T</span>}}_{\mathrm{<span\; class="notranslate">\; DSCHG</span>}}<span\; class="notranslate">\; =</span>\mathrm{<span\; class="notranslate">\; L</span>}<span\; class="notranslate">\; \&CenterDot;</span>{\mathrm{<span\; class="notranslate">\; I</span>}}_{\mathrm{<span\; class="notranslate">\; PK</span>}}<span\; class="notranslate">\; \&CenterDot;</span>\frac{{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; out</span>}}}{{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; IN</span>}}<span\; class="notranslate">\; \&CenterDot;</span><span\; class="notranslate">\; (</span>{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; out</span>}}<span\; class="notranslate">\; -</span>{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; IN</span>}}<span\; class="notranslate">\; )</span>}$

The coil current I _COIL flows in the form of a triangular wave, and its average value I _{COIL_CLK} within one CLK cycle T _CLK is given by the following formula:

$\mathrm{<span\; class="notranslate">\; 2</span>}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span>{\mathrm{<span\; class="notranslate">\; I</span>}}_{\mathrm{<span\; class="notranslate">\; COIL</span>}<span\; class="notranslate">\; \_</span>\mathrm{<span\; class="notranslate">\; CLK</span>}}<span\; class="notranslate">\; =</span>\frac{{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; IN</span>}}<span\; class="notranslate">\; \&CenterDot;</span>{\mathrm{<span\; class="notranslate">\; <figure-callout\; id="2"\; label="T\; CHG"\; filenames="A0381423700211.png"\; state="\{\{state\}\}">T</figure-callout></span><figure-callout\; id="2"\; label="T\; CHG"\; filenames="A0381423700211.png"\; state="\{\{state\}\}">\; </figure-callout>}}_{\mathrm{<span\; class="notranslate">\; </span>}}}{\mathrm{<span\; class="notranslate">\; 2</span>}<span\; class="notranslate">\; \&CenterDot;</span>\mathrm{<span\; class="notranslate">\; L</span>}}<span\; class="notranslate">\; \&CenterDot;</span>\frac{<span\; class="notranslate">\; (</span>{\mathrm{<span\; class="notranslate">\; T</span>}}_{\mathrm{<span\; class="notranslate">\; CHG</span>}}<span\; class="notranslate">\; +</span>{\mathrm{<span\; class="notranslate">\; T</span>}}_{\mathrm{<span\; class="notranslate">\; DSCHG</span>}}<span\; class="notranslate">\; )</span>}{{\mathrm{<span\; class="notranslate">\; T</span>}}_{\mathrm{<span\; class="notranslate">\; CLK</span>}}}<span\; class="notranslate">\; =</span>\frac{{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; IN</span>}}}{\mathrm{<span\; class="notranslate">\; 2</span>}<span\; class="notranslate">\; \&CenterDot;</span>\mathrm{<span\; class="notranslate">\; L</span>}}<span\; class="notranslate">\; (</span>{\mathrm{<span\; class="notranslate">\; T</span>}}_{\mathrm{<span\; class="notranslate">\; CHG</span>}}<span\; class="notranslate">\; \&Center\; Dot;</span>{\mathrm{<span\; class="notranslate">\; D.</span>}}_{\mathrm{<span\; class="notranslate">\; CYCLE</span>}}<span\; class="notranslate">\; )</span>$

Wherein D _CYCLE =(T _CHG +T _DSCHG )/T _CLK , which represents the duty cycle of the non-zero coil current in each CLK cycle T _CLK . A high power factor is achieved when the average coil current I _{COIL_CLK} follows the rectified sinusoidal waveform of V _IN , which occurs when T _CHG *D _CYCLE is set to a constant value.

Since the charging time T _CHG is also constant when the load current I _LOAD is constant, in order to keep the product of T _CHG *D _CYCLE constant and achieve a high power factor, the oscillator 35 will change the switching frequency F _SW of CLK to maintain D _CYCLE is basically constant. The average input power <P _IN > over a cycle of the input voltage V _IN is given by Equation 3):

$\mathrm{<span\; class="notranslate">\; 3</span>}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span>$ ${\mathrm{<span\; class="notranslate">\; P</span>}}_{\mathrm{<span\; class="notranslate">\; IN</span>}}<span\; class="notranslate">\; ></span><span\; class="notranslate">\; =</span>\frac{{\mathrm{<span\; class="notranslate">\; <figure-callout\; id="2"\; label="V\; ACRMS"\; filenames="A0381423700211.png"\; state="\{\{state\}\}">V</figure-callout></span><figure-callout\; id="2"\; label="V\; ACRMS"\; filenames="A0381423700211.png"\; state="\{\{state\}\}">\; </figure-callout>}}_{\mathrm{<span\; class="notranslate">\; </span>}}^{\mathrm{<span\; class="notranslate">ACRMS</span>}}}{\mathrm{<span\; class="notranslate">\; 2</span>}<span\; class="notranslate">\; *</span>{\mathrm{<span\; class="notranslate">\; L</span>}}_{\mathrm{<span\; class="notranslate">\; 25</span>}}}$ $<span\; class="notranslate">\; (</span>{\mathrm{<span\; class="notranslate">\; T</span>}}_{\mathrm{<span\; class="notranslate">\; CHG</span>}}<span\; class="notranslate">\; *</span>{\mathrm{<span\; class="notranslate">\; D.</span>}}_{\mathrm{<span\; class="notranslate">\; CYCLE</span>}}<span\; class="notranslate">\; )</span>$

where _VACRMS is the rms value of the line voltage VAC. When the load current I _LOAD is constant, the PFC circuit 100 works under the condition that the average input power <P _IN > is constant. Since V and L are both _constant , constant load conditions result in the product:

$\mathrm{<span\; class="notranslate">\; 4</span>}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; (</span>{\mathrm{<span\; class="notranslate">\; T</span>}}_{\mathrm{<span\; class="notranslate">\; CHG</span>}}<span\; class="notranslate">\; *</span>{\mathrm{<span\; class="notranslate">\; D.</span>}}_{\mathrm{<span\; class="notranslate">\; CYCLE</span>}}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; =</span>\frac{\mathrm{<span\; class="notranslate">\; 2</span>}<span\; class="notranslate">\; *</span>{\mathrm{<span\; class="notranslate">\; <figure-callout\; id="25"\; label="L"\; filenames="A0381423700241.png"\; state="\{\{state\}\}">L</figure-callout></span>}}_{\mathrm{<span\; class="notranslate">\; 25</span>}}<span\; class="notranslate">\; *</span><span\; class="notranslate">\; <</span>{\mathrm{<span\; class="notranslate">\; P</span>}}_{\mathrm{<span\; class="notranslate">\; IN</span>}}<span\; class="notranslate">\; ></span>}{{\mathrm{<span\; class="notranslate">\; <figure-callout\; id="2"\; label="V\; ACRMS"\; filenames="A0381423700211.png"\; state="\{\{state\}\}">V</figure-callout></span><figure-callout\; id="2"\; label="V\; ACRMS"\; filenames="A0381423700211.png"\; state="\{\{state\}\}">\; </figure-callout>}}_{\mathrm{<span\; class="notranslate">\; </span>}}^{\mathrm{<span\; class="notranslate">ACRMS</span>}}}$

Also constant. From these relationships, it can be deduced that the switching frequency F _SW required to achieve high power factor is given by:

$\mathrm{<span\; class="notranslate">\; 5</span>}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span>{\mathrm{<span\; class="notranslate">\; f</span>}}_{\mathrm{<span\; class="notranslate">\; SW</span>}}<span\; class="notranslate">\; =</span>\frac{\mathrm{<span\; class="notranslate">\; 2</span>}<span\; class="notranslate">\; *</span>{\mathrm{<span\; class="notranslate">\; <figure-callout\; id="25"\; label="L"\; filenames="A0381423700241.png"\; state="\{\{state\}\}">L</figure-callout></span>}}_{\mathrm{<span\; class="notranslate">\; 25</span>}}<span\; class="notranslate">\; *</span><span\; class="notranslate">\; <</span>{\mathrm{<span\; class="notranslate">\; P</span>}}_{\mathrm{<span\; class="notranslate">\; IN</span>}}<span\; class="notranslate">\; ></span>}{{\mathrm{<span\; class="notranslate">\; <figure-callout\; id="2"\; label="V\; ACRMS"\; filenames="A0381423700211.png"\; state="\{\{state\}\}">V</figure-callout></span><figure-callout\; id="2"\; label="V\; ACRMS"\; filenames="A0381423700211.png"\; state="\{\{state\}\}">\; </figure-callout>}}_{\mathrm{<span\; class="notranslate">\; </span>}}^{\mathrm{<span\; class="notranslate">ACRMS</span>}}<span\; class="notranslate">\; *</span>{\mathrm{<span\; class="notranslate">\; <figure-callout\; id="2"\; label="T\; CHG"\; filenames="A0381423700211.png"\; state="\{\{state\}\}">T</figure-callout></span><figure-callout\; id="2"\; label="T\; CHG"\; filenames="A0381423700211.png"\; state="\{\{state\}\}">\; </figure-callout>}}_{\mathrm{<span\; class="notranslate">\; </span>}}^{\mathrm{<span\; class="notranslate">CHG</span>}}}<span\; class="notranslate">\; *</span>\frac{{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; out</span>}}<span\; class="notranslate">\; -</span>{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; IN</span>}}}{{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; out</span>}}}$

As a result, the PFC circuit 100 can operate with a PFC close to unity if the switching frequency F _SW is set to be proportional to the difference between the output voltage V _OUT and the instantaneous rectified input voltage V _IN . In fact, under the steady-state conditions described, V _OUT is regulated and thus constant, so Equation 5) can be simplified to:

6) F _SW ＝K ₁ *(K ₂ -V _IN )

where K ₁ is a constant, K ₂ =V _OUT , and the regulator adjusts T _CHG so that at a given <P _IN > and VAC operating point, ${\mathrm{<figure-callout\; id="1"\; label="K"\; filenames="A0381423700211.png"\; state="\{\{state\}\}">K</figure-callout>}}_1=\frac{2*{\mathrm{<figure-callout\; id="25"\; label="L"\; filenames="A0381423700241.png"\; state="\{\{state\}\}">L</figure-callout>}}_{25}*<P_{\mathrm{IN}}>}{{\mathrm{<figure-callout\; id="2"\; label="V\; ACRMS"\; filenames="A0381423700211.png"\; state="\{\{state\}\}">V</figure-callout>}}_{\mathrm{ACRMS}}^{}*{\mathrm{<figure-callout\; id="2"\; label="T\; CHG"\; filenames="A0381423700211.png"\; state="\{\{state\}\}">T</figure-callout>}}_{\mathrm{CHG}}^{}*V_{\mathrm{out}}}.$ To achieve high power factor, the CLK frequency _FSW is effectively modulated by _VIN such that _FSW has a lower value near the peak _{of VIN} and a higher value when _VIN approaches zero volts. In order to achieve this, the oscillator 35 has several input terminals operating near the ground potential, one detects the input voltage V _{IN according to the induced current I IN} formed through the resistor 18, and the other detects the input voltage V _IN according to the current I _OUT formed through the resistor 45 to detect the output voltage V _OUT . Oscillator 35 subtracts I _IN from I _OUT to obtain a differential current that is used to establish the instantaneous value of CLK period T _CLK and switching frequency F _SW .

The detailed working process of the PFC circuit 100 can be referred to the timing diagram in FIG. 2 , which shows the input voltage V _IN , the coil current I _COIL , the driving signal V _DRIVE and the clock signal CLK in the selected switching period (T4-T0) and Waveforms within (T9-T5), each with a duration in the range of approximately 50 microseconds, and (T9-T5) > (T4-T0). Figure 2 shows two CLK cycles or periods T _CLK , the first period running from time T0 to time T4, and the second (and longer one) running from time T5 to time T9. Although the input voltage V _IN will vary in the form of a rectified sine wave, the CLK period is much shorter than the V _IN period. Therefore, to better describe the invention, V _IN is shown as a constant value in each cycle, but its value V _IN1 in the first cycle is lower than the value V _IN2 in the second cycle.

Assume that initially - just before time T0 - both CLK and V _DRIVE are logic low, and both transistor 29 and blocking diode 26 are off, so that I _COIL = 0.0 amps.

At time T0, as the clock signal CLK transitions from a logic low level to a logic high level and sends out a pulse of the drive signal V _DRIVE , the first switching cycle begins. Transistor 29 is turned on to charge coil 25. The charging current I _CHG increases linearly at the rate of V _IN /L ₂₅ . Since the voltage across transistor 29 is close to zero, the entire voltage V _IN is effectively applied across coil 25 . Thus, the charge current I _CHG increases at a rate proportional to the instantaneous value of V _IN .

During the period from time T0 to T1, the input signal V _IN has a substantially constant voltage value V _IN1 , so that the charging current I _CHG increases linearly until it reaches a peak value I _PK1 =V _IN1 *T _CHG /L ₂₅ at time T1 .

At time T1, V _DRIVE transitions from a logic high level to a logic low level, thereby turning off the transistor 29 so that the energy stored in the coil 25 is transferred to the capacitor 27 through the blocking diode 26 . The voltage drop across the blocking diode 26 is small compared to the voltage (V _OUT −V _IN ), so it can be considered that (V _OUT −V _IN ) is applied across the coil 25 and I _DSCHG at a rate of (V _OUT -V _IN1 )/L ₂₅ decreases linearly until it discharges to zero at time T3=T1+I _PK1 *L ₂₅ /(V _OUT −V _IN1 ).

At time T2, the clock signal CLK is reset from a high level to a low level, which does not cause a voltage change of the driving signal V _DRIVE .

From time T3 to time T4, I _COIL remains at zero for a non-conduction time, which is a characteristic of the discontinuous operation mode of the PFC circuit 100 .

At time T4, the first switching period ends and another switching period begins. Several CLK switching cycles may also follow.

At time T5, the specified second cycle starts, and CLK and V _DRIVE change from low to high at the same time, but the input voltage V _IN operates at a higher effective voltage value V _IN2 >V _IN1 . A higher VIN2 value causes the charge current ICHG to increase linearly at a faster rate and flow through coil 25 and transistor 29 until it reaches a peak value I _PK2 =V _IN2 *T _CHG /L ₂₅ at time T6, which is higher than the peak value I _PK1 . Note that T _CHG =(T1-T0)=(T6-T5), when I _LOAD is constant, this charging time also has a fixed value.

At time T6, V _DRIVE makes another jump from high to low, thereby turning off the transistor 29, and allowing the magnetic energy stored in the coil 25 to flow through the blocking diode 26 in the form of a discharge current I _DSCHG , so as to be stored in the capacitor 27 superior. During the period from time T6 to time T8, a substantially constant voltage (V _OUT −V _IN2 ) is applied across the coil 25, so that I _DSCH decreases linearly with a slope of (V _OUT −V _IN2 )/L ₂₅ until it is at Time T8=T6+I _PK2 *L ₂₅ /(V _OUT −V _IN2 ) is discharged to zero. Since V _IN2 >V _IN1 , the coil current I _COIL will reach a higher peak current I _PK2 , but discharge at a lower rate (V _OUT −V _IN2 )/L ₂₅ . The second non-conduction period begins at time T8 - when I _COIL is discharged to zero - and continues until the end of the second switching period and another switching period begins at time T9.

At time T7, the clock signal CLK transitions from high to low, which will not affect the level of the driving signal V _DRIVE .

The circuit schematic shown in FIG. 3 shows a portion of the PFC circuit 100 , including more details of the oscillator 35 , and the resistors 18 and 45 . Oscillator 35 includes current mirrors 57 - 60 , switches 62 - 65 , a timing capacitor 68 and a comparator 69 . Oscillator 35 is configured as a voltage controlled oscillator which generates a clock signal CLK in the form of a series of pulses at a nominal or center frequency which is modulated to be proportional to the difference (V _OUT -V _IN ). Proportional.

Timing capacitor 68 is connected between timing node 70 and ground potential. Capacitor 68 is generally integrated on the same semiconductor die together with other components of PFC control circuit 10, but can also be made as an external capacitor. In one embodiment, capacitor 68 has a value of approximately 100 picofarads. Capacitor 68 is sequentially charged and discharged by currents I _IM2 , I _IM3 , I _OM2 and I _OM3 to develop a triangular or ramp voltage V _RAMP at node 70 as described below.

The switches 62-65 are implemented with transistors, which are respectively controlled by the clock signal CLK or the complementary clock signal CLK is enabled or turned on, as shown in the figure. Therefore, switches 62 and 65 are enabled or closed when CLK is logic high, and switches 63 and 64 are at Closed when CLK is logic high and CLK is logic low.

Comparator 69 is configured as a hysteretic comparator which compares the voltage developed at timing node 70 with a reference voltage V _REF to generate clock signal CLK at its output. Comparator 69 has output terminals providing complementary clock signals CLK and CLK, or CLK can be obtained by inverting CLK by a separate inverter (not shown). When the comparator 69 generates a CLK with eg a logic high level, an internal hysteresis circuit will lower the comparison reference value by a hysteresis amount V _HYST to become (V _REF −V _HYST ). Thus, CLK remains logic high until V _RAMP discharges to a level lower than 2(V _REF -V _HYST ), at which point CLK transitions to logic low. The function of the hysteresis is to make V _RAMP form a triangular wave, and the triangular wave changes periodically between V _REF and (V _REF -V _HYST ), as shown in Fig. 2 . In an embodiment where the supply voltage V _CC =12.0V, V _REF has a value of approximately 3V and V _HYST has a value of approximately 1V, so the voltage difference (V _REF -V _HYST ) has a level of approximately 2V.

Current mirrors 57-58 include proportional transistors that generate mirrored currents I _IM1 , I _IM2 , I _IM3 and I _IM4 that are proportional to or integer multiples of the input sense current I _IN . Similarly, the current mirrors 59-60 also include proportional transistors, which generate mirror currents I _OM1 , I _OM2 and I _OM3 , which are proportional to the output sense current I _OUT or an integer multiple thereof.

The operation of the oscillator 35 is as follows. Assuming initially the clock signal CLK is logic low, so switches 63 and 64 are closed, switches 62 and 65 are open, and the value of V _RAMP is less than V _REF and is increasing, as shown in FIG. 2 . At time T0, CLK transitions to a logic high level, which closes switches 62 and 65 and opens switches 63-64, thereby discharging capacitor 68 with current I _OM3 and charging with current I _IM2 . The ratio of current mirrors 57-60 is such that I _OM3 is greater than I _IM2 so that the algebraic sum of currents I _OM3 and I _IM2 results in a net difference in current (I _OM3 −I _IM2 ) that discharges capacitor 68, thereby reducing V _RAMP level.

At time T2, V _RAMP reaches level (V _REF −V _HYST ), at which point CLK transitions to a logic low level, which closes switches 63 - 64 and opens switches 62 and 65 . Capacitor 68 is then charged by current I _OM2 and simultaneously discharged by current I _IM3 . The currents I _IM3 and I _OM2 are adjusted such that I _IM3 <I _OM2 , which charges capacitor 68 with an effective differential current (I _OM2 −I _IM3 ). When the capacitor 68 is charged to V _RAMP > V _REF , CLK will jump from low to high, thus starting another cycle.

The mirror scaling ratios of the current mirrors 57-60 are further chosen such that the currents charged and discharged by the capacitor 68 are respectively (I _OM2 −I _IM3 )=K ₃ *(V _OUT −V _IN ) and (I _OM3 −I _IM2 )=K ₄ *(V _OUT −V _IN ), where K ₃ and K ₄ are constants. It is not difficult to find that the switching frequency F _SW has the form shown in Equation 6) above, so that a power factor close to 1 can be achieved.

The circuit schematic shown in FIG. 4 shows a portion of the PFC circuit 100 including more details of the oscillator 35 and the resistor 18 in an alternative embodiment. Oscillator 35 includes current sources 80 - 81 , current mirrors 57 - 58 , switches 62 - 65 , timing capacitor 68 and comparator 69 .

When CLK is high level and switch 64 is closed, current source 80 provides a charging reference current I _REF1 from supply voltage V _CC to node 70, and when CLK is high level and switch 65 is closed, current source 81 supplies to node 70 70 provides a scaled or mirrored discharge reference current I _REF2 . The scaling or mirroring ratios of current mirrors 57-58 and current sources 80-81 are chosen such that when CLK is high, capacitor 68 is driven by a differential current (I _REF1 −I _IM3 )=K ₅ *(V _REF −V _IN ), and is discharged by a differential current (I _REF2 -I _IM2 )=K ₇ *(V _REF -V _IN ), where K ₅ and K ₇ are constants. Clearly, these equations establish a switching frequency F _SW corresponding to Equation 6) above, enabling a power factor close to unity, assuming V _REF represents the ideal value of V _OUT .

The schematic diagram shown in Fig. 5 shows more details of the oscillator 35 in another alternative embodiment. This embodiment has similar working process and structure with the embodiment shown in Fig. 4, but the comparator 69 among them is non-hysteresis type, and the switching limitation of V _RAMP is established by a limit voltage V _LIM , the circuit that produces this voltage Comprising resistors 83-84 and 88-89, a capacitor 85, a squaring circuit or multiplier 86, a dividing circuit 87 and a switch 90.

As shown above, for constant I _LOAD and T _CHG , high power factor can be achieved if the CLK frequency F _SW is proportional to (V _OUT -V _IN ). However, as shown in Equation 6), if V _IN has a high magnitude, there will be relatively large changes in F _SW , especially at the voltage peak where the peak current I _COIL flows. This embodiment provides a circuit that reduces overall frequency variation or jitter and operates as follows.

Resistors 83-84 work as a voltage divider that divides the input voltage VIN, and capacitor 85 cooperates with resistors 83-84 to form a low-pass filter that produces an average voltage <V _IN1 > that has essentially zero ripple , or at least small compared to the rectified sinusoidal waveform of V _IN . In one embodiment, resistors 83-84 and capacitor 85 are selected to set the low pass corner frequency to about 10 Hz, so that _VR is approximately a DC voltage. As a result of this low-pass filtering, <V _IN1 > can represent the average value of V _IN .

Multiplier 86 is a standard analog multiplier circuit that squares the average voltage V _IN1 to produce a squared voltage V _SQ =K ₈ *<V _IN1 > ² , where K ₈ is a constant.

The dividing circuit 87 divides the reference voltage V _REF by V _SQ to generate a voltage V _LIM =V _DIV =V _REF /(K ₈ *<V _IN1 > ² ), which is coupled to the two ends of the resistor 88 so that the clock signal CLK low sets an upper limit for V _RAMP at one input of comparator 69 . When CLK is at a high level, switch 90 is closed, and V _DIV is divided by resistors 88-89, thereby establishing the lower limit of V _RAM . The lower limit level is V _LIM = V _REF /(K ₈ *<V _IN1 > ² )*R ₈₉ /(R ₈₈ +R ₈₉ ), wherein R ₈₈ and R ₈₉ are the resistance values of resistors 88 and 89 respectively.

Thus, the switching frequency F _SW =K ₉ *<V _IN > ² *(V _REF -V _IN ), where K ₉ is a constant. This option enables oscillator 35 to limit switching frequency variation to aid in EMI filtering.

FIG. 6 shows a schematic diagram of a PFC circuit 100 in an alternative embodiment. In this embodiment, the resistor 18 is not needed, thereby eliminating the power consumed by it P _R18 =I _IN ² *R ₁₈ , where R ₁₈ is the resistance of the resistor 18 . Therefore, this embodiment is suitable for applications that require low standby power consumption and a power factor lower than ideal.

The embodiment shown in FIG. 6 modulates the switching frequency F _SW with the instantaneous value of the coil current I _COIL instead of the input voltage _{V IN} . On average, I _COIL has a sinusoidal waveform in phase with V _IN due to the power factor calibration work of the PFC circuit 100 . I _COIL is sensed in its return path through resistor 72 to diode bridge 20 and develops a current sense voltage V _CS across resistor 72 at node 39 for modulating F _SW . In one embodiment, resistor 72 has a resistance of about 0.1 ohms, and V _CS is about -0.1 volts when I _COIL is 1 ampere. In addition, I _COIL can also be measured by other techniques, such as replacing the current sense resistor 72 with a current transformer. Using the coil current I _COIL instead of the input voltage V _IN to vary the switching frequency F _SW is a method suitable for both continuous mode and discontinuous mode PFC circuits, and is also suitable for power factor correction and downstream voltage regulators or converters embodiments are combined in a single-stage circuit.

The power of this embodiment is believed to be lower than the previously described embodiments due to the data because the instantaneous value of I _COIL is only close to the rectified sinusoidal waveform of V _IN . However, this version has lower power dissipation and can be manufactured at low cost, making it suitable for many applications that do not require the highest power factor. In one embodiment, power factor can be improved by connecting a capacitor across resistor 72 . This capacitor is chosen to filter out high frequency components, such as those above the frequency of V _IN , thereby producing a waveform at node 39 that more ideally approximates a rectified sine wave.

FIG. 7 shows a portion of the PFC circuit 100 in the embodiment shown in FIG. 6 , including a resistor 82 , a current source 78 , and more details of the current mirror 57 of the oscillator 35 .

Transistors 76-77 are shown as forming a matched or ratioed pair of NPN bipolar transistors with their emitter regions arranged in predetermined ratios. Current source 78 provides a current I _R through transistor 77 to establish a base-emitter voltage which biases the base electrode of transistor 76 to a fixed potential.

Resistor 82 is usually made as an external resistor to avoid adverse effects caused by the negative potential of current sense voltage V _CS when I _COIL flows. If transistors 76 and 77 have the same emitter area ratio, then their respective emitters will operate at substantially the same potential, and since V _CS =-R ₇₂ *I _COIL , the current I _M1 is proportional to I _COIL , I _SENSE is substantially equal to I _M1 (neglecting 57 base current) and V _CS +(R ₈₂ *I _SENSE ) is zero, where resistor 82 is R ₈₂ , chosen to provide an ideal Sampling current I _SENSE . Then I _M1 =R ₇₂ *I _COIL /R ₈₂ . I _SENSE is mirrored by current mirrors 58-59 to provide differential charge and discharge currents (I _REF1 -I _M3 ) and (I _REF2 -I _M1 ), respectively, to timing node 70, as described above.

In summary, the present invention provides a PFC circuit capable of operating in a discontinuous mode with a fixed switching pulse width. This discontinuous mode of operation allows the PFC circuit to be fabricated with low-cost blocking diodes, thus reducing system cost. A pulse width modulator is synchronized to the transition edges of the clock signal to generate the pulses that establish the charge cycle for the coil current. The coil current is then discharged during the discharge cycle so that an input signal forms a PFC output voltage. An oscillator generates the clock signal such that its clock period is longer than the sum of charge plus discharge cycles, thus ensuring discontinuous mode operation. The oscillator has an input to sense the input signal to the PFC circuit in order to vary the clock period in a controlled manner so as to keep the product of the charging period times the coil current duty cycle constant. In this way, the PFC circuit can switch the coil current within a predetermined frequency range to help reduce electromagnetic interference with a low-cost EMI filter.

Claims (25)

1. a power factor is calibrated (PFC) circuit, comprising:

The pulse width modulator of a response clock signal job is used at switching line loop current on the charge cycle so that the power factor on the calibration first node, and wherein said coil current discharges on a discharge cycle to form an output voltage; And

An oscillator, it has an output and brings in the described clock signal of generation, the clock cycle that this clock signal has is longer than the summation of described charging and discharge cycle, and a first input end, is used to detect the input signal of pfc circuit to regulate the described clock cycle.

2. pfc circuit according to claim 1, the load current of wherein said output voltage is a steady state value, described charging and discharge cycle are summed on the described clock cycle, defining the duty factor of described coil current, and described input signal changes the described clock cycle and keeps the product constant of duty factor and charge cycle.

3. pfc circuit according to claim 1, the input signal of wherein said pfc circuit are basically with the form work of rectified sine wave voltage.

4. pfc circuit according to claim 1, wherein said oscillator are formed a voltage controlled oscillator, comprising:

The ramp generator of the described clock signal work of response, it has a Section Point provides charging current to form a ramp voltage to an electric capacity, and this ramp voltage rises to second reference level from first reference level in charge cycle;

A comparator is used for more described ramp voltage and first and second reference voltage, and this comparator also has an output that is connected to described oscillator output end; And

A current mirror, it has a first input end, is used for receiving the input current of the described input signal of representative, so that one first image current to be provided to Section Point, to be used for deducting this image current from charging current and to change the described clock cycle.

5. pfc circuit according to claim 4, wherein said current mirror provide one second image current in order to the charging Section Point, and described ramp generator comprises:

First current source that is connected to described Section Point is used to provide described charging current; And

One second current source, it is coupled with a discharging current discharges to Section Point, wherein deducts second image current from described discharging current.

6. pfc circuit according to claim 1, wherein said pulse width modulator have a feedback input end, and this input is connected and detects described output voltage, so that come the charge cycle of regulating impulse according to the load current of pfc circuit.

7. pfc circuit according to claim 1, the output voltage shown in it has the value that is higher than described input signal crest voltage.

8. pfc circuit according to claim 1, wherein said input signal has been represented described coil current.

9. pfc circuit according to claim 8 wherein also comprises an inductive reactance that is connected to the oscillator first input end, is used for the described coil current of conducting and forms an induced voltage.

10. the power factor with discontinuous mode work is calibrated (PFC) circuit, comprising:

A pulse width modulator, it has an input that is used for receiving a plurality of pulses, and pulse duration has been represented the load current of pfc circuit, and to be used for the charge coil electric current, described coil current is discharged forms an output voltage; And

An oscillator, it has an output and is used for producing described a plurality of pulse with a selected frequency, coil current being discharged to zero, and an input, be used to detect the input signal of pfc circuit to regulate described frequency.

11. pfc circuit according to claim 10, wherein said output voltage are formed on the node, and described pulse has back edge and is used for coil current is discharged on the electric capacity of described node to form described output voltage.

12. pfc circuit according to claim 11, when described load current was constant, described pulsewidth was basic identical.

13. the method for the power factor of an input signal of a calibration comprises:

Utilize clock signal to produce a plurality of pulses, so that set up a charge cycle for coil current, the clock cycle of wherein said clock signal will be longer than the summation of the charge cycle and the discharge cycle of coil current;

On discharge cycle, coil current is discharged to zero to form an output voltage; And

The input signal that detects pfc circuit is to change the described clock cycle.

14. method according to claim 13, the load current of wherein said output voltage is constant, described charging and discharge cycle are added a duty factor with definite described coil current on a clock cycle, and described input signal changes the described clock cycle to keep the product constant of described duty factor and charge cycle.

15. method according to claim 14 also comprises:

With a charging current electric capacity is charged to produce a ramp voltage;

More described ramp voltage and one first reference voltage are to produce described clock signal;

And

The input current of the described input signal of one of mirror image expression, and provide one first image current to change the clock cycle to described electric capacity.

16. comprising, method according to claim 15, wherein said mirror image from described charging current, deduct first image current to change the described clock cycle.

17. method according to claim 16, wherein said mirror image comprise that first saltus step according to described clock signal enables first image current.

Improve described ramp voltage 18. method according to claim 15, wherein said charging comprise with described charging current, and describedly relatively comprise first saltus step that produces described clock signal.

19. method according to claim 15 also comprises:

With a discharging current to described capacitor discharge, to reduce described ramp voltage; And

More described ramp voltage and one second reference voltage are with second saltus step of clocking.

20. method according to claim 18 comprises that also the described input current of mirror image is to provide one second image current, to deduct this image current from described discharging current, to change the described clock cycle.

21. power factor calibration (PFC) circuit comprises:

A basis is used for the pulse width modulator of the clock signal work of synchronous a plurality of pulses, and described a plurality of pulses are set up a coil current from an input voltage, and described coil current is discharged forms an output voltage; And

An oscillator, it has an output and is used for producing described clock signal with certain frequency, and an input is used to detect described coil current to change described frequency.

22. pfc circuit according to claim 21, wherein said clock signal through first saltus step from first logic level to second logic level, through second saltus step from second logic level to first logic level, and described pulse width modulator responds described first saltus step and produces described a plurality of pulse.

23. pfc circuit according to claim 21, wherein said a plurality of pulses have fixing pulsewidth.

24. pfc circuit according to claim 21 also comprises a current path that links to each other with the input of oscillator, is used for the described coil current of conducting to form an induced signal.

25. pfc circuit according to claim 24, wherein said current path comprise a resistance, described induced signal just is formed on this resistance.

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