CN1655018A - Flat panel display and its source driver - Google Patents

Abstract

A source driver is used to receive a clock signal, display data and a control signal to drive a display panel. The source driver includes a receiving device (receiver) and a transmitting device (transmitter). The receiving device receives the clock signal, display data and control signal. The transmitting device is coupled to the receiving device and is used to strengthen the driving capability of the clock signal, display data and control signal received by the receiving device and output them for use by the next source driver connected in series.

Description

Flat panel display and its source driver

technical field

The present invention relates to a flat panel display, and in particular to a source driver of the flat panel display.

Background technique

Flat panel displays (flat panel displays, FPDs) generally have the characteristics of light weight, thin thickness, small size, and power saving, so they can save space in offices or homes. Among various flat panel displays, liquid crystal display (LCD, liquid crystal display) has the most advantages of replacing traditional cathode ray tube (CRT) displays. In order to speed up its popularity and increase its competitiveness, reducing costs has become an inevitable trend.

Taking a liquid crystal display as an example, FIG. 1 is a block diagram of a known liquid crystal display. Please refer to FIG. 1 , a plurality of criss-cross gate channels (gate channel) 121 and a plurality of source channel (source channel) 131 are arranged on the liquid crystal display panel 110, and each gate channel intersects with the source channel. A pixel (not shown). The display state of the pixel is determined by the gate channel signal 121 as the source channel signal 131 during the activation period of the pixel. These gate channel signals 121 are sequentially generated by the gate driver 120 according to the gate control signal G_CONT; each source channel signal 131 is generated by the source driver 130 according to the clock signal CLK , Display data DATA and source control signal (source control signal) CONT are provided. The aforementioned gate control signal G_CONT, clock signal CLK, display data DATA and source control signal CONT are provided by a timing controller (timing controller) 140 .

In order to illustrate the known source driving circuit more clearly, part of the circuit related to the source driving in FIG. 1 is shown in FIG. 1A and FIG. 1B . FIG. 1A is a block diagram showing that part of the circuit related to source driving in FIG. 1 is implemented in a low-impedance circuit (eg, FPC). Please refer to FIG. 1A. In order to consider cost and design flexibility, the source driver 130 is generally implemented by a parallel combination of several integrated circuits (such as source drivers 130_1-130_n in the figure), and each integrated circuit is responsible for providing part of the source channel signal. 131. Each source driver integrated circuit is usually configured on a flexible printed circuit board (FPC, flexible printed circuit board), so various signal buses (CLK, DATA, CONT and Other buses) can transmit signals with lower impedance.

However, the assembly cost of FPC technology is too high, and the production yield is not easy to improve, so the number of FPCs must be reduced. Therefore, a known solution is to dispose each source driver integrated circuit on the liquid crystal display panel, and the circuit between the timing controller and the source driver is implemented with indium tin oxide (ITO). FIG. 1B is a block diagram showing that part of the circuit related to source driving in FIG. 1 is implemented in a high-impedance circuit such as ITO. Please refer to FIG. 1B , since ITO is a signal path with high impedance, the impedance of the ITO signal path is represented by an equivalent resistance in the figure. Therefore, the farther the source drivers ( 130_1 ˜ 130 — n ) are from the timing controller 140 , the greater the impedance between them. In other words, it will result in a reduction in the maximum frequency at which the system can operate.

Contents of the invention

The purpose of the present invention is to provide a source driver (source driver), which can be applied to a high impedance signal path (such as an ITO path on a liquid crystal display panel), reducing the flexible printed circuit used for connecting the timing controller to the liquid crystal display panel The number of boards (FPC, flexible printed circuit board) can be reduced, so the production cost can be reduced. Furthermore, the source driver of the present invention has a transmitter capable of enhancing the signal driving capability, thus overcoming the problem of high impedance of the signal transmission path, thereby increasing the maximum operating frequency of the system.

Another object of the present invention is to provide a flat panel display, in which the source drivers of the present invention are combined in a serial structure, and each stage of the source driver properly enhances the signal driving capability and then transmits the signal to the next stage of the source driver. Therefore, it can be applied to high-impedance signal paths (such as ITO paths on liquid crystal display panels), reducing the number of flexible printed circuit boards (FPC, flexible printed circuit board) used to connect the timing controller to the liquid crystal display panel, and not in the The efficiency is sacrificed, so the assembly cost of the flat panel display can be reduced, and the production yield can be improved.

Another object of the present invention is to provide another source driver, in addition to the aforementioned objects, it also provides options to set the master mode (master mode) or slave mode (slave mode), so as to save power consumption.

Another object of the present invention is to provide another flat panel display. In addition to the aforementioned objects, the operating modes of the source drivers of each level can be adjusted and set to be the main operation according to the allowable range of path impedance and system delay time. mode or slave mode to reduce system power consumption and electromagnetic interference (EMI).

To achieve the above object, the present invention provides a source driver for receiving clock signal, display data and control signal to drive the display panel. The source driver includes a receiver and a transmitter. The receiving device receives clock signals, display data and control signals. The sending device is coupled to the receiving device, and is used to enhance the driving capability of the clock signal, display data and control signal received by the receiving device and then output them for use by another source driver of the next stage.

According to the source driver described in the preferred embodiment of the present invention, the above-mentioned sending device/receiving device may be a differential signal transmitter/differential signal receiver or a transistor Logic signal transmitter (TTL signal transmitter) / transistor transistor logic signal receiver (TTL signal receiver). The above-mentioned transmitting device is more likely to be a voltage mode differential signal transmitter or a current mode differential signal transmitter.

According to the source driver described in a preferred embodiment of the present invention, the above-mentioned sending device may include a data synchronization circuit and a plurality of buffers. The data synchronization circuit synchronizes the timing of the clock signal, display data and control signals received by the receiving device. Each buffer is coupled to the data synchronization circuit, respectively receives the synchronized clock signal, display data and control signal, and outputs after strengthening the signal driving capability, so as to be used by another source driver of the next stage.

According to the source driver described in the preferred embodiment of the present invention, the above-mentioned sending device may include a plurality of voltage buffers (buffers), which respectively receive the clock signal, display data and control signal passing through the receiving device and strengthen the signal driving capability output for another source driver in the next stage.

The present invention further proposes a flat panel display including a display panel, a timing controller and a plurality of source drivers. The timing controller outputs clock signals, display data and control signals. The source drivers are coupled to each other in series structure, and each source driver is coupled to the display panel, and one end of the series structure is further coupled to the timing controller. Each source driver receives the clock signal, display data and control signal to drive the display panel, and at the same time strengthens the drive capability of the received clock signal, display data and control signal respectively and outputs it for another source driver of the next stage use.

According to the flat panel display of the preferred embodiment of the present invention, each of the above-mentioned source drivers includes a receiving device and a sending device. The receiving device receives clock signals, display data and control signals. The sending device is coupled to the receiving device, and is used to enhance the driving capability of the clock signal, display data and control signal passed through the receiving device and output them for use by another source driver of the next stage.

According to the flat panel display of the preferred embodiment of the present invention, the above-mentioned sending device includes a data synchronization circuit and a plurality of buffers. The data synchronization circuit receives and synchronizes the timing of the clock signal, display data and control signal passing through the receiving device. Each buffer is coupled to the data synchronization circuit, respectively receives the synchronized clock signal, display data and control signal, and outputs after strengthening the signal driving capability, so as to be used by another source driver of the next stage.

According to the flat panel display described in the preferred embodiment of the present invention, the above-mentioned sending device includes a plurality of voltage buffers, which respectively receive the clock signal, display data and control signal passing through the receiving device and output them after strengthening the signal driving capability, so as to provide Another source driver of the next stage is used.

According to the flat panel display described in the preferred embodiment of the present invention, the above-mentioned display panel can be an amorphous silicon liquid crystal display panel (α-Si liquid crystal display panel) or a low temperature polysilicon liquid crystal display panel (low temperature poly-silicon liquid crystal display panel) panel).

The present invention also provides a source driver for receiving master-slave setting signals, clock signals, display data and control signals to drive the display panel. The source driver includes a receiving device and a sending device. The receiving device receives clock signals, display data and control signals. The sending device is coupled to the receiving device and receives the master-slave setting signal for determining whether the sending device works in a master mode or a slave mode according to the master-slave setting signal. Among them, in the master mode, the clock signal, display data and control signal of the receiving device are respectively strengthened and then output; while in the slave mode, the clock signal, display data and control signal of the receiving device are separately output. Directly steers the output for use by another source driver in the next stage.

According to the source driver described in the preferred embodiment of the present invention, the above-mentioned sending device/receiving device may be a differential signal transmitter/differential signal receiver, or a transistor-transistor logic signal transmitter/transistor-transistor logic signal receiver device. The above-mentioned transmitting device is more likely to be a voltage mode differential signal transmitter, or a current mode differential signal transmitter.

According to the source driver described in a preferred embodiment of the present invention, the above-mentioned sending device includes a data synchronization circuit and a plurality of buffers. The data synchronization circuit synchronizes the timing of the clock signal, display data and control signals received by the receiving device. Each buffer is coupled to the data synchronization circuit for respectively receiving the synchronized clock signal, display data and control signal and outputting after strengthening the signal driving capability for another source driver of the next stage.

According to the source driver described in the preferred embodiment of the present invention, the above-mentioned sending device includes a plurality of voltage buffers, respectively receiving the clock signal, display data and control signal passing through the receiving device and outputting after strengthening the signal driving capability, for Another source driver of the next stage is used.

The present invention also provides a flat panel display, which includes a display panel, a timing controller, a control circuit and multiple source drivers. The timing controller outputs clock signals, display data and control signals; the control circuit outputs multiple master-slave setting signals. The source drivers are coupled to each other in a serial structure, and each source driver is coupled to the display panel and the control circuit, and one end of the serial structure is further coupled to the timing controller. Each source driver receives the clock signal, display data and control signal to drive the display panel, and each source driver decides whether to use the received clock signal, display data or not according to a corresponding signal among the master-slave setting signals. And the control signal strengthens the driving ability, and then outputs it for another source driver of the next stage.

According to the flat panel display of the preferred embodiment of the present invention, each of the above-mentioned source drivers includes a receiving device and a sending device. The receiving device receives clock signals, display data and control signals. The sending device is coupled to the receiving device and further receives a master-slave setting signal for determining whether the sending device is in a master or slave mode according to the master-slave setting signal. Among them, in the master mode, the clock signal, display data and control signals of the receiving device are respectively strengthened and then output, and the slave mode is output through the clock signal, display data and control signals of the receiving device respectively. The output is directly steered and then fed to another source driver in the next stage.

According to the flat panel display of the preferred embodiment of the present invention, the above-mentioned display panel may be an amorphous silicon liquid crystal display panel or a low temperature polysilicon liquid crystal display panel.

The present invention uses a series connection structure to couple the source drivers to each other, and outputs the received clock signal, display data, and control signal after respectively strengthening the drive capability, so it can be applied to high-impedance signal paths (such as liquid crystal display panels) The ITO path on the top) reduces the number of FPCs used by the timing controller to connect to the LCD panel without sacrificing performance. Therefore, it overcomes the problem of high impedance of the signal transmission path, thereby increasing the highest operating frequency of the system. Further, the assembly cost of the flat panel display is reduced, and the production yield is improved.

The present invention also provides the option to set the source driver in master mode or slave mode, and can adjust and set the source drivers of each level according to the allowable range of path impedance and system delay time. working mode to reduce system power consumption and electromagnetic interference (EMI).

Description of drawings

[Simple description of the diagram]

FIG. 1 is a block diagram of a known liquid crystal display.

FIG. 1A is a block diagram of a part of the circuit related to source driving in FIG. 1 implemented in a low-impedance circuit (eg, FPC).

FIG. 1B is a block diagram of a part of the circuit related to source driving in FIG. 1 implemented in a high impedance circuit (such as ITO).

FIG. 2 is a block diagram of a liquid crystal display according to a preferred embodiment of the present invention.

FIG. 2A is a partial circuit block diagram related to source driving in FIG. 2 .

FIG. 2B is a circuit block diagram showing the source driver in FIG. 2 according to a preferred embodiment of the present invention.

FIG. 2C is a timing diagram illustrating the timing synchronization of the input data of the source driver in FIG. 2B .

FIG. 2D is another circuit block diagram showing the source driver in FIG. 2 according to a preferred embodiment of the present invention.

FIG. 3A is a block diagram of a display source driving circuit according to another preferred embodiment of the present invention.

FIG. 3B is a block diagram of a source driver (set to slave mode) according to another preferred embodiment of the present invention.

FIG. 3C is a block diagram of a source driver (set as the master mode) according to another preferred embodiment of the present invention.

FIG. 3D is a block diagram of another source driver (set in the master mode) according to another preferred embodiment of the present invention.

Detailed ways

In order to make the above and other objects, features and advantages of the present invention more comprehensible, a preferred embodiment will be described in detail below together with the accompanying drawings.

For the convenience of describing the present invention, the following embodiments all take a liquid crystal display (LCD, liquid crystal display) as an example, but this should not limit the scope of application of the present invention.

FIG. 2 is a block diagram of a liquid crystal display according to a preferred embodiment of the present invention. Please refer to FIG. 2 , the liquid crystal display panel 210 is provided with a plurality of criss-cross gate channels (gate channel) 221 and a plurality of source channels (source channel) 231, and each gate channel intersects with the source channel with a Pixel (not shown). The display state of the pixel is determined by the gate channel signal 221 as the source channel signal 231 during the activation period of the pixel. These gate channel signals 221 are sequentially generated by a gate driver (gate driver) 220 according to a gate control signal (gate control signal) G_CONT; each source channel signal 231 is generated by multiple source drivers (sourcedriver) 230 according to a clock signal CLK, display data DATA and source control signal (source control signal) CONT are provided. The aforementioned gate control signal G_CONT, clock signal CLK, display data DATA and source control signal CONT are provided by a timing controller (timing controller) 240 .

In order to illustrate the embodiment of the source driver of the present invention more clearly, part of the circuit related to source driving in FIG. 2 is shown in FIG. 2A . FIG. 2A is a block diagram showing part of the circuit related to source driving in FIG. 2 . Referring to FIG. 2A , the source drivers 230_1 ˜ 230 — n are coupled to each other in a serial structure, and one end of the serial structure (here, the source driver 230_1 ) is coupled to the timing controller 240 . The source drivers 230_1˜230 — n are respectively responsible for providing part of the source channel signal 231 . In the figure, the equivalent resistance R represents the impedance of the signal transmission path, such as the impedance of the indium tin oxide (ITO, indium tin oxide) path on the display panel. Each source driver receives the clock signal CLK, the display data DATA and the control signal CONT to drive the display panel (such as the liquid crystal display panel 210 in FIG. The enhanced drive capability is output for another source driver in the next stage.

The source driver in this embodiment can be implemented with reference to FIG. 2B . FIG. 2B is a circuit block diagram showing the source driver in FIG. 2 according to a preferred embodiment of the present invention. Referring to FIG. 2B , the receiving device 250 in the source driver 230 receives the clock signal CLK, the display data DATA and the control signal CONT output by the timing controller 240 or the previous source driver. The channel driving circuit 260 obtains the clock signal, the display data and the control signal through the receiving device 250 and generates a plurality of source channel signals 231 accordingly. Each source channel signal 231 drives a corresponding source channel. Here, the receiving device 250 and the channel driving circuit 260 can be implemented with known technologies, so details are not repeated here.

The sending device 270 includes, for example, a data synchronization circuit 271 and a buffer 272 in this embodiment. The data synchronization circuit 271 is used for receiving multiple signals and synchronizing the timing of each signal before outputting. Here, for example, the timing of other signals is adjusted based on the clock signal CLK. Each buffer 272 respectively receives and strengthens the driving capability of the corresponding signal before outputting. The clock signal CLK, display data DATA and control signal CONT are received, synchronized and driven by the source driver 230 to be outputted as clock signal OCLK, display data ODATA and control signal OCONT respectively.

FIG. 2C is a timing diagram illustrating the timing synchronization of the input data of the source driver in FIG. 2B . Please refer to FIG. 2B and FIG. 2C at the same time. Here, it is assumed that the display data DATA has two data lines (DATA_x and DATA_y). Since the equivalent resistance and stray capacitance of the DATA_x and DATA_y transmission paths are different, the transfer delay time will be different. As shown in FIG. 2C , DATA_x and DATA_y have a stroke difference of Tskew. After passing through the data synchronization circuit 271 and the buffer 272, the stroke difference between the signals will be compensated, so as not to cause accumulation of transmission delay. As shown in the figure, the data of ODATA_x and ODATA_y are sent out at the same time for use by the next-level source driver.

The signal type transmitted between each source driver in this embodiment is, for example, voltage mode differential signal (voltage mode differential signal), current mode differential signal (current mode differential signal), transistor logic signal (TTL signal) or other signal types.

The source driver in this embodiment can also be implemented with reference to FIG. 2D . FIG. 2D is another circuit block diagram showing the source driver in FIG. 2 according to a preferred embodiment of the present invention. Please refer to FIG. 2D , where the receiving device and the transmitting device are only implemented with a plurality of voltage buffers (buffers) 280 . The source driver 230 receives the clock signal CLK, the display data DATA and the control signal CONT output by the timing controller 240 or the previous source driver. The channel driving circuit 260 obtains the clock signal, the display data and the control signal to generate a plurality of source channel signals 231 , and each source channel signal 231 drives a corresponding source channel. Each voltage buffer 280 respectively receives the clock signal CLK, the display data DATA and the control signal CONT and enhances the driving capability to output the clock signal OCLK, the display data ODATA and the control signal OCONT.

Therefore, the present embodiment can implement the source driver on a high-impedance circuit (such as ITO) without sacrificing performance. Also because the source driver is arranged on the display panel, the number of flexible printed circuit boards (FPC, flexible printed circuit board) is reduced, the assembly cost of the flat panel display is reduced, and the production yield is improved.

In order to reduce power consumption, if the delay time of the signal is within the allowable range of the system, a transmitter can be used to drive a bus structure composed of multiple source drivers. Again, another preferred embodiment is given according to the present invention. FIG. 3A is a block diagram of a display source driving circuit according to another preferred embodiment of the present invention. Referring to FIG. 3A , the source drivers 330_1 - 330_n are coupled to each other in a serial structure, and one end of the serial structure (here, the source driver 330_1 ) is coupled to the timing controller 340 . The source drivers 330_1˜330 — n are respectively responsible for providing part of the source channel signal 331 . In the figure, the equivalent resistance R represents the impedance of the signal transmission path, such as the impedance of the ITO path on the display panel. Each source driver receives the clock signal CLK, the display data DATA and the control signal CONT to drive the display panel (such as the liquid crystal display panel 210 in FIG. 2 ).

Each source driver 330_1-330_n also receives the master-slave setting signal M_S_1-M_S_n respectively, and the working mode of the source driver is determined according to the master-slave setting signal, master mode or slave mode. . If it is set as the main working mode, the received clock signal CLK, display data DATA and control signal CONT are respectively enhanced in drive capability and then output for use by another source driver in the next stage. When the working mode is set as the slave working mode, the received clock signal CLK, display data DATA and control signal CONT are directly output to reduce power consumption. The aforementioned master-slave setting signals M_S_1˜M_S_n are provided by the control circuit 390 .

FIG. 3B is a block diagram of a source driver (set in slave mode) according to another preferred embodiment of the present invention. Referring to FIG. 3B , the source driver 330 receives the clock signal CLK, the display data DATA and the control signal CONT outputted by the timing controller 340 or the previous source driver. The channel driving circuit 360 obtains the clock signal, the display data and the control signal to generate a plurality of source channel signals 331 , and each source channel signal 331 drives a corresponding source channel. The source driver 330 also receives the master-slave setting signal M_S. Here, for example, when the master-slave setting signal M_S is low, the source driver 330 is set to the slave mode; otherwise, when the master-slave setting signal M_S is high, The source driver 330 is set as the main working mode. In the slave working mode, the clock signal CLK, the display data DATA and the control signal CONT received by the source driver 330 are directly output through, for example, a pass line.

When the master-slave setting signal M_S is high, the source driver 330 is set as the master working mode. FIG. 3C is a block diagram of a source driver (set as the main working mode) according to another preferred embodiment of the present invention. Referring to FIG. 3C , the source driver 330 includes a receiving device 350 and a transmitting device 370 . In this embodiment, when the source driver 330 is set to be in the main working mode, its function is similar to that shown in FIG. 2B of the previous embodiment, so it will not be repeated here.

FIG. 3D is a block diagram of another source driver (set as the main working mode) according to another preferred embodiment of the present invention. Please refer to FIG. 3D , where the receiving device and the transmitting device are only implemented with a plurality of voltage buffers (buffers) 380 . The function of FIG. 3D is similar to that of FIG. 2D of the previous embodiment, so it will not be repeated here.

In this embodiment, the working mode of each source driver can be flexibly set according to the allowable range of the system delay time. For example, for a liquid crystal display panel with 10 source drivers, the possible serial connection combinations are M-M-M-M-M-M-M-M-M-M, M-S-M-S-M-S-M-S-M-S, M-S-S-M-S-S-M-S-S-S, M-S-S-S-M-S-S-S-M-S or M-S-S-S-S-M-S-M-S, where the driver is set as the main source driver; , and S means that the source driver is set to slave mode. The above configuration selection can adjust the master-slave setting signal M_S signal level of each source driver according to the path impedance to determine the master/slave working mode. Therefore, this embodiment can reduce system power consumption and electromagnetic interference (EMI).

Although the present invention has been disclosed above with preferred embodiments, it is not intended to limit the present invention. Anyone skilled in the art can make some changes and modifications without departing from the spirit and scope of the present invention. Therefore, this The scope of protection of an invention shall be defined by the scope of the patent applied for.

Claims (46)

1. A source driver for receiving a clock signal, a display data and a control signal to drive a display panel, the source driver comprising: a receiving device for receiving the clock signal, the display data and the control signal; and A sending device, coupled to the receiving device, used to enhance the driving capability of the clock signal, the display data and the control signal received by the receiving device, and output them for another source of the next stage drive used. 2. The source driver as claimed in claim 1, wherein the transmitting device is a differential signal transmitter. 3. The source driver as claimed in claim 2, wherein the receiving device is a differential signal receiver. 4. The source driver as claimed in claim 2, wherein the transmitting device is a voltage mode differential signal transmitter. 5. The source driver as claimed in claim 2, wherein the transmitting device is a current mode differential signal transmitter. 6. The source driver according to claim 1, wherein the transmitting device is a TTL signal transmitter. 7. The source driver according to claim 6, wherein the receiving device is a TTL signal receiver. 8. The source driver as claimed in claim 1, wherein the transmitting device comprises: a data synchronization circuit for synchronizing the timing of the clock signal, the display data and the control signal received through the receiving device; and A plurality of buffers, coupled to the data synchronization circuit, are used to respectively receive the synchronized clock signal, the display data and the control signal and strengthen the signal driving ability to output for another source of the next stage drive used. 9. The source driver as claimed in claim 1, wherein the transmitting device comprises a plurality of voltage buffers, respectively receiving the clock signal, the display data and the control signal passing through the receiving device and strengthening the signals After the drive capability is output, it can be used by another source driver in the next stage. 10. The source driver as claimed in claim 1, wherein the display panel is an α-Siliquid crystal display panel. 11. The source driver as claimed in claim 1, wherein the display panel is a low temperature poly-silicon liquid crystal display panel. 12. A flat panel display (flat panel display, FPD), comprising: a display panel; a timing controller for outputting a clock signal, a display data and a control signal; and A plurality of source drivers, the source drivers are coupled to each other in a serial structure, and the source drivers are all coupled to the display panel, and one end of the serial structure is further coupled to the timing A controller, the source drivers are used to receive the clock signal, the display data and the control signal to drive the display panel, and at the same time respectively enhance the driving capability of the received clock signal, the display data and the control signal The rear output is used by another source driver of the next stage. 13. The flat panel display as claimed in claim 12, wherein each of the source drivers comprises: a receiving device for receiving the clock signal, the display data and the control signal; and A sending device, coupled to the receiving device, used to enhance the driving capability of the clock signal, the display data and the control signal passed through the receiving device and output them for use by another source driver of the next stage . 14. The flat panel display as claimed in claim 13, wherein the transmitting device is a differential signal transmitter. 15. The flat panel display as claimed in claim 14, wherein the receiving device is a differential signal receiver. 16. The flat panel display as claimed in claim 14, wherein the transmitting device is a voltage mode differential signal transmitter. 17. The flat panel display as claimed in claim 14, wherein the transmitting device is a current mode differential signal transmitter. 18. The flat panel display as claimed in claim 13, wherein the transmitting device is a TTL signal transmitter. 19. The flat panel display according to claim 18, wherein the receiving device is a TTL signal receiver. 20. The flat panel display according to claim 13, wherein the sending device comprises: a data synchronization circuit for receiving and synchronizing the timing of the clock signal, the display data and the control signal passing through the receiving device; and A plurality of buffers, coupled to the data synchronization circuit, are used to respectively receive the synchronized clock signal, the display data and the control signal and strengthen the signal driving ability to output for another source of the next stage drive used. 21. The flat panel display according to claim 13, wherein the transmitting device comprises a plurality of voltage buffers, respectively receiving the clock signal, the display data and the control signal passing through the receiving device and strengthening the signals The drive capability is then output for use by another source driver in the next stage. 22. The flat panel display as claimed in claim 12, wherein the display panel is an α-Siliquid crystal display panel. 23. The flat panel display as claimed in claim 12, wherein the display panel is a low temperature poly-silicon liquid crystal display panel (low temperature poly-silicon liquid crystal display panel). 24. A source driver for receiving a master-slave setting signal, a clock signal, a display data and a control signal to drive a display panel, the source driver comprising: a receiving device for receiving the clock signal, the display data and the control signal; and A sending device, coupled to the receiving device and receiving the master-slave setting signal, is used to determine the sending device as a master mode (master mode) and a slave mode (slave mode) according to the master-slave setting signal ) one of the two, wherein, the main working mode is to output the clock signal, the display data and the control signal through the receiving device respectively after strengthening the driving capability, and the slave working mode will pass through the receiving device The clock signal, the display data and the control signal of the device are respectively directly outputted to be used by another source driver of the next stage. 25. The source driver as claimed in claim 24, wherein the transmitting device is a differential signal transmitter. 26. The source driver as claimed in claim 25, wherein the receiving device is a differential signal receiver. 27. The source driver as claimed in claim 25, wherein the transmitting device is a voltage mode differential signal transmitter. 28. The source driver as claimed in claim 25, wherein the transmitting device is a current mode differential signal transmitter. 29. The source driver as claimed in claim 24, wherein the transmitting device is a TTL signal transmitter. 30. The source driver as claimed in claim 29, wherein the receiving device is a TTL signal receiver. 31. The source driver as claimed in claim 24, wherein the transmitting device comprises: a data synchronization circuit for synchronizing the timing of the clock signal, the display data and the control signal received through the receiving device; and A plurality of buffers, coupled to the data synchronization circuit, are used to respectively receive the synchronized clock signal, the display data and the control signal and strengthen the signal driving ability to output for another source of the next stage drive used. 32. The source driver as claimed in claim 24, wherein the transmitting device comprises a plurality of voltage buffers, respectively receiving the clock signal, the display data and the control signal passing through the receiving device and strengthening the signals The drive capability is then output for use by another source driver in the next stage. 33. The source driver as claimed in claim 24, wherein the display panel is an α-Siliquid crystal display panel. 34. The source driver as claimed in claim 24, wherein the display panel is a low temperature poly-silicon liquid crystal display panel. 35. A flat panel display (flat panel display, FPD), comprising: a display panel; a timing controller for outputting a clock signal, a display data and a control signal; a control circuit for outputting a plurality of master-slave setting signals; and A plurality of source drivers, the source drivers are coupled to each other in a serial structure, and the source drivers are all coupled to the display panel and the control circuit, and one end of the serial structure is further coupled connected to the timing controller, the source drivers are used to receive the clock signal, the display data and the control signal to drive the display panel, and each of the source drivers is set according to the corresponding master-slave One of the signals determines whether to enhance the drive capability of the received clock signal, the display data and the control signal, and then output it for use by another source driver of the next stage. 36. The flat panel display as claimed in claim 35, wherein each of the source drivers comprises: a receiving device for receiving the clock signal, the display data and the control signal; and A sending device is coupled to the receiving device and further receives the master-slave setting signal, and is used to determine whether the sending device is a master mode (master mode) and a slave mode (slave) according to the master-slave setting signal mode) one of the two, wherein, the main working mode will be output through the clock signal, the display data and the control signal of the receiving device respectively to strengthen the driving capability, and the slave working mode will be output through the receiving device The clock signal, the display data and the control signal of the device are respectively directly outputted to be used by another source driver of the next stage. 37. The flat panel display as claimed in claim 36, wherein the transmitting device is a differential signal transmitter. 38. The flat panel display as claimed in claim 37, wherein the receiving device is a differential signal receiver. 39. The flat panel display as claimed in claim 37, wherein the transmitting device is a voltage mode differential signal transmitter. 40. The flat panel display as claimed in claim 37, wherein the transmitting device is a current mode differential signal transmitter (current mode differential signal transmitter). 41. The flat panel display as claimed in claim 36, wherein the transmitting device is a TTL signal transmitter. 42. The flat panel display according to claim 41, wherein the receiving device is a TTL signal receiver. 43. The flat panel display as claimed in claim 36, wherein the sending device comprises: a data synchronization circuit for synchronizing the timing of the clock signal, the display data and the control signal received through the receiving device; and A plurality of buffers, coupled to the data synchronization circuit, are used to respectively receive the synchronized clock signal, the display data and the control signal and strengthen the signal driving ability to output for another source of the next stage drive used. 44. The flat panel display as claimed in claim 36, wherein the transmitting device comprises a plurality of voltage buffers, respectively receiving the clock signal, the display data and the control signal passing through the receiving device and strengthening the signals The drive capability is then output for use by another source driver in the next stage. 45. The flat panel display as claimed in claim 35, wherein the display panel is an α-Siliquid crystal display panel. 46. The flat panel display as claimed in claim 35, wherein the display panel is a low temperature poly-silicon liquid crystal display panel (low temperature poly-silicon liquid crystal display panel).

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