CN1647398B

CN1647398B - Systems and methods for symbol clock recovery

Info

Publication number: CN1647398B
Application number: CN038076292A
Authority: CN
Inventors: J·夏; R·W·茨塔; S·M·罗普雷斯托; W·张
Original assignee: Micronas Semiconductors Inc
Current assignee: Micronas Semiconductors Inc
Priority date: 2002-04-05
Filing date: 2003-04-07
Publication date: 2010-05-26
Anticipated expiration: 2023-04-07
Also published as: BR0307917A; WO2003088512A1; CN1647398A; AU2003262124A1; KR20050004801A

Abstract

A system (300) and method for symbol clock recovery independent of segment location recovery uses the frequency and phase information in the upper and lower band edges of a signal to generate a signal (399) for correcting the symbol clock. A particular combination of raised-root cosine filters (320, 330), low-pass filters (348, 368, 397), multipliers (302, 304, 322, 324, 332, 334, 380, 390), and adders (340, 350, 360, 370, 395) effectively uses the tails (d) of a received signal (200) in the frequency domain to correct phase errors.

Description

Systems and methods for symbol clock recovery

对相关申请的参考References to related applications

要求提交于2002年4月5日的共同未决的U.S.临时专利申请60/370,326以及专利号未知的提交于2003年4月4日的U.S.实用新型专利申请的优先权。Priority is claimed to co-pending U.S. Provisional Patent Application 60/370,326, filed April 5, 2002, and U.S. Utility Patent Application, filed April 4, 2003, with unknown patent number.

技术领域technical field

本发明涉及用于解调接收的信号的方法和用于处理接收的信号的系统。The invention relates to a method for demodulating received signals and a system for processing received signals.

背景技术Background technique

在传统上，本地通信是通过线路进行的，因为这提供了一种确保对信息的可靠传递的成本有效的方式。对于长距离通信，需要通过无线电波传输信息。尽管从硬件的立场来看这是方便的，但射频(RF)传输给其带来了涉及损坏信息的问题，并且常常依赖于高功率发射器来克服天气条件、大的建筑物以及来自其它电磁辐射源的干扰。Traditionally, local communication has been over wires, as this provides a cost-effective way of ensuring reliable delivery of information. For long-distance communication, information needs to be transmitted via radio waves. While this is convenient from a hardware standpoint, radio frequency (RF) transmission poses problems involving corrupted information, and often relies on high-power transmitters to overcome weather conditions, large buildings, and other electromagnetic waves. interference from radiation sources.

所开发的各种调制技术提供了有关成本效力和所接收信号的质量的不同解决方案，但直到近期，它们仍主要是模拟的。频率调制和相位调制提供了对噪声的某种免疫力，而振幅调制较为容易被解调。然而，更近些时候，随着低成本微控制器的出现和国内移动电话和卫星通信的引入，数字调制已在普及性上取得进展。借助数字调制技术，出现了传统微处理器电路具有的优于其模拟对等形式的全部优点。通信链路上的问题可通过使用软件来克服。信息可被加密，误差校正可确保所接收的数据中较多的置信度，并且数字信号处理的使用可减小被分配给每个服务的有限带宽。The various modulation techniques developed offer different solutions regarding cost-effectiveness and quality of the received signal, but until recently they were mainly analog. Frequency modulation and phase modulation provide some immunity to noise, while amplitude modulation is easier to demodulate. More recently, however, digital modulation has gained in popularity with the advent of low-cost microcontrollers and the introduction of domestic mobile phones and satellite communications. With the help of digital modulation techniques, all the advantages that traditional microprocessor circuits have over their analog counterparts arise. Problems on the communication link can be overcome by using software. Information can be encrypted, error correction can ensure greater confidence in received data, and the use of digital signal processing can reduce the limited bandwidth allocated to each service.

与传统模拟系统一样，数字调制可使用具有不同优点的振幅、频率或相位调制。由于频率和相位调制技术提供了对噪声的更多的免疫力，它们对于现今使用中的大多数服务是优选的。Like traditional analog systems, digital modulation can use amplitude, frequency or phase modulation with different advantages. Since frequency and phase modulation techniques provide more immunity to noise, they are preferred for most services in use today.

传统模拟频率调制的简单变化可通过将数字信号施加于调制输入来实施。这样，其输出采取两个不同频率的正弦波的形式。为解调该波形，仅仅需要将信号传递经过两个滤波器并将结果变换回逻辑电平。在传统上，数字频率调制的这种形式被称为频移键控。A simple variation of traditional analog frequency modulation can be implemented by applying a digital signal to the modulating input. As such, its output takes the form of two sine waves of different frequencies. To demodulate this waveform, it is only necessary to pass the signal through two filters and convert the result back to logic levels. Traditionally, this form of digital frequency modulation has been called frequency shift keying.

数字相位调制或相位调制键控在频谱上与频率调制很相似。它包含改变所发送的波形的相位而不是频率，这些有限相位变化表示数字数据。以其最简单的形式，相位调制的波形可通过使用数字数据在等频率但相反相位的两个信号之间切换而产生。如果结果波形被乘以等频率的正弦波，则两个分量被产生：一个加倍所接收频率的余弦波形和一个振幅与相移的余弦成比例的频率无关项。这样，滤出较高频率项得到了原始的数字数据。Digital phase modulation or phase modulation keying is spectrally similar to frequency modulation. It involves changing the phase rather than the frequency of the transmitted waveform, and these finite phase changes represent digital data. In its simplest form, a phase-modulated waveform can be generated by using digital data to switch between two signals of equal frequency but opposite phase. If the resulting waveform is multiplied by a sine wave of equal frequency, two components are produced: a cosine waveform that doubles the received frequency and a frequency-independent term whose amplitude is proportional to the cosine of the phase shift. In this way, the original digital data is obtained by filtering out the higher frequency terms.

使相移键控的以上概念更进一步，可能相位的数量可被扩大到二以上。所发送的“载波”可经历任何数量的相位中的变化，并且将所接收的信号乘以等频率的正弦波将把相移解调成频率无关的电压电平。Taking the above concept of phase shift keying a step further, the number of possible phases can be expanded beyond two. The transmitted "carrier" can undergo any number of changes in phase, and multiplying the received signal by a sine wave of equal frequency will demodulate the phase shift into frequency independent voltage levels.

该技术的实例是四相移键控(QPSK)。借助四相移键控，载波在四个相位中变化，并且可由此表示每个相位变化的四个值的任何一个。尽管这可能看起来最初是无意义的，但它提供了这样一种调制方案：使载波能每符号发送二位信息而不是一位，由此有效地加倍载波的数据带宽。An example of this technique is Quadrature Phase Shift Keying (QPSK). With quadrature phase shift keying, the carrier varies in four phases and can thus represent any one of four values for each phase change. Although this may seem initially pointless, it provides a modulation scheme that enables the carrier to send two bits of information per symbol instead of one, thereby effectively doubling the carrier's data bandwidth.

相位调制的信号如何被解调并因此QPSK如何被解调的数学证明在以下被示出。A mathematical proof of how a phase modulated signal and thus QPSK is demodulated is shown below.

欧拉关系式如下表征正弦和余弦波：The Euler relation characterizes sine and cosine waves as follows:

$sin sin ωt ωt = = \frac{{e e}^{jωt jωt} - - {e e}^{- - jt jt}}{22 j j}$ $cos cos ωt ωt = = \frac{{e e}^{jωt jωt} + + {e e}^{- - jωt jωt}}{22}$

其中这样，对相同频率和相位的两个正弦波的乘法由以下给出：in Thus, the multiplication of two sine waves of the same frequency and phase is given by:

${sin sin}^{22} ωt ωt = = \frac{{e e}^{jωt jωt} - - {e e}^{- - jωt jωt}}{22 j j} \times \times \frac{{e e}^{jωt jωt} - - {e e}^{- - jωt jωt}}{22 j j} = = \frac{{e e}^{22 jωt jωt} - - {22 e e}^{00} + + {e e}^{- - 22 jωt jωt}}{- - 44} = = \frac{11}{22} ((\frac{{e e}^{j j ((22 ω ω)) t t} + + {e e}^{- - j j ((22 ω ω)) t t}}{22})) + + \frac{11}{22} . .$

数字接收器通过混合进入的正弦曲线信号与振荡器输出来实施该运算。如以上方程所示，其结果是一个正弦曲线输出，具有输入的二倍的频率和输入的一半的振幅，被叠加于输入振幅的一半的DC偏差上。Digital receivers perform this operation by mixing the incoming sinusoidal signal with the oscillator output. As shown in the above equation, the result is a sinusoidal output with twice the frequency and half the amplitude of the input, superimposed on a DC offset of half the input amplitude.

类似地，将sin(ωt)乘以cos(ωt)得到：Similarly, multiplying sin(ωt) by cos(ωt) gives:

$sin sin ωt ωt \times \times cos cos ωt ωt = = \frac{{e e}^{22 jωt jωt} - - {e e}^{- - 22 jωt jωt}}{44 j j}$

$= = sin sin 22 ωt ωt . .$

其结果是具有输入的二倍的频率的输出正弦曲线，而没有DC偏差。The result is an output sinusoid with twice the frequency of the input, without DC offset.

可以看出，将余弦波乘以任何经相移的正弦波得到“经解调的”波形，其具有输入频率的二倍的输出频率，其DC偏差根据相移φ来变化：It can be seen that multiplying a cosine wave by any phase-shifted sine wave yields a "demodulated" waveform with an output frequency twice the input frequency, whose DC deviation varies according to the phase shift φ:

$sin sin ωt ωt \times \times sin sin ((ωt ωt + + φ φ)) = = \frac{{e e}^{jωt jωt} - - {e e}^{- - jωt jωt}}{22 j j} \times \times \frac{{e e}^{j j ((ωt ωt + + φ φ))} - - {e e}^{- - j j ((ωt ωt + + φ φ))}}{22 j j}$

$= = \frac{{e e}^{j j ((22 ωt ωt + + φ φ))} - - {e e}^{j j ((ωt ωt - - ωt ωt - - φ φ))} {- - e e}^{j j ((ωt ωt + + φ φ - - ωt ωt))} + + {e e}^{- - j j ((22 ωt ωt + + φ φ))}}{- - 44}$

$= = \frac{cos cos ((22 ωt ωt + + φ φ))}{- - 22} - - \frac{{e e}^{jφ jφ} + + {e e}^{- - jφ jφ}}{- - 44}$

$= = \frac{cos cos ((22 ωt ωt + + φ φ))}{- - 22} + + \frac{cos cos φ φ}{22}$

$= = \frac{cos cos φ φ}{22} - - \frac{cos cos ((22 ωt ωt + + φ φ))}{22}$

这样，被施加了变化的相移的载波可通过将载波乘以来自本地振荡器的正弦曲线输出并滤出高频分量而解调成变化的输出电压。不幸的是，相移检测被局限于两个象限；π/2的相移不能被区分于-π/2的相移。因此，为精确地解码存在于所有四个象限中的相移，输入信号需要被乘以正弦曲线和余弦曲线波形两者，高频被滤出，并且数据被重构。将以上方程展开：In this way, a carrier to which a varying phase shift is applied can be demodulated into a varying output voltage by multiplying the carrier by the sinusoidal output from the local oscillator and filtering out the high frequency components. Unfortunately, phase shift detection is limited to two quadrants; a phase shift of π/2 cannot be distinguished from a phase shift of -π/2. Therefore, to accurately decode the phase shift present in all four quadrants, the input signal needs to be multiplied by both the sinusoidal and cosinusoidal waveforms, high frequencies filtered out, and the data reconstructed. Expand the above equation:

$cos cos ((ωt ωt)) \times \times sin sin ((ωt ωt + + φ φ)) = = \frac{{e e}^{jωt jωt} + + {e e}^{- - jωt jωt}}{22} \times \times \frac{{e e}^{j j ((ωt ωt + + φ φ))} + + {e e}^{- - j j ((ωt ωt + + φ φ))}}{22 j j}$

$= = \frac{{e e}^{j j ((22 ωt ωt + + φ φ))} - - {e e}^{j j ((- - φ φ))} + + {e e}^{j j ((φ φ))} - - {e e}^{- - j j ((22 ωt ωt + + φ φ))}}{44 j j}$

$= = \frac{sin sin ((22 ωt ωt + + φ φ))}{22} + + \frac{sin sin φ φ}{22}$

然而，从载波中去除数据并不是对混合器的输出进行低通过滤并将四个电压反馈重构成逻辑电平的简单过程。在实际中，使接收器处的本地振荡器与进入的信号完全同步是不容易的。如果本地振荡器在相位上与进入的信号不同，相矢量图上的信号将经历等于相位差的大小的相位旋转。而且，如果本地振荡器的相位和频率相对于进入的信号不是固定的，则将有相矢量图上的连续旋转。因此，前端解调器的输出一般被馈送到模-数(A/D)转换器中，并且从本地振荡器的相位或频率上的误差而导致的任何旋转在数字信号处理中被去除。However, removing the data from the carrier is not a simple process of low-pass filtering the output of the mixer and reconstructing the four voltage feedbacks to logic levels. In practice, it is not easy to perfectly synchronize the local oscillator at the receiver with the incoming signal. If the local oscillator is out of phase with the incoming signal, the signal on the phase vector diagram will undergo a phase rotation equal to the magnitude of the phase difference. Also, if the phase and frequency of the local oscillator are not fixed relative to the incoming signal, there will be a continuous rotation on the phase vector diagram. Thus, the output of the front-end demodulator is typically fed into an analog-to-digital (A/D) converter, and any rotation resulting from errors in phase or frequency of the local oscillator is removed in digital signal processing.

高级电视系统委员会(“ATSC”)已选择残留边带(“VSB”)作为用于数字电视(“DTV”)的传输标准。在ATSC标准中，8VSB是用于地面广播的标准，而16VSB被用于线缆传输。(国际电信联盟(“ITU”)标准限定五个VSB模式：2、4、8、16和8T)。The Advanced Television Systems Committee ("ATSC") has selected vestigial sideband ("VSB") as the transmission standard for digital television ("DTV"). In the ATSC standard, 8VSB is the standard for terrestrial broadcasting, while 16VSB is used for cable transmission. (The International Telecommunication Union ("ITU") standard defines five VSB modes: 2, 4, 8, 16, and 8T).

典型地，8VSB将三个补充信号用于同步化。首先，它将低电平RF导频用于载波采集。第二，如图1中所示，四符号数据段同步每832个符号被使用一次——就是说，每段一次——用于使数据时钟在频率和相位两者上同步。(典型地，四个符号是被规格化的[1，-1，-1，1])。最后，832符号数据帧同步每313个段被使用一次，用于数据成帧和均衡器训练。数据帧同步亦包括将信号识别为8VSB、16VSB或者其它适当的ITU模式之一的信息。Typically, 8VSB uses three complementary signals for synchronization. First, it uses low-level RF pilots for carrier acquisition. Second, as shown in Figure 1, four-symbol data segment synchronization is used every 832 symbols—that is, once per segment—to synchronize the data clocks in both frequency and phase. (Typically, the four symbols are normalized [1, -1, -1, 1]). Finally, 832-symbol data frame synchronization is used every 313 segments for data framing and equalizer training. Data frame synchronization also includes information identifying the signal as one of 8VSB, 16VSB, or other suitable ITU modes.

导频信号具有0.3dB的功率。尽管导频恢复典型地是可靠的，它可在某些情况下失败，如强的、近处的、缓慢移动的多路情况。The pilot signal has a power of 0.3dB. Although pilot recovery is typically reliable, it can fail in certain situations, such as strong, close-by, slow-moving multipath situations.

从段同步信号进行符号时钟恢复是相对慢的，并且依赖于成功的载波恢复和段位置恢复。此外，尽管一旦载波恢复和段位置恢复被成功地进行，则段同步信号典型地是可靠的，它仍可能在某些情况下失败，包括可能破坏导频信号的多路的种类(或甚至在导频信号尚未受多路的影响的特定实例中)。由于这种多路在广播数字传输可能理想的城市环境中是相对普通的，解决该问题对数字电视的商业发展和其它数字传输系统的改进是重要的。Symbol clock recovery from segment sync signals is relatively slow and depends on successful carrier recovery and segment position recovery. Furthermore, although the segment sync signal is typically reliable once carrier recovery and segment position recovery have been successfully performed, it can still fail in certain situations, including the multipath variety that can corrupt the pilot signal (or even in In the specific instance where the pilot signal has not been affected by multipath). Since such multiplexing is relatively common in urban environments where broadcast digital transmissions may be ideal, solving this problem is important to the commercial development of digital television and the improvement of other digital transmission systems.

因此，需要一种用于符号甚至恢复的新系统和方法，其可从8VSB信号进行符号时钟恢复，即使当段同步信号被完全去除或被严重地改变时，并且独立于载波恢复和段位置恢复。本发明尤其被指向满足这些需要。Therefore, there is a need for a new system and method for symbol even recovery that can perform symbol clock recovery from 8VSB signals even when the segment sync signal is completely removed or severely altered, and is independent of carrier recovery and segment position recovery . The present invention is directed specifically at meeting these needs.

发明内容Contents of the invention

为此，本发明提供一种解调接收的信号的方法，包括：接收数字数据流，其包括表示依照符号时钟采样的接收的信号的数据元素s_t的序列；选择本地频率f；确定a_t＝sin(πt/4)RRC(s_tcos(2πt/f))；确定b_t＝cos(πt/4)RRC(s_tcos(2πt/f))；确定c_t＝cos(πt/4)RRC(s_tsin(2πt/f))；确定d_t＝sin(πt/4)RRC(s_tsin(2πt/f))；提供第一输出信号v_t＝b_t+d_t；以及提供等于L₃(k(a_t-c_t)(sign(L₁(b_t-d_t)))-(a_t+c_t)(sign(L₂(b_t+d_t))))的第二输出信号；其中RRC是根升余弦滤波器；并且L₁、L₂和L₃是具有预定通带的无限脉冲响应低通滤波器。To this end, the invention provides a method of demodulating a received signal, comprising: receiving a digital data stream comprising a sequence of data elements _st representing the received signal sampled according to a symbol clock; selecting a local frequency f; determining _at =sin(πt/4)RRC(s _t cos(2πt/f)); determine b _t =cos(πt/4)RRC(s _t cos(2πt/f)); determine c _t =cos(πt/4 )RRC(s _t sin(2πt/f)); determine d _t =sin(πt/4)RRC(s _t sin(2πt/f)); provide a first output signal v _t =b _t +d _t ; Provides a value equal to L ₃ (k(a _t -c _t )(sign(L ₁ (b _t -d _t )))-(a _t +c _t )(sign(L ₂ (b _t +d _t )))) where RRC is a root raised cosine filter; and L ₁ , L ₂ and L ₃ are infinite impulse response low-pass filters with predetermined passbands.

本发明还提供一种用于处理接收的信号的系统，所述接收的信号具有在0处的期望中心频率、0dB的带宽b₀和-3dB的带宽b₃，该系统包括：模-数转换器，其被配置成采样接收的信号；以及数字信号处理装置，用于产生作为具有频率f_l和f_h的接收的信号的频域分量的函数的时钟调节信号，以使(b₀/2)-b₃＜f_l＜-(b₀/2)，并且(b₀/2)＜f_h＜b₃-(b₀/2)。The invention also provides a system for processing a received signal having a desired center frequency at 0, a bandwidth b ₀ of 0 dB, and a bandwidth b ₃ of -3 dB, the system comprising: analog-to-digital conversion a device configured to sample the received signal; and digital signal processing means for generating a clock adjustment signal as a function of frequency domain components of the received signal having frequencies f _l and f _h such that (b ₀ /2 )-b ₃ <f _l <-(b ₀ /2), and (b ₀ /2)<f _h <b ₃ -(b ₀ /2).

本发明又提供一种解调接收的信号的方法，包括：接收数字数据流，其包括表示依照时钟来采样的接收的信号的数据元素的序列，其中通过时钟调节信号对所述时钟进行频率和/或相位调节；将数据元素的序列乘以目标频率的数字余弦波，并且将结果传递经过第一升根余弦滤波器，以得到第一中间序列；将数据元素的序列乘以目标频率的数字正弦波，并且将结果传递经过第一升根余弦滤波器，以得到第二中间序列；将第一中间序列乘以目标频率四分之一的数字正弦波，以得到第三中间序列；将第一中间序列乘以目标频率四分之一的数字余弦波，以得到第四中间序列；将第二中间序列乘以目标频率四分之一的数字余弦波，以得到第五中间序列；将第二中间序列乘以目标频率四分之一的数字正弦波，以得到第六中间序列；从第三中间序列减去第五中间序列，以得到第七中间序列；从第四中间序列减去第六中间序列，以得到第八中间序列；作为以下各项的乘积，获得第九中间序列：预定常数k；第七中间序列；和将第八中间序列传递经过无限脉冲响应低通滤波器的结果的符号；相加第三中间序列和第五中间序列，以得到第十中间序列；相加第四中间序列和第六中间序列，以得到第十一中间序列；作为以下各项的乘积，获得第十二中间序列：第十中间序列；和将第十一中间序列传递经过无限脉冲响应低通滤波器的结果的符号；相减第九中间序列和第十二中间序列，以得到第十三中间序列；和作为将第十三中间序列传递经过无限脉冲响应低通滤波器的结果的函数，调节时钟。The present invention also provides a method of demodulating a received signal, comprising: receiving a digital data stream comprising a sequence of data elements representing a received signal sampled according to a clock, wherein the clock is frequency summed by a clock adjustment signal /or phase adjustment; multiply the sequence of data elements by the digital cosine wave of the target frequency, and pass the result through the first raised root cosine filter to obtain the first intermediate sequence; multiply the sequence of data elements by the digital of the target frequency sine wave, and pass the result through a first raised root cosine filter to obtain a second intermediate sequence; multiply the first intermediate sequence by a digital sine wave at one quarter of the target frequency to obtain a third intermediate sequence; Multiply an intermediate sequence by a digital cosine wave of one quarter of the target frequency to obtain a fourth intermediate sequence; multiply the second intermediate sequence by a digital cosine wave of one quarter of the target frequency to obtain a fifth intermediate sequence; Multiply the second intermediate sequence by a digital sine wave at one-fourth the frequency of interest to obtain the sixth intermediate sequence; subtract the fifth intermediate sequence from the third intermediate sequence to obtain the seventh intermediate sequence; subtract the fourth intermediate sequence from the fourth intermediate sequence Six intermediate sequences to obtain an eighth intermediate sequence; a ninth intermediate sequence to obtain as a product of: a predetermined constant k; a seventh intermediate sequence; and the result of passing the eighth intermediate sequence through an infinite impulse response low-pass filter the sign of ; add the third intermediate sequence and the fifth intermediate sequence to obtain the tenth intermediate sequence; add the fourth intermediate sequence and the sixth intermediate sequence to obtain the eleventh intermediate sequence; as the product of Twelfth intermediate sequence: the tenth intermediate sequence; and the sign of the result of passing the eleventh intermediate sequence through an infinite impulse response low-pass filter; subtracting the ninth intermediate sequence and the twelfth intermediate sequence to obtain the thirteenth intermediate sequence an intermediate sequence; and adjusting the clock as a function of the result of passing the thirteenth intermediate sequence through an infinite impulse response low pass filter.

附图说明Description of drawings

图1是8VSB数据段的某些特征的图。Figure 1 is a diagram of certain features of an 8VSB data segment.

图2是示出典型VSB信号的某些特征的频域图。Figure 2 is a frequency domain diagram illustrating certain characteristics of a typical VSB signal.

图3是依照本发明用于载波恢复的电路的方块图。Figure 3 is a block diagram of a circuit for carrier recovery in accordance with the present invention.

具体实施方式Detailed ways

为了促进理解本发明的原理，现在将参照在附图中说明的实施例，并且特定的语言将被用于描述它们。尽管如此，将理解没有由此旨在对本发明范围的限制。所说明的设备上的变更和修改以及如在此所说明的本发明原理的进一步应用被预期对本发明所涉及的领域中的技术人员来说将是正常发生的。To facilitate an understanding of the principles of the invention, reference will now be made to the embodiments illustrated in the drawings and specific language will be used to describe them. Nevertheless, it will be understood that no limitation of the scope of the invention is thereby intended. Alterations and modifications in the described devices and further applications of the principles of the invention as described herein are contemplated as will occur normally to those skilled in the art to which the invention pertains.

依照本发明的符号时钟恢复系统提供了强有力的恢复，即使是在由于多路干扰而造成的幻象常见的城市环境中。现有技术系统通常已使用了用于时钟恢复的段同步信号。本发明的符号时钟恢复使用信号的带边缘，因此它独立于段同步，从而使它比从现有技术系统的时钟段同步进行的恢复快且强有力。此外，由于符号时钟恢复独立于段同步，它可在解调过程中的较早时被完成，这又可提高调制其它部分的性能。The symbol clock recovery system according to the present invention provides robust recovery even in urban environments where phantoms due to multipath interference are common. Prior art systems have typically used segment sync signals for clock recovery. The symbol clock recovery of the present invention uses the band edge of the signal, so it is independent of segment sync, making it faster and more robust than recovery from clock segment sync of prior art systems. Furthermore, since symbol clock recovery is independent of segment sync, it can be done earlier in the demodulation process, which in turn can improve the performance of other parts of the modulation.

图2示出了以100概括示出的VSB信号的谱的某些特征。在该实例中，信号200的主要部分210是5.38MHz宽，包括3dB衰减的部分210内的未衰减的部分205。然而，振幅在主频域以外不被完全抑制。在该实例中，一个基本信号存在于信号的主要部分210以上和以下另外的0.31MHz处，该满带以215来指示。这些“带边缘”可被用于载波恢复，如以下所讨论的。FIG. 2 shows certain features of the spectrum of the VSB signal shown generally at 100 . In this example, the main portion 210 of the signal 200 is 5.38 MHz wide, including an unattenuated portion 205 within the 3 dB attenuated portion 210 . However, the amplitude is not completely suppressed outside the dominant frequency domain. In this example, a fundamental signal exists an additional 0.31 MHz above and below the main portion 210 of the signal, the full band being indicated at 215 . These "band edges" can be used for carrier recovery, as discussed below.

图3是以300概括示出的依照本发明的电路的方块图。信号从优选地以符号速率的两倍来运行的A/D转换器(未示出)在301处被输入给电路300。将理解，以符号速率的两倍来采样足以满足Nyquist条件。该上游A/D转换器可以以符号速率的大于两倍来采样其输入信号，但在该点以上硬件频率的增加导致硬件成本的增加而没有性能的对应增加。电路300包括数控振荡器(“DCO”)310，其产生两个信号：sin(ωn)和cos(ωn)，其中“n”是符号计数并且ω＝2π/f。第一乘法器302将输入信号乘以cos(ωn)信号，并且第二乘法器304将输入信号乘以sin(ωn)信号。来自第一和第二乘法器302和304的输出然后被分别传递经过第一和第二根升余弦(“RRC”)滤波器320和330。第一RRC滤波器320的输出在第三乘法器322处被乘以sin(πn/4)，并且在第四乘法器324处被乘以cos(πn/4)。第二RRC滤波器330的输出类似地在第五乘法器332处被乘以sin(πn/4)，并且在第六乘法器334处被乘以cos(πn/4)。FIG. 3 is a block diagram of a circuit according to the invention shown generally at 300 . A signal is input to circuit 300 at 301 from an A/D converter (not shown), preferably operating at twice the symbol rate. It will be appreciated that sampling at twice the symbol rate is sufficient to satisfy the Nyquist condition. The upstream A/D converter can sample its input signal at greater than twice the symbol rate, but an increase in hardware frequency above this point results in an increase in hardware cost without a corresponding increase in performance. Circuit 300 includes a digitally controlled oscillator ("DCO") 310 that generates two signals: sin(ωn) and cos(ωn), where "n" is the symbol count and ω=2π/f. The first multiplier 302 multiplies the input signal by the cos(ωn) signal, and the second multiplier 304 multiplies the input signal by the sin(ωn) signal. The outputs from the first and second multipliers 302 and 304 are then passed through first and second root raised cosine ("RRC") filters 320 and 330, respectively. The output of the first RRC filter 320 is multiplied by sin(πn/4) at the third multiplier 322 and by cos(πn/4) at the fourth multiplier 324 . The output of the second RRC filter 330 is similarly multiplied by sin(πn/4) at the fifth multiplier 332 and by cos(πn/4) at the sixth multiplier 334 .

第六乘法器334的输出由第一累加器340从第三乘法器322的输出减去并且由第三累加器360加给第三乘法器322的输出。第五乘法器332的输出由第二累加器350从来自第四乘法器324的输出并且由第四累加器370加给第四乘法器324的输出。第二累加器350的输出被传递经过第一低通无限脉冲响应(“IIR”)滤波器348，其优选地在大约70kHz处具有-3dB的衰减以滤出带边缘以上的高频分量。The output of the sixth multiplier 334 is subtracted from the output of the third multiplier 322 by the first accumulator 340 and added to the output of the third multiplier 322 by the third accumulator 360 . The output of fifth multiplier 332 is taken from the output of fourth multiplier 324 by second accumulator 350 and added to the output of fourth multiplier 324 by fourth accumulator 370 . The output of the second accumulator 350 is passed through a first low-pass infinite impulse response ("IIR") filter 348, which preferably has a -3dB attenuation at about 70kHz to filter out high frequency components above the band edge.

IIR滤波器348的输出经过第一限制器346。第一限制器346指定值1给任何正输入，并且指定值-1给任何负输入。(本领域的技术人员将认识到这是作为sign()函数)。第一限制器346的输出使用第七乘法器380来乘以第一累加器340的输出。本领域的技术人员将理解，第七乘法器380的输出已被乘以两个RCC滤波器，因此信号在整体上已被有效地乘以平升余弦滤波器。这样，第七乘法器380的输出表示从下带边缘获得的频率和相位校正信息。The output of IIR filter 348 passes through first limiter 346 . The first limiter 346 assigns a value of 1 to any positive input and a value of -1 to any negative input. (Those skilled in the art will recognize this as the sign() function). The output of the first limiter 346 is multiplied by the output of the first accumulator 340 using a seventh multiplier 380 . Those skilled in the art will understand that the output of the seventh multiplier 380 has been multiplied by two RCC filters, so the signal as a whole has effectively been multiplied by a flattened cosine filter. Thus, the output of the seventh multiplier 380 represents the frequency and phase correction information obtained from the lower band edge.

第四累加器370的输出被传递经过第二低通IIR滤波器368，其优选地在70kHz处具有-3dB的衰减以滤出带边缘以上的高频分量。第二低通IIR滤波器368的输出经过第二限制器366。象第一限制器346那样，第二限制器366指定值1给任何正输入，并且指定值-1给任何负输入。第二限制器的输出使用第八乘法器390来乘以第三累加器360的输出。将理解，来自第八乘法器390的输出表示从上带边缘获得的频率和相位校正信息。The output of the fourth accumulator 370 is passed through a second low pass IIR filter 368 which preferably has a -3dB attenuation at 70kHz to filter out high frequency components above the band edge. The output of the second low-pass IIR filter 368 passes through a second limiter 366 . Like the first limiter 346, the second limiter 366 assigns a value of 1 to any positive input and a value of -1 to any negative input. The output of the second limiter is multiplied by the output of the third accumulator 360 using the eighth multiplier 390 . It will be appreciated that the output from the eighth multiplier 390 represents frequency and phase correction information obtained from the upper band edge.

第七乘法器380的输出然后使用第九乘法器385来乘以加权因子“r”。第八乘法器390的输出使用第五累加器395从第九乘法器385的输出中减去。第五累加器395的输出然后被传递经过第三低通IIR滤波器397以产生符号时钟调节信号399，其然后被返回到符号时钟以完成反馈回路。The output of seventh multiplier 380 is then multiplied by a weighting factor "r" using ninth multiplier 385 . The output of the eighth multiplier 390 is subtracted from the output of the ninth multiplier 385 using a fifth accumulator 395 . The output of the fifth accumulator 395 is then passed through a third low pass IIR filter 397 to generate a symbol clock adjustment signal 399, which is then returned to the symbol clock to complete the feedback loop.

本领域的技术人员将认识到，VSB信号的下带边缘包含导频信号。这是加权因子由第九乘法器385来施加的原因。典型地，当k是大约0.3时，上和下带边缘贡献将被适当地平衡。Those skilled in the art will recognize that the lower band edge of the VSB signal contains the pilot signal. This is why the weighting factors are applied by the ninth multiplier 385 . Typically, when k is around 0.3, the upper and lower band edge contributions will be properly balanced.

将进一步理解，由于来自低带边缘的频率和相位信息被包含在第九乘法器385的输出中，并且来自上带边缘的频率和相位信息被包含在第八乘法器390的输出中，因此当上和下带边缘被平衡时，第五累加器的输出被驱动到零，从而使第三低通IIR滤波器397的输出可被用于完成提供符号时钟恢复的反馈环路。It will be further appreciated that since the frequency and phase information from the low band edge is contained in the output of the ninth multiplier 385, and the frequency and phase information from the upper band edge is contained in the output of the eighth multiplier 390, when When the upper and lower band edges are balanced, the output of the fifth accumulator is driven to zero so that the output of the third low pass IIR filter 397 can be used to complete the feedback loop providing symbol clock recovery.

本发明实施上的变化将被本领域的技术人员想起。例如，信号的产生和计算的一些或全部可由特定用途或通用集成电路，或由离散部件，或者以软件来进行。Variations in the practice of the invention will occur to those skilled in the art. For example, some or all of the signal generation and calculations may be performed by application-specific or general-purpose integrated circuits, or by discrete components, or in software.

尽管本发明已被详细说明和描述于附图和以上描述中，它们应被理解成在性质上是说明性的而不是局限性的，应理解仅优选实施例已被示出和描述，并且属于本发明精神范围内的所有变化和修改需要受到保护。While the invention has been illustrated and described in detail in the drawings and foregoing description, it is to be considered illustrative in nature and not restrictive, it being understood that only preferred embodiments have been shown and described, and it is to be understood that All changes and modifications within the spirit of the invention are required to be protected.

Claims

1. A method of demodulating a received signal comprising:

receiving a digital data stream comprising a sequence of data elements _st representing a received signal sampled according to a symbol clock;

select the local frequency f;

Determine a _t = sin(πt/4)RRC(s _t cos(2πt/f));

Determine b _t =cos(πt/4)RRC(s _t cos(2πt/f));

Determine c _t =cos(πt/4)RRC(s _t sin(2πt/f));

Determine d _t = sin(πt/4)RRC(s _t sin(2πt/f));

providing a first output signal v _t =b _t +d _t ; and

Provides a value equal to L ₃ (k(a _t -c _t )(sign(L ₁ (b _t -d _t )))-(a _t +c _t )(sign(L ₂ (b _t +d _t )))) The second output signal of

in

RRC is a root raised cosine filter; and

L ₁ , L ₂ and L ₃ are infinite impulse response low pass filters with their own passbands.

2. The method of claim 1, further comprising adjusting the symbol clock in response to the second output signal.

3. A method of demodulating a received signal comprising:

receiving a digital data stream comprising a sequence of data elements representing a received signal sampled according to a clock, wherein the clock is frequency and/or phase adjusted by a clock adjustment signal;

multiplying the sequence of data elements by a digital cosine wave of the target frequency and passing the result through a first raised root cosine filter to obtain a first intermediate sequence;

multiplying the sequence of data elements by a digital sine wave at the frequency of interest, and passing the result through a first raised root cosine filter to obtain a second intermediate sequence;

Multiply the first intermediate sequence by a digital sine wave at one quarter of the target frequency to obtain the third intermediate sequence;

Multiply the first intermediate sequence by a digital cosine wave of one quarter of the target frequency to obtain the fourth intermediate sequence;

multiply the second intermediate sequence by a digital cosine wave of one quarter of the target frequency to obtain the fifth intermediate sequence;

Multiply the second intermediate sequence by a digital sine wave at one quarter of the target frequency to obtain the sixth intermediate sequence;

subtracting the fifth intermediate sequence from the third intermediate sequence to obtain a seventh intermediate sequence;

subtracting the sixth intermediate sequence from the fourth intermediate sequence to obtain the eighth intermediate sequence;

The ninth intermediate sequence is obtained as the product of:

a predetermined constant k;

the seventh intermediate sequence; and

passing the eighth intermediate sequence through the sign of the result of an infinite impulse response low-pass filter;

adding the third intermediate sequence and the fifth intermediate sequence to obtain the tenth intermediate sequence;

adding the fourth intermediate sequence and the sixth intermediate sequence to obtain an eleventh intermediate sequence;

The twelfth intermediate sequence is obtained as the product of:

the tenth intermediate sequence; and

passing the eleventh intermediate sequence through the sign of the result of an infinite impulse response low-pass filter;

obtaining the difference between said ninth intermediate sequence and said twelfth intermediate sequence to obtain a thirteenth intermediate sequence; and

The clock is adjusted as a function of the result of passing the thirteenth intermediate sequence through an infinite impulse response low-pass filter.