CN1538500A - Semiconductor device, manufacturing method thereof, and testing method of semiconductor device - Google Patents

Abstract

A semiconductor device includes the first layer, a plurality of first test elements which are arranged in the first layer, the second layer which is adhered to the first layer and is different from the first layer, and a plurality of pads which are arranged in the second layer and electrically connected to the first test elements.

Description

Semiconductor device, manufacturing method thereof, and testing method of semiconductor device

technical field

The present invention relates to a semiconductor device having a TEG (Test Element Group), a manufacturing method of the semiconductor device, and a testing method of the semiconductor device.

Background technique

Conventionally, in order to facilitate reliability evaluation of semiconductor devices, etc., TEG (Test Element Group) chips in which elements constituting semiconductor devices (wiring, transistors, capacitors, resistors, etc.) are mounted on a chip have been used.

In the existing TEG chip 10, as shown in FIGS. 13 and 14, a test site (test area) unit 20 and a probe pad unit 30 are formed on one silicon substrate 70.

Here, the test site unit 20 indicates an area where a test element 22 such as a transistor or a capacitor exists, and the probe pad unit 30 indicates an area where a probe pad for piercing a probe exists.

In the conventional TEG chip 10 , one TEG 11 is constituted by a test site unit 20 composed of three test elements 22 and sixteen probe pads 37 . Specifically, three test elements 22 are arranged in the center of the TEG 11, and eight probe pads 37 are arranged on both sides of the test elements 22, respectively. Here, the probe pads 37 are electrically connected to the test elements 22 through wirings and contacts in the insulating films 71, 72, 73, 74, 75, and 76, respectively.

Under the above circumstances, the degree of integration of semiconductor integrated circuits is increasing year by year, and the size of semiconductor devices evaluated by test sites is shrinking. However, the probe pads at the electrical evaluation test site deviated from the trend of shrinking semiconductor devices and maintained their original size.

For example, in the 0.11 μm generation, the size of the probe pads is 80 μm to 100 μm square, and the test site is laid out with an area approximately the same as the area dedicated to the probe pads. Therefore, in the layout of the TEG, the probe pads for measurement occupy a maximum of 60% of the area of the TEG chip. In addition, the probe pad here refers to a pad configured only for the probe.

On the other hand, conventionally, it was difficult to reduce the area of the probe pad because it was not possible to share the probe pad with a plurality of test elements and to evaluate the test site with a common probe card.

Contents of the invention

As described above, in the prior art, the dedicated area of the probe pads in the TEG chip is large, and it is difficult to reduce the area of the probe pads. Therefore, the area where the test site can be formed is small, and the area of the test site is limited due to the probe pad.

A semiconductor device according to a first aspect of the present invention includes: a first layer; a plurality of first test elements disposed in the first layer; a second layer bonded to the first layer and different from the first layer ; and a plurality of pads disposed in the second layer and electrically connected to the first test element.

The method of manufacturing a semiconductor device according to the second aspect of the present invention includes the following steps: a step of forming a first layer having a plurality of first test elements and a second layer having a plurality of pads and being different from the first layer; and a step of laminating the first and second layers and electrically connecting the first test element to the pad.

The manufacturing method of the semiconductor device of the 3rd aspect of this invention has the following process: The process of respectively forming the 1st layer which has a plurality of test elements, and the 2nd layer different from the said 1st layer which has a plurality of pads; a step of electrically connecting the first and second layers and electrically connecting at least a part of the test element to the pad; and a step of evaluating performance of at least a part of the test element.

Description of drawings

FIG. 1A is a plan view showing a TEG chip according to a first embodiment of the present invention.

FIG. 1B is a cross-sectional view of the TEG chip along line IB-IB of FIG. 1A .

Fig. 2A is a plan view showing a test site unit according to the first embodiment of the present invention.

FIG. 2B is a cross-sectional view of the test site unit along line IIB-IIB of FIG. 2A .

3A is a plan view showing a probe pad unit according to the first embodiment of the present invention.

FIG. 3B is a cross-sectional view of the probe pad unit along line IIIB-IIIB of FIG. 2A .

Fig. 4 is a plan view showing a TEG chip according to the first embodiment of the present invention.

FIG. 5A is a plan view showing a related art TEG chip.

5B is a plan view showing the TEG chip of the first embodiment of the present invention.

Fig. 6A is a plan view showing a TEG chip according to a second embodiment of the present invention.

FIG. 6B is a cross-sectional view of the TEG chip along line VIB-VIB of FIG. 6A.

Fig. 7 is a cross-sectional view showing a test site unit according to a second embodiment of the present invention.

8 is a cross-sectional view showing a wiring layer unit according to a second embodiment of the present invention.

9 is a cross-sectional view showing a chip carrier unit according to a second embodiment of the present invention.

10A is a cross-sectional view showing a state in which a test site unit and a wiring layer unit according to the second embodiment of the present invention are bonded together.

10B is a cross-sectional view showing a state in which a test site unit, a wiring layer unit, and a chip carrier unit are bonded according to the second embodiment of the present invention.

Fig. 11 is a plan view showing another TEG chip according to the first and second embodiments of the present invention.

Fig. 12 is a plan view showing another TEG chip according to the first and second embodiments of the present invention.

FIG. 13 is a plan view showing a related art TEG chip.

FIG. 14 is a cross-sectional view of the TEG chip taken along line XIV-XIV in FIG. 13 .

Detailed ways

Embodiments of the present invention will be described below with reference to the drawings. In this description, common reference signs are assigned to common parts in all the drawings.

[First embodiment]

In the first embodiment, a TEG (test element group) chip is constituted by a test site unit and a probe pad unit, and the TEG chip is formed by bonding the test site unit and the probe pad unit together.

A TEG chip according to a first embodiment of the present invention will be described below using FIG. 1A and FIG. 1B .

As shown in FIG. 1A and FIG. 1B, regarding the TEG chip 10 of the first embodiment, after the test site (test area) unit 20 and the probe pad unit 30 are formed respectively, the test site unit 20 and the probe pad unit 30 are bonded together. The pad unit 30 makes it integrated. Here, the so-called test site unit 20 means the region where the test element 22 exists, and the so-called probe pad unit 30 means the region where the probe pad 37 for raising the probe exists.

For example, one TEG 11 of the TEG chip 10 is formed by a test site unit 20 composed of three test elements 22 and sixteen probe pads 37 . Specifically, three test elements 22 are arranged in the center of the TEG 11, and eight probe pads 37 are arranged on both sides of the test elements 22, respectively. Furthermore, the probe pads 37 are electrically connected to the test element 22a via the wirings 24, 35 and the contacts 23, 34, 36 in the insulating films 25, 31, 32, respectively.

Here, the test elements 22 in the test site unit 20 have elements 22 a electrically connected to the probe lands 37 and elements 22 b not electrically connected to the probe lands 37 . Thus, in the first embodiment, unlike the prior art, there are elements 22 b not electrically connected to the probe pads 37 on the silicon substrate 21 below the probe pads 37 . Therefore, in the plan view of the TEG chip 10 , there is a portion where the test element 22 overlaps with the probe pads 37 .

The test site unit according to the first embodiment of the present invention will be described below using FIGS. 2A and 2B .

As shown in FIGS. 2A and 2B , with the test site unit 20 of the first embodiment, the test element 22 is formed on the entire surface of the silicon substrate 21 . Also, wirings (lands) 24 connected to the test element 22 are formed in the insulating film 25 . The upper surface of the wiring 24 is exposed outside the insulating film 25 and serves as a connection portion for electrical connection with the probe pad unit 30 .

The plurality of test elements 22 of the test site unit 20 are separated at predetermined intervals (test site pitch P1 ), and are arranged on the entire TEG chip 10 . Here, the test site pitch P1 is set based on a standard pad set for each generation of each device.

In addition, the test element 22 is, for example, a memory element such as SRAM, DRAM, FeRAM, or MRAM, a capacitor, a resistor, wiring, and the like.

In addition, the surface shape of the test element 22 may be a rectangle as shown in the drawing, or may be changed into various shapes such as a square or a circle.

The probe pad unit according to the first embodiment of the present invention will be described below using FIGS. 3A and 3B .

As shown in FIGS. 3A and 3B, the probe pad unit of the first embodiment is constituted by the probe pad 37 and the multilayer wiring layer. Specifically, the contact 34, the wiring 36, and the probe pad 37 are formed in the insulating films 31 and 32, and the insulating film (passivation) having the opening 38 to expose a part of the upper surface of the probe pad 37 is formed. film) 33. Here, the lower surface of the contact 34 is exposed outside the insulating film 31 and serves as a connection portion electrically connected to the test site unit 20 .

The plurality of probe pads 37 of the probe pad unit 30 are separated at predetermined intervals (land pitches P2) in the row direction (horizontal direction of the paper), and are spaced apart in the column direction (longitudinal direction of the paper). They are spaced at predetermined intervals (land pitch P3 ) and arranged on the entire TEG chip 10 . Here, the pad pitch P2 in the row direction is set based on the standard pad group for each generation of each device. In addition, the pad pitch P3 in the column direction is set based on the minimum pitch of the probes.

A method of manufacturing the TEG chip according to the first embodiment of the present invention will be described below.

First, the test site unit 20 and the probe pad unit 30 are individually formed.

For example, the test site unit 20 is formed as follows. First, test elements 22 such as SRAM and DRAM are formed on a silicon substrate 21 , and the test elements 22 are filled with an insulating film 25 . Then, an opening is formed in the insulating film 25 and the opening is filled with a metal film to form the contact 23 . Furthermore, wiring 24 made of a metal film is formed on contact 23 .

For example, the probe pad unit 30 is formed as follows. First, an opening is formed in the insulating film 31 and the opening is filled with a metal film to form the contact 34 . Next, the wiring 35 connected to the contact 34 is formed. Then, insulating film 32 is formed to bury wiring 35 . Next, an opening is formed in the insulating film 32 , and the opening is filled with a metal film to form a contact 36 . Next, probe pads 37 connected to contacts 36 are formed. Then, after the insulating film 33 is formed on the probe pad 37 , the opening 38 is formed in the insulating film 33 . Thereby, a part of the upper surface of the probe pad 37 is exposed to the outside.

After the test site unit 20 and the probe land unit 30 are individually formed as described above, the test site unit 20 and the probe land unit 30 are bonded together.

Specifically, first, the side opposite to the silicon substrate 21 of the test site unit 20 is made to face the side opposite to the probe pad 37 of the probe pad unit 30 . Then, bonding is performed so that the wiring 24 of the test site unit 20 and the contact 34 of the probe pad unit 30 are in contact with each other. As a result, a part of the test element 22 is electrically connected to the probe pad 37, and the TEG chip 10 is completed.

The method for testing the TEG chip according to the first embodiment of the present invention will be described below.

First, the test site unit 20 and the probe pad unit 30 are individually formed.

Next, the test site unit 20 and the probe pad unit 30 are bonded together, and a part of the test element 22 is electrically connected to the probe pad 37 .

Next, the performance of the test element 22 is evaluated by touching the probes to the probe pads 37 of the probe pad unit 30 .

In such a test method, a plurality of test elements 22 are formed on the test site unit 20 , but the test elements 22 to be evaluated are only elements electrically connected to the probe pads 37 . That is, in the case of FIG. 1B , the test evaluation of the test element 22a electrically connected to the probe pad 37 can be performed, but the test evaluation of the test element 22b not electrically connected to the probe land 37 cannot be performed.

Therefore, in the first embodiment, only the test element 22 to be subjected to test evaluation among the plurality of test elements 22 provided on the TEG chip 10 can be selected for test evaluation. That is, for example, the test evaluation can be performed by selecting an evaluation target by the following method.

First, as shown in FIG. 4, a plurality of test elements 22 are sorted by each element type. Then, the test elements 22 of the same kind are arranged in a row so that different kinds of test elements are arranged in each row.

Here, it is assumed that test elements 22 made of SRAM are arranged in the first group 12a, 12b, 12c, and 12d, test elements 22 made of DRAM are arranged in the second group 13a, 13b, 13c, and 13d, and test elements 22 made of DRAM are arranged in the third group. In 14a, 14b, 14c, and 14d, a test element 22 composed of MRAM is disposed.

In this example, when the test site unit 20 and the probe land unit 30 are attached as shown in FIG. twenty two.

In addition, when the probe pad unit 30 in FIG. 4 is moved to the right of the paper, and the test elements 22 of the second group 13a, 13b, 13c, and 13d are electrically connected to the probe pad 37, Only the test elements 22 made of DRAMs of the second groups 13a, 13b, 13c, and 13d may be evaluated. Similarly, when the probe pad unit 30 of FIG. 4 is moved towards the left direction of the paper, and the test elements 22 of the third group 14a, 14b, 14c, 14d are electrically connected to the probe pad 37, Only the test elements 22 made of MRAM of the third groups 14a, 14b, 14c, and 14d may be evaluated.

According to the above-mentioned first embodiment, the test site unit 20 and the probe pad unit 30 are formed and bonded together. Therefore, the test element 22 can be formed on the silicon substrate 21 regardless of the occupied area of the probe pad 37 . Therefore, the area limitation of the test element 22 caused by the area of the probe pad 37 can be eliminated. Therefore, the following effects can be obtained.

In the prior art, the test elements 22 are arranged at the pitch P1', but in the first embodiment, the test elements 22 can be arranged at the pitch P1 of P1'/N. Therefore, a maximum of N times as many test elements 22 as conventional ones can be arranged on the entire surface of the silicon substrate 21 .

For example, in the case where the test elements 22 of the prior art are arranged at the pitch P1' (see FIG. Figure 5B). Therefore, in this case, a maximum of three times as many test elements 22 as conventional ones can be arranged on the entire surface of the silicon substrate 21 .

Furthermore, since the number of test elements 22 can be increased in this manner, the types of test elements 22 to be evaluated can be increased. This is very effective because a large number of test elements are placed in the same area in a system LSI in which various devices are formed on the same substrate.

In addition, according to the above-mentioned first embodiment, the test elements 22 are classified for each type and the test elements 22 of the same type are arranged in a row, and by adjusting the bonding position of the test part unit 20 and the probe pad unit 30, A component to be evaluated among the plurality of test components 22 is selected.

[Second embodiment]

The second embodiment is an example of the case where area bumps are used. Furthermore, a TEG chip is constituted by a test site unit, a wiring layer unit, and a chip carrier unit, and the TEG chip is formed by bonding the test site unit, the wiring layer unit, and the chip carrier unit together.

In addition, in the second embodiment, the same parts as those in the above-mentioned first embodiment are omitted or simplified, and the different parts are mainly described.

A TEG chip according to a second embodiment of the present invention will be described below using FIGS. 6A and 6B. In addition, solder balls are not shown and omitted in FIG. 6A .

As shown in FIG. 6A and FIG. 6B, regarding the TEG chip 10 of the second embodiment, after the test site unit 20, the wiring layer unit 40, and the chip carrier unit 50 are respectively formed, the test site unit 20, the wiring layer unit 40 and chip carrier unit 50 to make it integrated.

Here, a plurality of test elements 22 in the test site unit 20 are arranged at high density on the silicon substrate 21 . Moreover, a plurality of test elements 22 have elements 22a electrically connected to solder balls 61 via wiring lines 24, 45, 49, 56, 58, 60, contacts 23, 44, 46, 57, 59 and bumps 47 and elements 22a not electrically connected. to component 22b on solder ball 61. Thus, in the second embodiment, there are elements 22b not electrically connected to the solder balls 61 on the silicon substrate 21 under the bumps 47 . Therefore, there is a portion where the test element 22 and the bump 47 overlap in the plan view of the TEG chip 10 .

Fig. 7 shows a test site unit according to a second embodiment of the present invention, but since its structure is the same as that of the above-mentioned first embodiment, its description is omitted.

The wiring layer unit of the second embodiment of the present invention will be described below using FIG. 8 .

As shown in FIG. 8, the wiring layer unit 40 of the second embodiment is composed of bumps 47 and multiple wiring layers. Specifically, contacts 44, 46 and wirings 45, 49 are formed in insulating films 41, 42, and insulating film 43 having openings 48 to expose part of the upper surface of wirings (lands) 49 is formed. Also, bumps 47 are formed on the exposed back surface of the wiring 49 . Here, the lower surface of the contact 44 is exposed outside the insulating film 41 and serves as a connection portion for electrical connection with the test site unit 20 . In addition, the bumps 47 serve as connection portions for electrical connection with the chip carrier unit 50 .

The plurality of bumps 47 and wiring 49 of the wiring layer unit 40 are, for example, the same as in the first embodiment, separated at predetermined intervals (land pitch P2) in the row direction, and separated at predetermined intervals (land pitch P3) in the column direction. ) are separated and arranged on the entire TEG chip 10.

A chip carrier unit according to a second embodiment of the present invention will be described below using FIG. 9 .

As shown in FIG. 9, the chip carrier unit 50 of the second embodiment is constituted by solder balls 61 and multilayer wiring layers. Specifically, contacts 57 and 59 and wirings 56 , 58 and 60 are formed in insulating films 51 , 52 , 53 , 54 and 55 , and solder balls 61 are formed on wiring 60 . Here, the lower surface of the wiring 56 is exposed outside the insulating film 51 and serves as a connection portion for electrical connection with the wiring layer unit 40 .

A method of manufacturing the TEG chip according to the second embodiment of the present invention will be described below.

First, the test site unit 20, the wiring layer unit 40, and the chip carrier unit 50 are individually formed.

For example, the test site unit 20 is formed by the same method as in the above-mentioned first embodiment.

For example, the wiring layer unit 40 is formed as follows. First, an opening is formed in the insulating film 41 and the opening is filled with a metal film to form a contact 44 . Next, the wiring 45 connected to the contact 44 is formed. Then, an insulating film 42 is formed so as to bury the wiring 45 . Next, an opening is formed in the insulating film 42, and the opening is filled with a metal film to form the contact 46 and the wiring 49. FIG. Next, after the insulating film 43 is formed on the wiring 49 , the opening 48 is formed in the insulating film 43 . Then, bumps 47 are formed in the openings 48 .

For example, the chip carrier unit 50 is formed as follows. First, the wiring 56 is formed in the insulating film 51 , and the insulating film 52 is formed on the wiring 56 . An opening is formed in the insulating film 52, and a contact 57 is formed by filling the opening with a metal film. Next, the wiring 58 connected to the contact 57 is formed. Then, an insulating film 53 is formed to bury the wiring 58 . Next, an insulating film 54 is formed on the insulating film 53, an opening is formed in the insulating film 54, and a contact 59 is formed by filling the opening with a metal film. Next, the wiring 60 connected to the contact 59 is formed. Then, an insulating film 55 is formed to bury the wiring 60 . Next, solder balls 61 are formed on the wiring 60 .

As described above, after the test site unit 20 , the wiring layer unit 40 , and the chip carrier unit 50 are individually formed, the test site unit 20 and the wiring layer unit 40 are bonded together as shown in FIG. 10A .

Specifically, first, the side opposite to the silicon substrate 21 of the test site unit 20 is made to face the side opposite to the bump 47 of the wiring layer unit 40 . Then, bonding is performed so that the pads 24 of the test site unit 20 and the contacts 44 of the wiring layer unit 40 are in contact with each other. As a result, a part of the test element 22 is electrically connected to the bump 47 .

Next, as shown in FIG. 10B , the test site unit 20 , the wiring layer unit 40 and the chip carrier unit 50 are attached.

Specifically, first, the side opposite to the bump 47 of the wiring layer unit 40 is made to face the side opposite to the solder ball 61 of the chip carrier unit 50 . Then, bonding is performed so that the bumps 47 of the wiring layer unit 40 and the wirings 56 of the chip carrier unit 50 are in contact with each other. Thus, the TEG chip 10 is completed.

The method of testing the TEG chip according to the second embodiment of the present invention will be described below.

First, the test site unit 20, the wiring layer unit 40, and the chip carrier unit 50 are individually formed.

Next, the test site unit 20 and the wiring layer unit 40 are bonded together, and a part of the test element 22 is electrically connected to the bump 47 .

Next, the test site unit 20 , the wiring layer unit 40 , and the chip carrier unit 50 are bonded together, and electrically connected via a part of the test element 22 , solder balls 61 and bumps 47 .

Next, using the solder balls 61, the performance of the test element 22 was evaluated.

In such a test method, a plurality of test elements 22 are formed on the test site unit 20 , but the test elements 22 to be evaluated are only elements electrically connected to the solder balls 61 . That is, in the case of FIG. 6B , the test evaluation of the test element 22a electrically connected to the solder ball 61 can be performed, but the test evaluation of the test element 22b not electrically connected to the solder ball 61 cannot be performed.

Therefore, in the second embodiment, only the test element 22 to be subjected to test evaluation among the plurality of test elements 22 provided on the TEG chip 10 can be selected for test evaluation.

According to the above-mentioned second embodiment, the test site unit 20, the wiring layer unit 40, and the chip carrier unit 50 are formed and bonded together. Therefore, the test element 22 can be formed on the silicon substrate 21 regardless of the occupied area of the wiring (land). Therefore, the limitation of the area of the test element 22 due to the area of the wiring 49 can be eliminated.

In addition, similarly to the first embodiment, the test elements 22 are classified for each type and the test elements 22 of the same type are arranged in a row. By adjusting the bonding position of the test portion unit 20 and the wiring layer unit 40, multiple Components intended to be evaluated in a test component 22.

In addition, this invention is not limited to each said Example, Various deformation|transformation is possible in the range which does not deviate from the summary in the implementation stage.

For example, when evaluating heat resistance and the like, the TEG chip 10 can be placed in a package.

In addition, the layout of the test elements and pads is not limited to the above-mentioned layout, and may be as follows. For example, as shown in FIG. 11 , it may be a structure in which the test element 22 is surrounded by the probe pads 37 . For example, as shown in FIG. 12 , a U-shaped test element 22 may be surrounded by probe pads 37 .

Additional advantages and modifications of the invention will readily occur to those skilled in the art. Therefore, the invention in its broader aspects is not limited to the specific details and representative embodiments shown and described herein. Accordingly, various modifications may be made without departing from the spirit and scope of the general concept of the invention as defined by the appended claims and their equivalents.

Claims (26)

1. A semiconductor device, characterized in that, possesses: Tier 1; a plurality of first test elements arranged in the above-mentioned first layer; a second layer, bonded to said first layer, said second layer being different from said first layer; and A plurality of pads are provided in the second layer and electrically connected to the first test element. 2. The semiconductor device as claimed in claim 1, further comprising: A plurality of bumps are respectively arranged on the above-mentioned pads; a third layer, bonded to the second layer via the bumps, the third layer being different from the first and second layers; and Solder balls are provided on the third layer and are electrically connected to the first test element. 3. The semiconductor device as claimed in claim 1, characterized in that: All the above-mentioned first test elements are elements of the same type. 4. The semiconductor device as claimed in claim 1, characterized in that: The above-mentioned first test elements are arranged in one row in the first row. 5. The semiconductor device as claimed in claim 1, characterized in that: It further includes a plurality of second test elements provided in the first layer and electrically insulated from the pads. 6. The semiconductor device as claimed in claim 5, characterized in that: All the above-mentioned second test elements are elements of the same type. 7. The semiconductor device as claimed in claim 5, characterized in that: The second test element is a different type of element from the first test element. 8. The semiconductor device as claimed in claim 5, characterized in that: The first test elements are arranged in a row in a first column, and the second test elements are arranged in a row in a second column different from the first row. 9. The semiconductor device as claimed in claim 5, characterized in that: The second test element is provided in the first layer below the pad. 10. The semiconductor device as claimed in claim 1, further comprising: A first connection member disposed in the first layer and connected to the first test element; and A second connection member is provided in the second layer and connected to the pad and the first connection member. 11. The semiconductor device as claimed in claim 2, further comprising: a first connection member disposed in the first layer and connected to the first test element; a second connecting member disposed in said second layer and connected to said pad and said first connecting member; and A third connection member is provided in the third layer and connected to the bumps and the solder balls. 12. A method of manufacturing a semiconductor device, comprising the following steps: A process of separately forming a first layer having a plurality of first test elements and a second layer having a plurality of pads different from the first layer; and A step of attaching the above-mentioned first and second layers and electrically connecting the above-mentioned first test element to the above-mentioned land. 13. The manufacturing method of a semiconductor device as claimed in claim 12, characterized in that: When forming the above-mentioned second layer, a plurality of bumps are respectively formed on the above-mentioned pads, Forming the third layer with solder balls separately from the formation of the above-mentioned first and second layers, After bonding the above-mentioned first and second layers, the above-mentioned second and third layers are bonded, and the above-mentioned first test element is electrically connected through the above-mentioned solder ball and the above-mentioned bump. 14. The manufacturing method of a semiconductor device as claimed in claim 12, characterized in that: All the above-mentioned first test elements are elements of the same type. 15. The manufacturing method of a semiconductor device as claimed in claim 12, characterized in that: The above-mentioned first test elements are formed in one row in the first row. 16. The manufacturing method of a semiconductor device as claimed in claim 12, characterized in that: When the first layer is formed, a plurality of second test elements electrically insulated from the pads are formed in the first layer. 17. The manufacturing method of a semiconductor device as claimed in claim 16, characterized in that: All the above-mentioned second test elements are elements of the same type. 18. The manufacturing method of a semiconductor device as claimed in claim 16, characterized in that: The second test element is a different type of element from the first test element. 19. The manufacturing method of a semiconductor device as claimed in claim 16, characterized in that: The first test elements are arranged in a row in a first column, and the second test elements are arranged in a row in a second column different from the first row. 20. The manufacturing method of a semiconductor device as claimed in claim 16, characterized in that: The second test element is formed in the first layer below the pad. 21. The manufacturing method of a semiconductor device as claimed in claim 12, characterized in that: When forming the above-mentioned first layer, a first connection member connected to the above-mentioned first test element is formed in the above-mentioned first layer, When forming the second layer, a second connection member connected to the land and the first connection member is formed in the second layer. 22. The manufacturing method of a semiconductor device as claimed in claim 13, characterized in that: When forming the above-mentioned first layer, a first connection member connected to the above-mentioned first test element is formed in the above-mentioned first layer, When forming the above-mentioned second layer, a second connection member connected to the above-mentioned pad and the above-mentioned first connection member is formed in the above-mentioned second layer, When the third layer is formed, a third connection member connected to the bump and the solder ball is formed in the third layer. 23. A method for testing a semiconductor device, characterized in that it comprises the following steps: A process of separately forming a first layer having a plurality of test elements and a second layer having a plurality of pads different from the first layer; A step of attaching the above-mentioned first and second layers and electrically connecting at least a part of the above-mentioned test element to the above-mentioned pad; and A step of evaluating the performance of at least a part of the test element. 24. The method for testing a semiconductor device as claimed in claim 23, characterized in that: When forming the above-mentioned second layer, a plurality of bumps are respectively formed on the above-mentioned pads, Forming the third layer with solder balls separately from the formation of the above-mentioned first and second layers, After bonding the first and second layers, the second and third layers are bonded, and at least a part of the test element is electrically connected to the solder balls via the bumps. 25. The testing method of semiconductor device as claimed in claim 23, it is characterized in that: Elements of the same kind among the above-mentioned test elements are respectively formed in a row. 26. The testing method of semiconductor device as claimed in claim 25, it is characterized in that: Among the above-mentioned test elements, the above-mentioned same kind of elements were evaluated separately.

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