CN1536590A

CN1536590A - High quality factor inductive device with shielding pattern embedded in substrate

Info

Publication number: CN1536590A
Application number: CNA031091849A
Authority: CN
Inventors: 杨宗儒; 黄唯夫; 陈幸足; 许长丰; 黄国忠
Original assignee: Silicon Integrated Systems Corp
Current assignee: Silicon Integrated Systems Corp
Priority date: 2003-04-04
Filing date: 2003-04-04
Publication date: 2004-10-13

Abstract

The invention relates to an inductance device with high quality factor, which comprises an insulating layer formed on the surface of a semiconductor substrate, a conductive film formed on the insulating layer and separated from the semiconductor substrate, and a shielding pattern embedded in the semiconductor substrate and comprising a plurality of isolation parts and a plurality of high-concentration doping parts. The isolation parts are distributed in the semiconductor substrate so as to separate the surface of the semiconductor substrate into a plurality of unconnected areas. The high-concentration doped portions are formed in the semiconductor substrate and close to the surface, and are electrically insulated from each other by the isolation portions. The shielding pattern also comprises a plurality of metal silicide layers formed on the plurality of high-concentration doping parts, and an ion injection well for accommodating the plurality of isolation parts and the plurality of high-concentration doping parts.

Description

High Quality Factor Inductive Devices with Shielding Patterns Embedded in Substrate

技术领域technical field

本发明涉及一种电感器件。本发明特别涉及一种用于射频集成电路的电感器件，具有嵌埋于半导体基底中的屏蔽图案，可降低储存于电感器件中的能量损耗，从而增强电感器件的品质因子。The invention relates to an inductance device. The invention particularly relates to an inductance device used in a radio frequency integrated circuit, which has a shielding pattern embedded in a semiconductor substrate, which can reduce energy loss stored in the inductance device, thereby enhancing the quality factor of the inductance device.

背景技术Background technique

在射频集成电路的应用中，不仅需要使用二极管与晶体管等主动器件以及电阻与电容等被动器件，而且需要设置有各种电感器件例如线圈或变压器。图1(a)显示一已知的电感器件10的透视图。参照图1(a)，已知的电感器件10包括有一半导体基底11、一绝缘层12、以及一导电膜13。绝缘层12沉积于半导体基底11上，使导电膜13隔离于半导体基底11。导电膜1 3形成于绝缘层12上，具有两端子A与B，作为电感器件10中用以提供电感效应的电流路径。典型地，导电膜13形成图1(a)所示的螺旋带状，但也可为任意的形状。In the application of radio frequency integrated circuits, not only active devices such as diodes and transistors and passive devices such as resistors and capacitors need to be used, but also various inductive devices such as coils or transformers need to be provided. FIG. 1( a ) shows a perspective view of a known inductive device 10 . Referring to FIG. 1( a ), a known inductor device 10 includes a semiconductor substrate 11 , an insulating layer 12 , and a conductive film 13 . The insulating layer 12 is deposited on the semiconductor substrate 11 to isolate the conductive film 13 from the semiconductor substrate 11 . The conductive film 13 is formed on the insulating layer 12, has two terminals A and B, and serves as a current path for providing an inductive effect in the inductor device 10. Typically, the conductive film 13 is formed in a spiral ribbon shape as shown in FIG. 1( a ), but may have any shape.

图1(b)显示图1(a)所示的已知电感器件的等效电路图。参照图1(b)，符号A与B分别代表导电膜13的两端子。符号Rs与Ls分别代表导电膜13的等效电阻与等效电感。符号Cs代表导电膜13中位于下方的部分和位于上方的部分因相互重叠所造成的等效电容。符号Cox代表半导体基底11与导电膜13间所形成的等效电容。符号Csi与Rsi分别代表半导体基底11的等效电感与等效电阻。图1(b)所示的各等效电路符号也对应地显示于图1(a)中，以更明确显示出每一等效电路符号的物理意义。Fig. 1(b) shows an equivalent circuit diagram of the known inductive device shown in Fig. 1(a). Referring to FIG. 1(b), symbols A and B represent two terminals of the conductive film 13, respectively. The symbols Rs and Ls respectively represent the equivalent resistance and the equivalent inductance of the conductive film 13 . The symbol Cs represents the equivalent capacitance caused by overlapping of the lower portion and the upper portion of the conductive film 13 . The symbol Cox represents the equivalent capacitance formed between the semiconductor substrate 11 and the conductive film 13 . Symbols Csi and Rsi respectively represent the equivalent inductance and equivalent resistance of the semiconductor substrate 11 . The equivalent circuit symbols shown in FIG. 1(b) are also correspondingly displayed in FIG. 1(a), so as to more clearly show the physical meaning of each equivalent circuit symbol.

由电路学理论，图1(b)所示的等效电路可进一步地简化成图1(c)所示的等效电路。参照图1(c)，电容Cox、电容Csi、与电阻Rsi简化成相互并联的电容Cp与电阻Rp。By circuit theory, the equivalent circuit shown in Figure 1(b) can be further simplified into the equivalent circuit shown in Figure 1(c). Referring to FIG. 1( c ), the capacitor Cox, the capacitor Csi, and the resistor Rsi are simplified into a capacitor Cp and a resistor Rp connected in parallel.

${R R}_{p p} = = \frac{11}{{ω ω}^{22} {C C}_{ox ox}^{22} {R R}_{si the si}} + + \frac{{R R}_{si the si} {(({C C}_{ox ox} + + {C C}_{si the si}))}^{22}}{{C C}_{ox ox}^{22}} \cdot &Center Dot; \cdot &Center Dot; \cdot &Center Dot; ((11))$

${C C}_{p p} = = {C C}_{ox ox} \cdot &Center Dot; \frac{11 + + {ω ω}^{22} (({C C}_{ox ox} + + {C C}_{si the si})) {C C}_{si the si} {R R}_{si the si}^{22}}{11 + + {ω ω}^{22} {(({C C}_{ox ox} + + {C C}_{si the si}))}^{22} {R R}_{si the si}^{22}} \cdot &Center Dot; \cdot &Center Dot; \cdot &Center Dot; ((22))$

此外，依据电磁学理论，电感器件10的品质因子Q(Quality Factor)可表示成下列方程式：In addition, according to the electromagnetic theory, the quality factor Q (Quality Factor) of the inductance device 10 can be expressed as the following equation:

$Q Q = = \frac{ω ω {L L}_{s the s}}{{R R}_{s the s}} \cdot &Center Dot; \frac{{R R}_{p p}}{{R R}_{p p} + + [[{((ω ω {L L}_{s the s} / / {R R}_{s the s}))}^{22} + + 11]] {R R}_{s the s}} \cdot &Center Dot; [[11 - - \frac{{R R}_{s the s}^{22} (({C C}_{s the s} + + {C C}_{p p}))}{{L L}_{s the s}} - - {ω ω}^{22} {L L}_{s the s} (({C C}_{s the s} + + {C C}_{p p}))]] \cdot \cdot \cdot &Center Dot; \cdot &Center Dot; ((33))$

其中第二乘项代表半导体基底损耗因子且第三乘项代表自身共振因子。Wherein the second multiplication term represents the dissipation factor of the semiconductor substrate and the third multiplication term represents the self-resonance factor.

从方程式(3)与图1(c)可知，为了获得更高的品质因子Q，必须提高Rp的值且降低Cp的值。再者依据方程式(1)，倘若Rsi减少，也即半导体基底损耗减少，则可使Rp的值增加。基于此理论，近来已经提议配置一屏蔽图案于已知的电感器件10中使得半导体基底的损耗降低(Rsi降低)，从而增加品质因子Q，如下文所述。It can be known from equation (3) and FIG. 1(c) that in order to obtain a higher quality factor Q, the value of Rp must be increased and the value of Cp must be decreased. Furthermore, according to equation (1), if Rsi decreases, that is, the loss of the semiconductor substrate decreases, the value of Rp can be increased. Based on this theory, it has recently been proposed to deploy a shielding pattern in the known inductor device 10 to reduce the loss of the semiconductor substrate (Rsi reduction), thereby increasing the quality factor Q, as described below.

图2显示一已知的屏蔽图案14配置于图1(a)所示的已知电感器件10中的透视图。参照图2，屏蔽图案14嵌埋于绝缘层12中，位于导电膜13的下方。屏蔽图案14由低电阻材料例如金属或多晶硅所形成并且接地而成为一接地电位面。由于屏蔽图案14可阻挡从导电膜13而来的电力线，防止其穿入半导体基底11中，故半导体基底11不会造成能量损耗，也即电阻Rsi好似降低到零。结果，配置有屏蔽图案14的已知电感器件20可获得较高的品质因子Q。FIG. 2 shows a perspective view of a known shielding pattern 14 disposed in the known inductor device 10 shown in FIG. 1( a ). Referring to FIG. 2 , the shielding pattern 14 is embedded in the insulating layer 12 and located under the conductive film 13 . The shielding pattern 14 is formed of low resistance material such as metal or polysilicon and is grounded to form a ground potential plane. Since the shielding pattern 14 can block the electric force from the conductive film 13 and prevent it from penetrating into the semiconductor substrate 11, the semiconductor substrate 11 does not cause energy loss, that is, the resistance Rsi seems to be reduced to zero. As a result, a higher quality factor Q can be obtained for the known inductive device 20 configured with the shield pattern 14 .

然而，屏蔽图案14的配置却造成屏蔽图案14与导电膜13间形成一寄生电容，使得Cp增加，反而导致品质因子Q变差。However, the configuration of the shielding pattern 14 causes a parasitic capacitance to be formed between the shielding pattern 14 and the conductive film 13 , so that Cp increases, and the quality factor Q deteriorates.

发明内容Contents of the invention

为了克服现有技术的不足之处，本发明的一个目的在于提供一种电感器件，设置嵌埋于半导体基底中的屏蔽图案，不仅可降低半导体基底所造成的能量损耗而且可降低屏蔽图案所造成的寄生电容，从而获的相对高的品质因子。In order to overcome the deficiencies of the prior art, an object of the present invention is to provide an inductance device, which is provided with a shielding pattern embedded in the semiconductor substrate, which can not only reduce the energy loss caused by the semiconductor substrate but also reduce the energy loss caused by the shielding pattern. The parasitic capacitance, so as to obtain a relatively high quality factor.

依据本发明的一个实施例，一种高品质因子的电感器件包括一半导体基底、一绝缘层、一导电膜、以及一屏蔽图案。绝缘层形成于半导体基底的表面上方。导电膜形成于绝缘层上且与半导体基底分离。屏蔽图案嵌埋于半导体基底中且包括多个隔离部与多个高浓度掺杂部。多个隔离部分布于半导体基底中，其中每一隔离部具有一底部与一顶部。底部深入半导体基底内且顶部露出于该表面上，从而分隔表面成多个不相连通的区域。多个高浓度掺杂部形成于半导体基底内且靠近该表面，通过多个隔离部而彼此电绝缘。According to an embodiment of the present invention, a high quality factor inductor device includes a semiconductor substrate, an insulating layer, a conductive film, and a shielding pattern. An insulating layer is formed over the surface of the semiconductor substrate. The conductive film is formed on the insulating layer and separated from the semiconductor substrate. The shielding pattern is embedded in the semiconductor substrate and includes a plurality of isolation parts and a plurality of high-concentration doped parts. A plurality of isolation parts are distributed in the semiconductor substrate, and each isolation part has a bottom and a top. The bottom is deep into the semiconductor substrate and the top is exposed on the surface, thereby separating the surface into a plurality of disconnected regions. A plurality of high-concentration doped parts are formed in the semiconductor substrate and close to the surface, and are electrically insulated from each other by a plurality of isolation parts.

屏蔽图案还包括多个硅化金属层，形成于多个高浓度掺杂部上，通过多个隔离部而彼此电绝缘。The shielding pattern further includes a plurality of silicide metal layers formed on the plurality of high-concentration doped parts and electrically insulated from each other by a plurality of isolation parts.

屏蔽图案还包括一离子注入井，形成于半导体基底中，使得多个隔离部与多个高浓度掺杂部都容纳于离子注入井内。The shielding pattern further includes an ion implantation well formed in the semiconductor substrate, so that a plurality of isolation parts and a plurality of high-concentration doped parts are accommodated in the ion implantation well.

根据本发明的屏蔽图案，高浓度掺杂部、离子注入井、以及自行对准硅化金属层都为低电阻结构，使得半导体基底的表面层的电阻降低。结果，可成功地阻挡从导电膜而来的电力线，防止其更深地穿入半导体基底中。因此，半导体基底所造成的能量损耗可显著地降低。因为屏蔽图案嵌埋于半导体基底而非绝缘层中，所以屏蔽图案与导电膜间的距离变得较大。结果，由于屏蔽图案的配置所造成的寄生电容变得较小，而获得相对高的品质因子。According to the shielding pattern of the present invention, the high-concentration doped part, the ion implantation well, and the self-aligned silicide metal layer are all low-resistance structures, so that the resistance of the surface layer of the semiconductor substrate is reduced. As a result, the lines of electric force coming from the conductive film can be successfully blocked from penetrating deeper into the semiconductor substrate. Therefore, the energy loss caused by the semiconductor substrate can be significantly reduced. Since the shield pattern is embedded in the semiconductor substrate instead of the insulating layer, the distance between the shield pattern and the conductive film becomes larger. As a result, the parasitic capacitance due to the configuration of the shield pattern becomes smaller to obtain a relatively high quality factor.

多个隔离部使多个高浓度掺杂部彼此电性绝缘且使多个自行对准硅化金属层彼此电性绝缘。借助该结构，可避免涡电流产生于高浓度掺杂部与自行对准硅化金属层中。The isolation parts electrically insulate the high-concentration doped parts from each other and electrically insulate the self-aligned metal silicide layers from each other. With this structure, eddy current can be avoided from being generated in the high-concentration doped part and the self-aligned silicide metal layer.

附图说明Description of drawings

图1(a)显示已知的电感器件的透视图。Figure 1(a) shows a perspective view of a known inductive device.

图1(b)与1(c)显示图1(a)所示的已知电感器件的等效电路图。1(b) and 1(c) show the equivalent circuit diagram of the known inductor device shown in FIG. 1(a).

图2显示已知的屏蔽图案配置于图1(a)所示的已知电感器件中的透视图。FIG. 2 shows a perspective view of a known shielding pattern configured in the known inductor device shown in FIG. 1( a ).

图3(a)显示依据本发明的具有嵌埋于基底中的屏蔽图案的电感器件的一例子的透视图。FIG. 3( a ) shows a perspective view of an example of an inductor device with a shielding pattern embedded in a substrate according to the present invention.

图3(b)显示依据本发明的屏蔽图案的另一例子的顶视图。Fig. 3(b) shows a top view of another example of the masking pattern according to the present invention.

图4(a)至4(g)显示依据本发明的具有嵌埋于基底中的屏蔽图案的电感器件的一例子的制造方法的剖面图。4( a ) to 4 ( g ) are cross-sectional views showing an example of a manufacturing method of an inductor device having a shielding pattern embedded in a substrate according to the present invention.

组件符号说明：Description of component symbols:

10，20已知电感器件10, 20 known inductance devices

11 半导体基底11 Semiconductor substrate

12 绝缘层12 insulation layer

13 导电膜13 conductive film

14 屏蔽图案14 shield pattern

30 依据本发明的电感器件30 According to the inductance device of the present invention

31 半导体基底31 Semiconductor substrate

32 绝缘层32 insulation layer

33 导电膜33 conductive film

34 屏蔽图案34 shield pattern

35 钝化膜35 passivation film

41 隔离部41 Isolation Department

42 高浓度掺杂部42 High concentration doping part

43 离子注入井43 Ion implantation well

44 自行对准硅化金属层44 self-aligned silicide metal layer

50 氧化垫层50 oxide pad

51 氮化硅层51 silicon nitride layer

52 沟槽52 Groove

具体实施方式Detailed ways

下文中的说明与附图将使本发明的前述与其它目的、特征、与优点更明显。The foregoing and other objects, features, and advantages of the present invention will be more apparent from the following description and accompanying drawings.

现将参照附图详细说明依据本发明的优选实施例。Preferred embodiments according to the present invention will now be described in detail with reference to the accompanying drawings.

图3(a)显示依据本发明的电感器件30的一例子的透视图。参照图3(a)，电感器件30包括一半导体基底31，具有一表面、一绝缘层32、一导电膜33、以及一嵌埋于半导体基底31中的屏蔽图案34。举例而言，半导体基底31由硅所形成且为P型或N型基底。绝缘层32沉积于半导体基底31的表面上方且由绝缘材料例如氧化硅所形成。导电膜33形成于绝缘层32上而与半导体31基底分离。导电膜33由金属或合金所形成，具有两端子A与B，作为电感器件30中用以提供电感效应的电流路径。典型地，导电膜33形成为图3(a)所示的螺旋带状，但也可为任意的形状。FIG. 3(a) shows a perspective view of an example of an inductive device 30 according to the present invention. Referring to FIG. 3( a ), the inductor device 30 includes a semiconductor substrate 31 having a surface, an insulating layer 32 , a conductive film 33 , and a shielding pattern 34 embedded in the semiconductor substrate 31 . For example, the semiconductor substrate 31 is formed of silicon and is a P-type or N-type substrate. The insulating layer 32 is deposited on the surface of the semiconductor substrate 31 and is formed of an insulating material such as silicon oxide. The conductive film 33 is formed on the insulating layer 32 and separated from the base of the semiconductor 31 . The conductive film 33 is formed of metal or alloy, has two terminals A and B, and serves as a current path for providing an inductive effect in the inductor device 30 . Typically, the conductive film 33 is formed in a spiral ribbon shape as shown in FIG. 3( a ), but may have any shape.

屏蔽图案34嵌埋于半导体基底31中，主要形成于半导体基底31的表面层中。屏蔽图案34包括多个隔离部41、多个高浓度掺杂部42、一离子注入井43、以及多个自行对准硅化金属(Salicide)层44。具体而言，多个隔离部41分布于半导体基底31中，其中每一隔离部41具有一底部与一顶部，该底部深入半导体基底31内且顶部露出半导体基底3 1的表面上，从而分隔该表面成多个不相连通的区域。举例而言，多个隔离部41配置成辐射状或彼此垂直。The shield pattern 34 is embedded in the semiconductor substrate 31 and is mainly formed in the surface layer of the semiconductor substrate 31 . The shield pattern 34 includes a plurality of isolation portions 41 , a plurality of high-concentration doped portions 42 , an ion implantation well 43 , and a plurality of self-aligned salicide layers 44 . Specifically, a plurality of isolation portions 41 are distributed in the semiconductor substrate 31, wherein each isolation portion 41 has a bottom and a top, the bottom is deep into the semiconductor substrate 31 and the top is exposed on the surface of the semiconductor substrate 31, thereby separating the The surface is divided into multiple disconnected regions. For example, the plurality of isolation portions 41 are arranged radially or perpendicular to each other.

多个高浓度掺杂部42形成于半导体基底31内且靠近半导体基底31的表面，由多个隔离部41而彼此电绝缘。多个高浓度掺杂部42中每一个的导电型态为N型或P型。多个高浓度掺杂部42形成于由多个隔离部41所分隔的多个不相连通的区域中。因此，多个高浓度掺杂部42可视为配置成一预定的图案。A plurality of high-concentration doped portions 42 are formed in the semiconductor substrate 31 and close to the surface of the semiconductor substrate 31 , and are electrically insulated from each other by the plurality of isolation portions 41 . The conductivity type of each of the plurality of high-concentration doped portions 42 is N-type or P-type. A plurality of high-concentration doped parts 42 are formed in a plurality of disconnected regions separated by a plurality of isolation parts 41 . Therefore, the plurality of high-concentration doped portions 42 can be considered to be arranged in a predetermined pattern.

离子注入井43形成于半导体基底31中位于导电膜33的下方的区域。离子注入井43的深度必须足够深使得多个隔离部41与多个高浓度掺杂部42都容纳于离子注入井43内。离子注入井43为N型井或P型井。The ion implantation well 43 is formed in a region of the semiconductor substrate 31 below the conductive film 33 . The depth of the ion implantation well 43 must be deep enough so that the plurality of isolation portions 41 and the plurality of high-concentration doped portions 42 are accommodated in the ion implantation well 43 . The ion implantation well 43 is an N-type well or a P-type well.

自行对准硅化金属层44形成于多个高浓度掺杂部42中的每一个的表面上，可有效地降低半导体基底31的表面电阻值。举例而言，自行对准硅化金属层44得由硅化钛层所形成。The self-aligned silicide metal layer 44 is formed on the surface of each of the plurality of high-concentration doped portions 42 , which can effectively reduce the surface resistance of the semiconductor substrate 31 . For example, the self-aligned metal silicide layer 44 is formed from a titanium silicide layer.

在本发明中，半导体基底31中位于导电膜33下方的部分表面层嵌埋有屏蔽图案34。包括屏蔽图案34中的高浓度掺杂部42、离子注入井43、以及自行对准硅化金属层44都为低电阻结构，使得半导体基底31的表面层的电阻降低。结果，可成功地阻挡从导电膜33而来的电力线，防止其更深地穿入半导体基底31中。因此，半导体基底31所造成的能量损耗可显著地降低。In the present invention, the shielding pattern 34 is embedded in a part of the surface layer of the semiconductor substrate 31 below the conductive film 33 . The high-concentration doped portion 42 in the shielding pattern 34 , the ion implantation well 43 , and the self-aligned silicide metal layer 44 are all low-resistance structures, so that the resistance of the surface layer of the semiconductor substrate 31 is reduced. As a result, the lines of electric force coming from the conductive film 33 can be successfully blocked from penetrating deeper into the semiconductor substrate 31 . Therefore, energy loss caused by the semiconductor substrate 31 can be significantly reduced.

因为本发明的屏蔽图案34嵌埋于半导体基底31而非绝缘层32中，所以屏蔽图案34与导电膜33间的距离变得较大。结果，由于屏蔽图案34的配置所造成的寄生电容变得较小，克服了已知电感器件20所遭遇的问题而获得相对高的品质因子。Because the shielding pattern 34 of the present invention is embedded in the semiconductor substrate 31 instead of the insulating layer 32 , the distance between the shielding pattern 34 and the conductive film 33 becomes larger. As a result, the parasitic capacitance due to the configuration of the shield pattern 34 becomes smaller, overcoming the problems encountered by the known inductive device 20 and obtaining a relatively high quality factor.

应注意在依据本发明的电感器件30中，屏蔽图案34可仅由多个隔离部41、多个高浓度掺杂部42、与自行对准硅化金属层44所组成而不包括离子注入井43于其中。或者，屏蔽图案34可仅由多个隔离部41与多个高浓度掺杂部42所组成而不包括离子注入井43与自行对准硅化金属层44于其中。It should be noted that in the inductor device 30 according to the present invention, the shielding pattern 34 may only consist of a plurality of isolation portions 41, a plurality of high-concentration doped portions 42, and a self-aligned silicide metal layer 44 without including the ion implantation well 43 in it. Alternatively, the shielding pattern 34 may only consist of a plurality of isolation portions 41 and a plurality of high-concentration doped portions 42 without including the ion implantation well 43 and the self-aligned metal silicide layer 44 therein.

在本发明中，屏蔽图案34中的多个隔离部41使多个高浓度掺杂部42彼此电绝缘且使多个自行对准硅化金属层44彼此电性绝缘。由这种结构，可避免涡电流产生于高浓度掺杂部42与自行对准硅化金属层44中。In the present invention, the plurality of isolation portions 41 in the shielding pattern 34 electrically isolate the plurality of high-concentration doped portions 42 from each other and electrically isolate the plurality of self-aligned silicide metal layers 44 from each other. With this structure, eddy currents can be avoided from being generated in the high-concentration doped portion 42 and the self-aligned metal silicide layer 44 .

应注意屏蔽图案34中的由高浓度掺杂部42与自行对准硅化金属层44所组成的图案不限于图3(a)所示，而为任何可防止涡电流产生的图案。举例而言，图3(b)显示依据本发明的屏蔽图案的另一例子的顶视图。图3(b)中的斜线区域为高浓度掺杂部42、自行对准硅化金属层44、或两者的组合。It should be noted that the pattern composed of the high-concentration doped portion 42 and the self-aligned metal silicide layer 44 in the shielding pattern 34 is not limited to that shown in FIG. 3( a ), but any pattern that can prevent eddy current generation. For example, FIG. 3( b ) shows a top view of another example of the shielding pattern according to the present invention. The hatched area in FIG. 3( b ) is the high-concentration doped portion 42 , the self-aligned metal silicide layer 44 , or a combination of both.

下文将参照图4(a)至4(g)详细说明依据本发明的具有嵌埋于基底中的屏蔽图案的电感器件的一例子的制造方法。Hereinafter, a method for manufacturing an example of an inductor device having a shielding pattern embedded in a substrate according to the present invention will be described in detail with reference to FIGS. 4( a ) to 4 ( g ).

如图4(a)所示，准备一P型硅基底31。在P型硅基底31的表面中预定形成依据本发明的电感器件30的区域上依序形成一氧化垫层50与一氮化硅层51。举例而言，氧化垫层50的厚度约为110埃而氮化硅层51的厚度约为1200埃。As shown in FIG. 4(a), a P-type silicon substrate 31 is prepared. An oxide pad layer 50 and a silicon nitride layer 51 are sequentially formed on the surface of the P-type silicon substrate 31 where the inductor device 30 according to the present invention is to be formed. For example, the thickness of the pad oxide layer 50 is about 110 angstroms and the thickness of the silicon nitride layer 51 is about 1200 angstroms.

如图4(b)所示，由蚀刻去除氮化硅层51、氧化垫层50、与P型硅基底31的一部分，以形成多个沟槽52于P型硅基底31中。举例而言，每一沟槽52的从P型硅基底31的表面起算的深度约为3600埃。As shown in FIG. 4( b ), the silicon nitride layer 51 , the pad oxide layer 50 , and a part of the P-type silicon substrate 31 are removed by etching to form a plurality of trenches 52 in the P-type silicon substrate 31 . For example, the depth of each trench 52 from the surface of the P-type silicon substrate 31 is about 3600 angstroms.

如图4(c)所示，由高密度等离子体使氧化物填满多个渠沟52以形成多个浅沟槽隔离部41。As shown in FIG. 4( c ), a plurality of trenches 52 are filled with oxide by high-density plasma to form a plurality of STIs 41 .

如图4(d)所示，去除剩余的氧化层垫50与氮化硅层51，以露出P型硅基底31中未形成有多个浅沟槽隔离部41的表面。As shown in FIG. 4( d ), the remaining oxide layer pad 50 and silicon nitride layer 51 are removed to expose the surface of the P-type silicon substrate 31 where the plurality of STIs 41 are not formed.

如图4(e)所示，由第一离子注入(如图中的箭头所示)形成一N型离子注入井43于P型硅基底31中。N型离子注入井43的深度控制成大于浅沟槽隔离部41的深度。随后，由第二离子注入(如图中的箭头所示)形成多个N型高浓度掺杂部42。N型高浓度掺杂部42的深度控制成小于浅沟槽隔离部41的深度，使得多个N型高浓度掺杂部42由多个浅沟槽隔离部41相互电性绝缘。As shown in FIG. 4( e ), an N-type ion implantation well 43 is formed in the P-type silicon substrate 31 by the first ion implantation (shown by the arrow in the figure). The depth of the N-type ion implantation well 43 is controlled to be greater than the depth of the shallow trench isolation portion 41 . Subsequently, a plurality of N-type high-concentration doped portions 42 are formed by second ion implantation (shown by arrows in the figure). The depth of the N-type high-concentration doped portion 42 is controlled to be smaller than the depth of the shallow trench isolation portion 41 , so that the plurality of N-type high-concentration doped portions 42 are electrically isolated from each other by the plurality of shallow trench isolation portions 41 .

如图4(f)所示，由已知的自行对准硅化金属工艺而形成多个自行对准硅化金属层44于多个N型高浓度掺杂部42上。多个自行对准硅化金属层44由多个浅沟槽隔离部41相互电绝缘。As shown in FIG. 4( f ), a plurality of self-aligned metal silicide layers 44 are formed on the plurality of N-type high-concentration doped portions 42 by a known self-aligned metal silicide process. The plurality of self-aligned suicide metal layers 44 are electrically isolated from each other by the plurality of shallow trench isolations 41 .

如图4(g)所示，一绝缘层32沉积于P型硅基底31的表面上，从而覆盖多个浅沟槽隔离部41与多个自行对准硅化金属层44。随后，在绝缘层32上形成一螺旋带状的导电膜33。因而，完成依据本发明的电感器件30。为了保护电感器件30，要形成一钝化膜35以覆盖螺旋带状的导电膜33。As shown in FIG. 4( g ), an insulating layer 32 is deposited on the surface of the P-type silicon substrate 31 to cover the STIs 41 and the self-aligned metal silicide layers 44 . Subsequently, a conductive film 33 in the shape of a spiral ribbon is formed on the insulating layer 32 . Thus, the inductance device 30 according to the present invention is completed. In order to protect the inductance device 30, a passivation film 35 is formed to cover the conductive film 33 in the form of a spiral ribbon.

虽然本发明已由优选实施例作为例示加以说明，应了解的是：本发明不限于此被揭示的实施例。相反，本发明意欲涵盖对于本领域技术人员而言明显的各种修改与相似配置。因此，申请专利范围的范围应根据最广泛的诠释，以包容所有此类修改与相似配置。While the present invention has been described by way of illustration of preferred embodiments, it is to be understood that the invention is not limited to the disclosed embodiments. On the contrary, the invention is intended to cover various modifications and similar arrangements apparent to those skilled in the art. Accordingly, the scope of claims should be accorded the broadest interpretation to encompass all such modifications and similar arrangements.

Claims

1. high-quality-factor inductance component comprises:

The semiconductor substrate has a surface;

One insulating barrier is formed at the described surface at the described semiconductor-based end;

One conducting film is formed on the described insulating barrier and is located away from the described semiconductor-based end, and described conducting film has two-terminal and as a current path; And

One shielding pattern was embedded in the described semiconductor-based end, comprising:

A plurality of isolation parts, be distributed in, wherein each isolation part has a bottom and a top at described the semiconductor-based end, and described bottom is goed deep at described the semiconductor-based end and described top is exposed on the described surface, become a plurality of zones that are not connected thereby separate described surface, and

A plurality of high-concentration dopant portion is formed at at described the semiconductor-based end and near described surface, is electrically insulated each other by described a plurality of isolation parts.

2. high-quality-factor inductance component according to claim 1, wherein said a plurality of isolation parts are configured to radial.

3. high-quality-factor inductance component according to claim 1, wherein said a plurality of isolation parts are configured to the shape that is perpendicular to one another.

4. high-quality-factor inductance component according to claim 1, wherein said shielding pattern also comprises:

A plurality of metal silicide layers are formed in the described a plurality of high-concentration dopant portion, are electrically insulated from each other by described a plurality of isolation parts.

5. high-quality-factor inductance component according to claim 4, each in wherein said a plurality of metal silicide layers is formed by aiming at metal silicide layer voluntarily.

6. high-quality-factor inductance component according to claim 1, wherein said shielding pattern also comprises:

One ion injects well, is formed at at described the semiconductor-based end, makes described a plurality of isolation part and described a plurality of high-concentration dopant portion all be contained in described ion and injects into well.

7. high-quality-factor inductance component according to claim 6, the conductivity at the wherein said semiconductor-based end are that conductivity that P type, described ion inject well is that each conductivity of N type and described a plurality of high-concentration dopant portion is the N type.

8. high-quality-factor inductance component according to claim 6, the conductivity at the wherein said semiconductor-based end are that conductivity that P type, described ion inject well is that each conductivity of N type and described a plurality of high-concentration dopant portion is the P type.

9. high-quality-factor inductance component according to claim 6, the conductivity at the wherein said semiconductor-based end are that conductivity that N type, described ion inject well is that each conductivity of P type and described a plurality of high-concentration dopant portion is the P type.

10. high-quality-factor inductance component according to claim 6, the conductivity at the wherein said semiconductor-based end are that conductivity that N type, described ion inject well is that each conductivity of P type and described a plurality of high-concentration dopant portion is the N type.