CN1523799A

CN1523799A - Device and method for generating slave synchronization code in common channel of baseband chip

Info

Publication number: CN1523799A
Application number: CNA03103988XA
Authority: CN
Inventors: 刚李; 李刚; 王小璐; 汪浩
Original assignee: Huawei Technologies Co Ltd
Current assignee: HiSilicon Technologies Co Ltd
Priority date: 2003-02-18
Filing date: 2003-02-18
Publication date: 2004-08-25
Anticipated expiration: 2023-02-18
Also published as: CN1272925C

Abstract

一种基带芯片公共信道中产生从同步码的装置和方法，其中，m为不小于0的整数，所述装置包括：至少一个与逻辑运算单元和一个异或运算单元；一个获取装置，用于获取任意数对应的二进制数的各比特对应的二进制数；其中，为得到所述矩阵的第n行i列的值hn(i)时，所述获取装置分别获取所述n和i的0到m－1比特对应的二进制数，将获取的所述n和i对应二进制数的相同比特由所述与逻辑运算单元分别求与，将所述分别求与的0到m－1个状态通过所述异或运算单元后获取所述hn(i)，其中所述n和i为大于等于0小于2^m的整数。利用本发明，当存储的数据量大时，可大大节省寄存器资源的消耗。A device and method for generating synchronous codes in a common channel of a baseband chip, wherein m is an integer not less than 0, and the device includes: at least one AND logic operation unit and an exclusive OR operation unit; an acquisition device for Obtain the binary number corresponding to each bit of the binary number corresponding to any number; wherein, when obtaining the value hn(i) of the nth row i column of the matrix, the obtaining means obtains the 0 to i of the n and i respectively. For the binary number corresponding to the m-1 bit, the same bit of the acquired binary number corresponding to n and i is separately summed by the AND logic operation unit, and the 0 to m-1 states of the summation are respectively summed through the said AND logic operation unit The hn(i) is obtained after the XOR operation unit, wherein the n and i are integers greater than or equal to 0 and less than 2 ^m . Utilizing the invention, when the amount of stored data is large, the consumption of register resources can be greatly saved.

Description

Apparatus and method for generating secondary synchronization code in common channel of baseband chip

Technical Field

The present invention relates to an apparatus and method for generating a Secondary Synchronization Code (SSC), and more particularly, to an apparatus and method for generating a Secondary Synchronization Code (SSC) in a baseband chip common channel.

Background

In the design of the WCDMA base station baseband modulation chip common channel modulation circuit, a plurality of secondary synchronization codes SSCs need to be generated, and according to the 3G25.213 protocol, 16 spare secondary synchronization codes SSCs are required to be generated, { Csc 1,.. and Csc 16}, which are complex value sequences with the same real part and imaginary part and are generated by Hadamard (Hamming) sequences. And hamming sequences are obtained by generating z-sequences. Define the z sequence as:

z＝<b，b，b，-b，b，b，-b，-b，b，-b，b，-b，-b，-b，-b，-b>，

wherein:

b＝<x1，x2，x3，x4，x5，x6，x7，x8，-x9，-x10，-x11，-x12，-x13，-x14，-x15，-x16>。

wherein,x1， x 2.. x 15.. x16 is the same as the definition of a sequence of PSC (Primary synchronization code) code, i.e.

a＝<x1，x2，x3，...，x16>＝<1，1，1，1，1，1，-1，-1，1，-1，1，-1，1，-1，-1，1>

From the a-sequence, it can be calculated:

b＝<1，1，1，1，1，1，-1，-1，，-1，1，-1，1，-1，1，1，-1>。

in general, a Hadamard sequence is generated by the rows of the matrix H8:

H₀＝(1)

<math> <mrow> <msub> <mi>H</mi> <mi>k</mi> </msub> <mo>=</mo> <mfenced open='[' close=']'> <mtable> <mtr> <mtd> <msub> <mi>H</mi> <mrow> <mi>k</mi> <mo>-</mo> <mn>1</mn> </mrow> </msub> </mtd> <mtd> <msub> <mi>H</mi> <mrow> <mi>k</mi> <mo>-</mo> <mn>1</mn> </mrow> </msub> </mtd> </mtr> <mtr> <mtd> <msub> <mi>H</mi> <mrow> <mi>k</mi> <mo>-</mo> <mn>1</mn> </mrow> </msub> </mtd> <mtd> <msub> <mrow> <mo>-</mo> <mi>H</mi> </mrow> <mrow> <mi>k</mi> <mo>-</mo> <mn>1</mn> </mrow> </msub> </mtd> </mtr> </mtable> </mfenced> <mo>,</mo> <mi>k</mi> <mo>&GreaterEqual;</mo> <mn>1</mn> </mrow> </math>

where the rows of the matrix are numbered starting from the top row 0 (full 1 sequence). The Hadamard sequences of order n are denoted as a row of the matrix H8, numbered from the top, n being 0, 1, 2,.. 255, and the i-th symbols of the sequences hn and z being denoted as hn (i) and z (i), i being 0, 1, 2,.. 255, i being 0 for the leftmost symbol.

The kth SSC code, Cssck,

k

1, 2, 3.

Cssck＝(1+j)<hm(0)’z(0)，hm(1)’z(1)，hm(2)’z(2)，...，hm(255)’z(255)>

Where m-16 x (k-1) and the leftmost chip of the sequence correspond to the chip transmitted first in time.

Fig. 1 depicts a schematic block diagram of a prior art apparatus for generating a secondary synchronization channel code. Fig. 2 depicts a schematic circuit diagram of a b-sequence generator, a z-sequence generator and a control unit in the apparatus for generating a slave synchronization channel code of fig. 1. According to fig. 1 and 2, the b-sequence generator 1 comprises a 2-input multiplexer and shift registers, and is generated by shifting the b-sequence in the synchronization code by one bit per system clock cycle from 16 fixed shift registers triggered by the external signal ssc _ sync, and the counter count [7:0] in the control unit 3 starts counting from 0 to 255 triggered by the external signal ssc _ sync to generate the correlation control. The function performed by the Z sequence generator 2 is to send b sequences every 16 system clock cycles or to invert b sequences, according to Z (i) in the equation for Cssck.

Therefore, the key to obtaining Cssck is how to compute the matrix H8. Fig. 3 is a schematic diagram of a storage device for obtaining a matrix H8 by using a table lookup method in the prior art. Since the matrix sequence H8 is actually a 256 × 256 matrix, a table lookup method can be adopted to query data corresponding to a row and a column according to a row number (address of the RAM) and a column number (corresponding bit in the RAM). The matrix can be realized by a table look-up method, and data corresponding to a certain row and a certain column are inquired according to a row number (the address of the RAM) and a column number (a corresponding bit in the RAM).

In the prior art, the method of generating the matrix sequence H8 by using the table lookup method consumes a large amount of register resources. As in the above application, to implement a 256 by 256 matrix, the registers consumed are 8192 bytes.

Disclosure of Invention

The object of the present invention is to overcome the above-mentioned drawbacks of the prior art and to provide an apparatus and method for generating Secondary Synchronization Codes (SSCs), i.e. Hadamard sequence matrices, in a baseband chip common channel, which enables real-time calculation of the values of the corresponding positions for a regular matrix with known row and column numbers, using simple logic.

The present invention provides a method for generating Secondary Synchronization Code (SSC), i.e. generating 2, in common channel of baseband chip^mApparatus for each element of an order Hadamard sequence matrix, wherein m is an integer no less than 0, the apparatus comprising:

at least one AND logic operation unit and one XOR operation unit;

an acquiring means for acquiring a binary number corresponding to each bit of a binary number corresponding to an arbitrary number;

when obtaining the value hn (i) of the n-th row and i-th column of the matrix, the obtaining device respectively obtains binary numbers corresponding to bits from 0 to m-1 of the n and i, respectively ANDies the same bits of the obtained binary numbers corresponding to the n and i by the AND logic operation unit, and obtains the hn (i) after passing the states from 0 to m-1 respectively ANDed through the XOR operation unit, wherein the n and i are more than or equal to 0 and less than 2^mIs an integer of (1).

Optionally, when m is 1, n and i are integers less than 2; said device comprising two-input and logic arithmetic units and an exclusive or arithmetic unit, according to the elements of said rows (n) and columns (i) of the 2 nd order Hadamard sequence matrix to be obtained, the two-input and logic operation units input the corresponding bits from the 1 st bit to the 2 nd bit of the binary numbers of the row (n) and the column (i) respectively, namely, the input of one two-input and logic operation unit is the 1 st bit of the binary number of the row (n) and the column (i), respectively, the input of the other two-input and logic operation unit is the 2 nd bit of the binary number of the row (n) and the column (i), respectively, the output end of the one two-input and logic operation unit and the output end of the other two-input and logic operation unit are respectively connected to the input end of the exclusive-or operation unit, and the output end of the exclusive-or operation unit outputs corresponding elements.

Preferably, when m is increased by 1, the apparatus includes one increased and logic operation unit to perform an increased 1-bit and logic operation of the rows (n) and columns (i).

Optionally, when m is increased by 1, the apparatus includes one increased two-input and logic operation unit to perform an increased 1-bit and logic operation of the rows (n) and columns (i).

Preferably, the device further comprises an additional exclusive or operation unit for performing exclusive or operation of the additional two inputs and the output of the logic operation unit.

In addition, a synchronization code (SSC) generated in a common channel of a baseband chip is generated 2^mApparatus for each element of an order Hadamard sequence matrix, wherein m is an integer no less than 0, the apparatus comprising:

a processor unit for performing an and logic operation and an xor operation;

a storage means for storing a binary number corresponding to each bit of a binary number corresponding to an arbitrary number;

when obtaining the value hn (i) of the n-th row and i-th column of the matrix, the processor unit reads the binary numbers corresponding to the bits from 0 to m-1 of the n and i stored in the storage device, respectively ANDies the same bits of the binary numbers corresponding to the read n and i by the processor unit, and obtains the hn (i) after carrying out XOR operation on the 0 to m-1 states respectively ANDed, wherein the n and i areLess than 2^mIs an integer of (1).

The present invention also provides a method for generating a synchronization code (SSC) 2 in a common channel of a baseband chip^mA method of ordering elements in a Hadamard-sequence matrix, wherein m is an integer no less than 0, the method comprising:

when the value hn (i) of the n row and the i column of the matrix needs to be obtained;

obtaining binary numbers corresponding to bits from 0 to m-1 of the n and the i;

respectively solving the same bits of binary numbers corresponding to the n and the i which are obtained by the OR;

performing exclusive or operation on all the states from 0 to m-1 respectively obtained by the summation;

outputting said hn (i), wherein n and i are less than 2^mIs an integer of (1).

Optionally, the step of obtaining binary numbers corresponding to bits 0 to m-1 of n and i includes the steps of: obtaining the least significant bit of the n and i binary numbers and obtaining the next significant bit of the n and i binary numbers.

Preferably, the step of obtaining binary numbers corresponding to the same bits of the obtained n and i respectively comprises the steps of: and the least significant bit of the obtained n and i binary numbers is evaluated and the next significant bit of the or the n and i binary numbers is evaluated.

Optionally, the step of performing an exclusive or operation includes the steps of: exclusive-or the least significant bit of the acquired n and i binary numbers and the next significant bit of the or the n and i binary numbers.

By using the invention, when the amount of the stored data is large, the consumption of register resources can be greatly saved. With the present invention, since the expansion and reduction of such a matrix are calculated using the same circuit, it is not necessary to update the circuit at any time.

Drawings

FIG. 1 depicts a schematic block diagram of a prior art apparatus for generating a secondary synchronization channel code;

fig. 2 depicts a schematic circuit diagram of b-sequencer 1 z-sequencer 2 and control unit 3 of the apparatus for generating a slave synchronization channel code of fig. 1;

FIG. 3 is a diagram of a prior art storage device for obtaining a matrix H8 by using a table lookup method;

FIG. 4 is a schematic diagram of the circuit of the present invention for generating H8 matrix;

fig. 5 is a schematic diagram of the circuit for generating H9 matrix according to the present invention.

Detailed Description

The present invention will be described in further detail with reference to the accompanying drawings and specific embodiments.

Table 1 shows a schematic structure of an H8 array used in the present invention, in which an nth order Hadamard sequence is denoted as a row of matrix H8, numbered from the top, n is 0, 1, 2.

TABLE 1

Wherein the Hadamard sequences are generated by the rows of the matrix H8:

H₀＝(1)

from this equation, the values of hn (i) in the entire matrix sequence can be calculated, and table 2 shows the values for the points of the H8 array. In other words, when the 2-ary number n [7:0] represents the number of rows and the 2-ary number i [7:0] represents the number of columns, the data hn (i) corresponding to the n rows and i columns of the matrix is ^ (n & i). Where & represents a logical AND and ^ represents a logical XOR. For Hk (k ═ 0) matrix, the matrix with n as rows and i as columns can be obtained by hn (i) ═ n & i.

TABLE 2

Where n (k) represents the k-th digit from the lower to the upper digits when n is represented by binary, such as: 255(7) · 1,. 255(0) · 1; 4(4), (6), 4(4), (2), 4(1), 4(0), and 4(3), 1; 3(1) ═ 3(0) ═ 1, and 3(2 to 7) are all 0.

From this result, the present invention has designed the circuit shown in fig. 4, with which the H8 matrix is generated. The circuit is also suitable for generating a matrix of Hk expansion, wherein data can be obtained according to the number of rows and columns, and the corresponding circuit only needs to reduce or increase the 2-input AND gate and the 2-input XOR gate according to the size of the matrix.

Referring to fig. 4, a schematic diagram of the H8 matrix generating circuit of the present invention is depicted. Wherein, according to the logical relationship, the following formula can be obtained:

hn(i)＝^(^(^(n(5)&i(5))(n(4)&i(4)))(^(n(7)&i(7))(n(6)&i(6))))(^(^(n(3)&i(3))(n(2)&i(2)))(^(n(1)&i(1))(n(0)&i(0)))))。

wherein:&representing a logical and, a represents a logical xor. For example: h is₂₅₅(255)＝0，h₂₅₄(255)＝1。

Fig. 4 depicts a specific circuit of the present invention for generating the H8 matrix according to the above formula. The circuit comprises 8 two-input AND gates, two inputs of each AND gate respectively input binary numbers of the same bit of n and I, and the matrix is 256 multiplied by 256, so 8 binary numbers are required for representing the binary numbers, and 8 two-input AND gates are required. In addition, for the outputs of 8 two-input and gates, an exclusive or is required according to the above formula, therefore, the present embodiment further includes 7 two-input exclusive or gates, wherein the inputs of 4 two-input exclusive or gates are respectively connected with the outputs of 8 two-input and gates, the outputs of the 4 two-input exclusive or gates are connected to 2 two-input exclusive or gates, the outputs of the 2 two-input exclusive or gates are connected to 1 two-input exclusive or gate, and the last 1 two-input exclusive or gate outputs an element of the H8 matrix, i.e., a slave synchronization code. In practice, the invention can also be implemented by an eight-input exclusive or gate. In addition, the invention can be realized by an AND logic unit and an XOR logic unit by utilizing a storage unit and a control unit, wherein the control unit stores the result of the first AND in the storage unit, then calculates the second AND result, then calculates the XOR of the two AND results, and so on, and all the results can be obtained. Alternatively, all and results may be stored first, and then exclusive-or may be performed.

Fig. 5 shows a schematic diagram of the H9 matrix generating circuit of the present invention, the principle of which is the same as above. The circuit includes all the circuits in fig. 4, and additionally an and gate and an xor gate are added. The 8 and gates and 7 xor gates are the same as the working mode of fig. 4, that is: the matrix is 256 × 256, and 8 binary bit representations are required, so that 8 two-input and gates are required. In addition, for the outputs of 8 two-input and gates, an exclusive or is required according to the above formula, and therefore, the embodiment further includes 7 two-input exclusive or gates, wherein the inputs of 4 two-input exclusive or gates are respectively connected with the outputs of 8 two-input and gates, the outputs of the 4 two-input exclusive or gates are connected to 2 two-input exclusive or gates, the outputs of the 2 two-input exclusive or gates are connected to 1 two-input exclusive or gate, and the 1 two-input exclusive or gate outputs elements of the H8 matrix. To obtain the elements of the H9 matrix, the output of the xor gate that outputs the elements of the H8 matrix needs to be xored with the output of the added and gate. In the added and gates, the input is the binary number of the added n and I bits (here shown is the ninth bit, which can actually be any one bit, in fact, as long as the input of the 9 and gates is the binary number of the same bit of 9 n and I, respectively, the order of which does not affect the result).

Finally, the added exclusive-or gate outputs the elements of the H9 matrix, i.e., the 9 th order slave synchronization code.

In fact, the 8 exclusive or gates of the present invention can also be implemented by one nine-input exclusive or gate. In addition, the present invention can be implemented by an and logic unit and an exclusive or logic unit using a storage unit and a control unit.

It can be seen that the circuit for obtaining any order slave sync code is a simple copy of the circuit for obtaining H10, e.g., an and logic unit and an xor logic unit need to be added to the circuit for generating H9. Therefore, the circuit is simple. And because its circuit logic is simply replicated, the invention may be implemented in a programmable device having a processing unit and a memory unit.

In practical application, a method for generating Secondary Synchronization Code (SSC) in common channel of baseband chip by obtaining 2^mEach element in the order Hadamard sequence matrix generates a secondary synchronization code, where m is an integer no less than 1. When the value hn (i) of the i-th row of the matrix needs to be obtained to generate the slave synchronous code, the processing device firstly obtains binary numbers corresponding to bits from 0 to m-1 of the n and the i in step 1; then, in step 2, respectively corresponding to the acquired n and iThe same bits of the binary number to obtain 0 to m-1 states, respectively; in step 3, performing exclusive OR operation on all the states from 0 to m-1 respectively obtained by the summation in the step 2; in step 4, outputting said hn (i) to generate said slave synchronization code, wherein n and i are less than 2^mIs an integer of (1). Wherein, step 1 also includes step 11: acquiring the lowest bit of the n and i binary numbers and acquiring the next bit of the n and i binary numbers; and obtain the higher order bits. Step 2 further comprises step 21: and the least significant bit of the obtained n and i binary numbers is evaluated, and the next significant bit of the or-taken n and i binary numbers and the higher significant bit are evaluated. Step 3 further comprises step 31: exclusive-or the least significant bit of the acquired n and i binary numbers and the next significant bit of the or the n and i binary numbers, and the higher significant bit.

In this way, 2 can be easily generated^mElements in the order Hadamard sequence matrix, where m is an integer no less than 0, without requiring complicated circuits and operations, can be obtained, so that any order slave synchronization code can be obtained.

Although the present invention is depicted by way of example as specific circuits depicted in H8 and H9, those skilled in the art will appreciate that there are numerous variations and permutations of the present invention as the and logic cells and the xor logic cells may be implemented by programmable logic units, and that a general purpose computer, having programmed the disclosed methods into its executable programs, may also implement the apparatus of the present invention for generating slave synchronization codes by executing the programs that implement the methods of the present invention, and it is intended that the appended claims cover such variations and permutations.

Claims

1. a kind of baseband chip common channel produces the device from synchronous code, and described device produces each element in 2 ^m orders Hadamard sequence matrix, and wherein, m is the integer not less than 0, it is characterized in that: described device comprises:

At least one AND logical operation unit and one exclusive OR operation unit;

An obtaining device, used to obtain the binary number corresponding to each bit of the binary number corresponding to any number;

Wherein, in order to obtain the value hn(i) of the nth row i column of the matrix, the obtaining means respectively obtains the binary numbers corresponding to bits 0 to m-1 of the n and i, and the obtained n The same bit of the binary number corresponding to i is separately summed by the AND logical operation unit, and the 0 to m-1 states of the respective summation are passed through the exclusive OR operation unit to generate the slave synchronization code to obtain the Said hn(i), wherein said n and i are integers greater than or equal to 0 and less than 2 ^m .

2. produce in the common channel of baseband chip as claimed in claim 1 from the device of synchronization code, wherein, when m=1, described n and i are the integer less than 2; It is characterized in that: described device comprises two Two-input and logical operation unit and one XOR operation unit, wherein the input of the first two-input and logical operation unit is the first bit of the row and column respectively, and the input of the second two-input and logical operation unit is respectively The second bit of the row and column, the first and second two inputs and the output of the logical operation unit are respectively coupled to the input of the exclusive OR operation unit, and the output of the exclusive OR operation unit outputs The corresponding element of the slave synchronization code.

3. in the common channel of baseband chip as claimed in claim 2, produce the device from synchronous code, it is characterized in that, when m increases 1, described device comprises a described AND logical operation unit that increases, to carry out described row And the addition of 1-bit logical operation of the column.

4. in the common channel of baseband chip as claimed in claim 3, produce the device from synchronous code, it is characterized in that, when m increases 1 again, described device comprises the described two input and logical operation unit of an increase, to carry out The rows and columns are added with a 1-bit AND logic operation.

5. as claimed in claim 3 or 4 in the common channel of baseband chip, produce the device from synchronous code, it is characterized in that, also comprise an increased XOR operation unit, to complete described two input and logics of described one increase XOR operation of the output of the arithmetic unit.

6. A kind of device that produces from synchronous code in the common channel of baseband chip, wherein, m is the integer not less than 0, it is characterized in that: described device comprises:

A processor unit for AND and XOR operations;

A storage device for storing the binary number corresponding to each bit of the binary number corresponding to any number;

Wherein, in order to generate the slave synchronization code, the value hn(i) of the nth row i column of the matrix is obtained, and the one processor unit reads 0 to m of the n and i stored by the storage device The binary number corresponding to -1 bit, the same bits of the read n and i corresponding to the binary number are separately summed by the processor unit, and the 0 to m-1 states of the summation are respectively summed through the described The processor unit generates the slave synchronization code after an XOR operation, and obtains the hn(i), wherein the n and i are integers less than 2 ^m .

7. a kind of method that produces from synchronous code in the common channel of baseband chip, described method produces from synchronous code by obtaining each element in 2 ^m order Hadamard sequence matrix, and wherein, m is the integer not less than 1, it is characterized in that: The methods include:

When the value hn(i) of the nth row i column of the matrix needs to be obtained to generate the slave synchronization code,

Obtain the binary number corresponding to bits 0 to m-1 of the n and i,

Respectively find the same bits of the binary numbers corresponding to the obtained n and i to obtain 0 to m-1 states respectively;

Exclusive OR operation is performed on all the 0 to m-1 states that are summed respectively ;

Outputting the hn(i) to generate the slave synchronization code, wherein the n and i are integers less than 2 ^m .

8. in the common channel of baseband chip as claimed in claim 7, produce the method from synchronous code, it is characterized in that, the step of described binary number corresponding to 0 to m-1 bit of said acquisition of described n and i comprises the step: acquisition The lowest bit of the n and i binary numbers is summed to obtain the next bit of the n and i binary numbers.

9. produce in the common channel of baseband chip as claimed in claim 7 from the method for synchronous code from synchronous code, it is characterized in that, described respectively seek the step of identical bit with described n and i corresponding binary numbers of described acquisition The method comprises the step of summing the lowest bit of the acquired n and i binary numbers and summing the next bit of the or obtained n and i binary numbers.

10. in the common channel of baseband chip as claimed in claim 9, produce the method from synchronous code, it is characterized in that, the described step of carrying out XOR operation comprises the step: the described n of XOR described acquisition and i binary number The least significant bit is summed and the next bit of the n and i binary numbers taken or taken.