CN1510860A - A Frequency Lock Detection Circuit of Phase Locked Loop - Google Patents

Abstract

The invention provides a frequency lock detection circuit of a phase-locked loop, comprising two two-frequency divider groups composed of N two-frequency dividers, a comparison pulse generator and a rising edge trigger; the first two-frequency divider group is used It is used to generate the frequency division signal of the input signal, wherein the output frequency division signal of each two frequency divider is input to the comparison pulse generator; the comparison pulse generator is used to perform the N frequency division signals output by the first two frequency divider group Logic operation to obtain a comparison pulse waveform with a certain pulse width, which is output to the input terminal of the rising edge trigger; the input signal of the second two frequency divider groups is output to the first frequency divider after frequency division by N frequency dividers. The reset terminal of each two-frequency divider in the frequency divider group and the clock terminal of the rising edge trigger; the output signal of the rising edge trigger is a frequency lock detection signal. The invention has simple structure, and adopts two frequency dividers as the basic unit, has high reliability, is easy to implement, and is beneficial to reduce the area of the circuit layout.

Description

A Frequency Lock Detection Circuit of Phase Locked Loop

technical field

The invention relates to a phase-locked loop circuit in a communication system, in particular to a frequency-locked detection technology therein.

Background technique

A phase-locked loop circuit is a circuit widely used in communication systems, such as in microprocessors, digital video circuits, mobile communications, optical communications and other fields. Its main purpose is to realize that the output clock frequency is consistent with the input reference frequency or multiples of the input reference frequency (such as 2 times, 4 times, 16 times, etc.) within a pre-set small error range, that is, frequency locking. The basic structure of the phase-locked loop is shown in FIG. 1 , including a phase comparator (phase detector) 10 , a low-pass filter 20 , a voltage-controlled oscillator 30 and a frequency division circuit 40 . The phase detector 10 compares the phases of the reference clock input A and the frequency-divided signal B of the output clock. If there is a phase difference between the signals A and B, a voltage signal is generated, and the high-frequency component is removed through the low-pass filter 20, and then input to the voltage signal. controlled oscillator 30 to generate an output clock signal.

Because whether the clock frequency output by the phase-locked loop is locked has a direct impact on the working conditions of the next-level circuit of the communication system, so in the application of the phase-locked loop, it is very important to judge whether the output clock frequency of the phase-locked loop is locked at a certain fixed frequency of.

Frequency lock detection circuits commonly used in phase-locked loops include the following:

The first is to use the signals UP and DOWN output by the phase detector in the internal circuit of the phase-locked loop to detect whether the output frequency is locked;

The second is to use the output clock of the phase-locked loop to compare with the reference clock to detect whether the output frequency is locked.

For the first type of frequency lock detection circuit, the locking condition of the output clock of the phase locked loop is judged by monitoring the UP and DOWN signals output by the phase detector in the phase locked loop circuit. As shown in Figure 2, the circuit includes two voltage comparators and a judgment circuit. The UP and DOWN signals output by the phase detector are compared with the reference voltage through the voltage comparator to obtain two comparison voltages, which are input to the In the judging circuit, a detection signal is obtained. If there is no voltage pulse exceeding the reference voltage in the voltage comparator in the UP and DOWN signals output by the phase detector, the detection signal is high, indicating that the output frequency of the phase-locked loop and the reference clock frequency have reached the same, and there is no phase difference. This judges that the frequency of the phase-locked loop is locked; if the UP and DOWN signals continue to generate voltage pulses exceeding the reference voltage in the voltage comparator, the detection signal is low, causing the loop filter to charge and discharge, changing the output frequency of the voltage-controlled oscillator , it means that the PLL frequency is not locked. The disadvantage of this circuit is that it cannot strictly judge the fluctuation range of the UP and DOWN signal amplitudes output by the phase detector, which is prone to misjudgment. When the comparison voltage of the detection circuit is too low, as long as there is a small jitter in the output clock of the phase-locked loop, it will cause a misjudgment by the judgment circuit; when the comparison voltage of the detection circuit is too high, the unlocked output clock of the phase-locked loop The UP and DOWN signal fluctuations generated by the phase detector and the comparison signal are smaller than the comparison voltage, so that the frequency lock detection circuit cannot detect the loss of lock, and also causes misjudgment. Therefore, the reliability of this detection circuit is low.

The second detection circuit detects whether the output clock frequency is locked by comparing the closeness of the clock change edges between the output clock frequency of the phase-locked loop and the reference clock. When the changing edges of the two clocks are very close in several consecutive clock cycles, the detection circuit thinks that the clock frequency output by the phase-locked loop has been locked, otherwise it is not locked. But the disadvantage of this circuit is that it is very difficult to accurately judge the small interval between two edges by using an analog circuit; in addition, if there is a static error in the phase-locked loop, even if the output frequency of the phase-locked loop has been locked, the detection circuit No lock is still considered and a lock signal cannot be provided.

The U.S. patent PHASE LOCK DETECTION IN A PHASELOCK LOOP with the patent number US5278520 provides a circuit for frequency lock detection, as shown in Figure 3a, the N-frequency division of the reference clock REFCLK and the output clock is input to the NAND gate 110 and the XOR gate 118, the output of NAND gate 110 is passed by After the transmission gate 112 controlled by the TIMESOT signal passes through the transmission network formed by the NOT gates 114, 116 and the transmission gate 120, the output signal and the signal REFCLK and OSCOUT/N are input to the NOR gate 118, and the signal output by the NOR gate 118 First pass by The transmission gate 124 controlled by TIMESLOT after phase inversion passes through the transmission network composed of NOT gates 128, 130, 134 and transmission gate 136, and finally passes through the transmission gate 140 and NOT gate 142 controlled by TIMESLOT to obtain the required detection signal. When the first logic change occurs in the control signal TIMESLOT, the reference clock REECLK and the frequency division clock OSCOUT/N to be tested are at the first logic value; when the control signal When the second logic change of TIMESLOT occurs, the reference clock REFCLK and the clock OSCOUT/N to be tested are at another logic value. If the above two conditions are met, a flag signal DETECT that the signal to be tested is locked is generated. The waveform diagram of each signal See Figure 3b. In the case of locking, the reference clock REFCLK and the clock OSCOUT/N to be tested are at high level at the same time on the falling edge of the control signal TIMESLOT, then the output of the NAND gate 110 is at a low level, and through the transfer gate 112, the NOT gates 114 and 116 transmission, output to the first input terminal of the NAND gate 118, and still maintain a low level; when the control signal When the rising edge of TIMESLOT arrives, if the reference clock REFCLK and the clock OSCOUT/N to be tested are at low level at the same time, the NAND gate 118 outputs a high level, and passes through the transmission gate 124, the NOT gates 128, 130, 134, and the transmission gate 140 The transmission of the NAND gate 142 makes the lock flag signal DETECT a high level, indicating locking; in the case of non-locking, when the control signal When the rising edge of TIMESLOT arrives, if the reference clock REFCLK and the clock OSCOUT/N to be tested are not low at the same time, the output of the NAND gate 118 is low level, passing through the transmission gate 124, the NOT gates 128, 130, 134, and the transmission gate 140 The transmission of the NAND gate 142 makes the lock flag signal DETECT low, indicating that the clock under test is not locked. The circuit also shows that the lock flag signal DETECT must jump to an effective state some time before the phase-locked loop phase-locked effective signal, otherwise an error occurs. In addition, this circuit uses a sampling clock instead of a control signal. In order to obtain a proper timing of a reference clock, some external circuits are required, thereby greatly increasing the die area of the chip.

With the application of phase-locked loops more and more widely, the requirements for the performance and reliability of phase-locked loops are also getting higher and higher. Therefore, there is an urgent need for a frequency-locked detection circuit with strong reliability, simple structure and practicality.

Contents of the invention

The technical problem to be solved by the present invention is to propose a new frequency lock detection circuit applied to a phase-locked loop to solve the problems of low reliability and large circuit layout area of the existing frequency lock detection circuit.

The frequency lock detection circuit of the present invention comprises two two-frequency divider groups composed of N two-frequency dividers, a comparison pulse generator and a rising edge trigger;

The input signal of the first two-frequency divider group is the output feedback clock of the phase-locked loop, which is used to generate the frequency-divided signal of the input signal, wherein the output frequency-divided signal of each two-frequency divider is input to the comparison pulse generator;

The comparison pulse generator is used to perform logic operations on the N frequency division signals output by the first two frequency divider group to obtain a comparison pulse waveform with a certain pulse width, which is output to the rising edge trigger input terminal;

The input signal of the second two-frequency divider group is a reference clock, and the signals divided by N two-frequency dividers are respectively output to the reset terminals of each two-frequency divider of the first frequency divider group and the The clock terminal of the rising edge trigger;

The output signal of the rising edge trigger is a frequency lock detection signal.

The frequency locking detection circuit of the present invention has a simple structure, and adopts a two-frequency divider as a basic unit, has high reliability, is easy to realize, and is beneficial to reducing the circuit layout area.

Description of drawings

Figure 1 is a basic structural diagram of a general phase-locked loop;

FIG. 2 is a schematic diagram of an existing frequency locking detection circuit;

Figure 3a is a schematic diagram of a frequency lock detection circuit;

Fig. 3b is an input and output waveform diagram of the circuit shown in Fig. 3a;

Fig. 4 is the schematic diagram of the frequency locking detection circuit of the present invention;

FIG. 5 is a schematic diagram of two frequency dividers 101 in FIG. 4;

FIG. 6 is an input and output waveform diagram of the two frequency divider 101 shown in FIG. 5;

Fig. 7 is the application diagram of the frequency locking detection circuit of the present invention in the phase-locked loop;

Fig. 8 is an input and output waveform diagram of the frequency lock detection circuit of the present invention.

Detailed ways

The specific implementation of the present invention will be further described in detail below in conjunction with the accompanying drawings.

FIG. 1-FIG. 3 are introductions about the prior art, which have been described above and will not be repeated here.

In FIG. 4 , the frequency lock detection circuit includes a first two-frequency divider group 10 a , a second two-frequency divider group 10 b , a comparison pulse generator 11 and a rising edge trigger 12 .

Both the first two-frequency divider group 10 a and the second two-frequency divider group 10 b are composed of N two-frequency dividers 101 . FIG. 5 is a schematic diagram of the two-frequency divider 101, wherein IN is an input terminal, OUT is an output terminal, and RESET is a reset terminal. When RESET is high, the two frequency divider 101 realizes the normal frequency division function, that is, the rising edge triggers counting, and the signal frequency of the output terminal OUT is half of the frequency of the input terminal IN signal; when RESET is low, the output terminal OUT signal stay low. The waveform diagram of the input terminal IN, the output terminal OUT and the reset signal of the two frequency divider 101 is shown in FIG. 6 .

The input signal of the first two-frequency divider group 10a is the phase-locked loop output feedback clock signal FBCLK, and the N two-frequency dividers 101 in the first two-frequency divider group 10a are connected in sequence, that is, the output of the previous two-frequency divider The signal is the input signal of the next two-frequency divider; the output signal of each two-frequency divider 101 will also be output to the comparison pulse generator 11; the reset signal of the two-frequency divider 101 is from the second two-frequency divider group 10b output signal. The function of the first two-frequency divider group 10a is to generate the frequency-divided signal of the input signal FBCLK divided by two, divided by four, ..., ^2N , and provided to the comparison pulse generator 11 for logic operation to generate a comparison pulses while counting as a binary counter.

The function of the comparison pulse generator 11 is to perform logic operations on the N frequency-divided signals output by the first two-frequency divider group 10a according to the specified frequency locking detection accuracy, to obtain a comparison pulse waveform with a certain pulse width that meets the detection accuracy E, as the input signal of the rising edge trigger 12. For example, the detection accuracy is 1000ppm, then the width of the comparison pulse is 2 clock lengths, and the number of two frequency dividers in the frequency divider group is 10, which means counting 2 ¹⁰ clock pulses, and the error is between -1 and +1 The interval is one-thousandth of the error.

The input signal of the second frequency divider group 10b is the reference clock REFCLK, and the reset signal is the reset signal RESET of the system. The N two frequency dividers 101 are also connected in sequence, and the output of the last two frequency divider is used as the whole second frequency divider. The output signal D of the two-frequency divider group 10b is used as the reset signal of each two-frequency divider in the first two-frequency divider group 10a and the clock signal of the rising edge trigger 12 .

The rising edge trigger 12 outputs the value of the input terminal D to the Q output terminal when the clock terminal CLK is a rising edge moment, and its output signal is the frequency lock detection signal LOCK INDICATOR.

The basic principle of the frequency lock detection circuit of the present invention is: utilize the output feedback clock of continuous phase-locked loop to define the comparison pulse of certain width, and count the reference clock frequency, when the output feedback clock frequency of the phase-locked loop and the reference clock frequency differ When within the specified error range, the reference clock frequency counting pulse change edge will fall within the comparison pulse generated by the output feedback clock of the phase-locked loop, so as to obtain the frequency lock detection signal.

The frequency detection circuit of the present invention first determines the number of two frequency dividers 101 in the two frequency divider groups 10a, 10b according to the specified detection accuracy, and generates a comparison pulse waveform E through the comparison pulse generator 11. Assume that the frequency lock detection accuracy is 1‰, that is, when the difference between the reference clock frequency and the frequency of the detected signal is within 1‰, the detected signal is locked. At this time, the count value of the two frequency divider groups 10a and 10b is about 1000, and the number of the two frequency dividers should be 11, that is, the high pulse width is ²¹⁰ =1024 cycles, and the low pulse width is also 1024 cycles; compare the pulse width It is 2 periods (-1 to +1).

The application of the frequency lock detector of the present invention in the phase-locked loop is shown in Figure 7. The reference clock and the feedback clock of the phase-locked loop are input into the frequency lock detector, and the corresponding frequency detection signal is output through the frequency lock detection and sent to the lower system. This allows the lower-level system to judge whether the phase-locked loop is working stably and normally, so as to perform corresponding operations.

In the waveform diagram shown in FIG. 8, at the beginning, the frequency of the feedback clock FBCLK output by the phase-locked loop is lower than the frequency of the reference clock REFCLK, and the signal D is the count signal output by the reference signal REFCLK through the second two-frequency divider group 10b. The signal E is a comparison pulse signal generated by the output feedback clock FBCLK passing through the first two frequency divider group 10 a and the comparison pulse generator 11 . Signal D changes from low level to high level earlier than signal E. At this time, for rising edge trigger 12, when signal D changes from low level to high level, rising edge trigger 12 will signal E here. When the level value (low level) is output, that is, the frequency lock detection signal LOCK INDICATOR is low level, indicating that it is not locked, indicating that the frequency difference between the frequency of the phase-locked loop feedback clock FBCLK and the frequency of the reference clock REFCLK is greater than 1‰.

In the next counting cycle, when the average frequency of the output feedback clock FBCLK of the phase-locked loop and the reference clock REFCLK are basically consistent, the rising edge of the signal D falls within the high level range of the signal E, and the output LOCK of the rising edge trigger 12 INDICATOR is high level, indicating that the frequency difference between the output clock of the phase-locked loop and the reference clock does not exceed 1‰, and at this time, the output clock frequency is locked to the reference clock frequency.

Through the above detailed introduction, it can be clearly seen that the present invention is reliable in detection, simple in structure, easy to implement, and effectively overcomes the problems in the prior art.

Claims (3)

1, a kind of frequency lock testing circuit of phase-locked loop is characterized in that, comprises two two frequency divider groups of being made up of N two frequency dividers (101) (10a, 10b), relatively pulse generator (11) and rising edge trigger (12);

The input signal of described first liang of frequency divider group (10a) is the output feedback clock of phase-locked loop, is used to produce the fractional frequency signal of input signal, and wherein the output frequency division signal of each two frequency divider (101) all inputs to described relatively pulse generator (11);

Described relatively pulse generator (11) is used for N fractional frequency signal of described first liang of frequency divider group (10a) output carried out logical operation, obtains a comparison impulse waveform with certain pulsewidth, outputs to the input of described rising edge trigger (12);

The input signal of described second liang of frequency divider group (10b) is a reference clock, reset signal is the reset signal of system, outputs to the clock end of the reset terminal and the described rising edge trigger (12) of described first each two frequency divider (101) of frequency divider group (10a) respectively through the signal behind N two frequency dividers (101) frequency division;

The output signal of described rising edge trigger (12) is the frequency lock detection signal.

2, frequency lock testing circuit according to claim 1, it is characterized in that, described first liang of frequency divider group (10a) comprises N two frequency dividers (101) that link to each other successively, and the output signal that promptly goes up one two frequency divider is the input signal of next two frequency dividers; The output signal of each two frequency divider (101) is all exported to comparison pulse generator (11); The reset signal of two frequency dividers (101) is the output signal from second liang of frequency divider group (10b).

3, frequency lock testing circuit according to claim 1 and 2, it is characterized in that, described second liang of frequency divider group (10b) comprises N two frequency dividers (101) that link to each other successively, and the output signal that promptly goes up one two frequency divider is the input signal of next two frequency dividers; The output of last two frequency divider is output signals of whole second liang of frequency divider group (10b), as the reset signal of each two frequency divider (101) in first liang of frequency divider group (10a) and the clock signal of rising edge trigger (12).

Images