CN1505129A

CN1505129A - Method and device for manufacturing extended capacitor in memory

Info

Publication number: CN1505129A
Application number: CNA021526346A
Authority: CN
Inventors: ��ز��; 王重博; 夏启明
Original assignee: Winbond Electronics Corp
Current assignee: Winbond Electronics Corp
Priority date: 2002-11-28
Filing date: 2002-11-28
Publication date: 2004-06-16
Anticipated expiration: 2022-11-28
Also published as: CN1245748C

Abstract

The present invention relates to a method and device for manufacturing an extended capacitor in a memory. The method mainly comprises first forming mutually staggered contact nodes on a substrate of the memory, and then depositing an electroplated substrate above each contact node. Conductive materials are electroplated on both sides of the electroplated substrate to form capacitor plates. The electroplated substrate is then etched away to leave only the capacitor plates, thus completing the capacitor formation steps. The capacitor obtained by the above steps has a larger effective plate area than conventional technology, so the capacitance can be effectively increased in a high-density memory process.

Description

Extension electric capacity method for making and device in the memory

(1) technical field

The present invention refers to be formed with in a kind of storage element in small size (Memory Cell) the electric capacity method for making and the device of high density and high appearance value especially about extension electric capacity method for making and device in a kind of memory.

(2) background technology

Along with its process technique of memory is constantly upgraded toward accurate processing procedure, the rapid rising of density of storage element (Memory cell), the area that it occupied is also and then reduction naturally, will cause the capacitor's capacity in the storage element also to descend so thereupon.So how on limited area, still can keep certain suitable capacitor's capacity, when becoming present manufacturing memory the problem that must improve, wherein the difficulty that must overcome is the upper and lower layer limit and the therebetween high-dielectric coefficient insulating barrier of electric capacity, and the occupied space utmost point of three is difficult to grasp.

For guaranteeing under the high-density storage processing procedure, still to possess certain appearance value, so by stack electric capacity (Stacked Capacitor, STC) structure increases the appearance value, with cylinder (Cylinder) stack capacitor and spill (Concave) stack capacitor, because of electric capacity is shaped as an ellipticity, in the memory cell of minimum area, the deposition formation for high-dielectric coefficient insulating barrier in the electric capacity and upper electrode plate has the problem that deposition space is difficult to control.Especially in the formation of the high-dielectric coefficient layer of column type (Cylinder) stack capacitor and spill (Concave) stack capacitor inside, be difficult to control more as BST, SrTi03, PZT etc.

On the other hand, with convex type (Convex) stack capacitor, though the problem that above-mentioned relevant deposition and space are controlled can be greatly improved, greatly reduce yet its polar board surface of convex type stack capacitor is long-pending, its appearance value also only is 0.6 times of column type stack capacitor.

(3) summary of the invention

For effectively overcoming above-mentioned located by prior art disappearance, main purpose of the present invention provides extension electric capacity method for making and device in a kind of memory, change the kenel that staggers mutually into the contact zone (Contactnode) that the left and right sides on the storage element (Memory cell) is adjacent, change in view of the above and upwards be formed with the flaky electric capacity pole plate again, form by this and may extend to adjacent contact pole plate partly, reaching increases the pole plate effective area, improves capacitor's capacity.

Another object of the present invention is to provide extension electric capacity method for making and device in a kind of memory, it is fabrication steps formation capacitor plate with general pattern such as light shield development, etching, deposition, make the formation of each capacitor plate be easier to control, and can promote the processing procedure acceptance rate of electric capacity.

For realizing aforementioned purpose, extension electric capacity method for making in the memory of the present invention includes following steps: make each adjacent contact zone of the left and right sides (Contact node) be staggered each other; The deposition plating substrate is in each top, alternating expression contact zone deposition plating substrate; Layer deposited isolating and the step that plating substrate and separator are formed, and aforementioned plating substrate is divided into the kenel that is arranged in parallel more, and also be formed with the be arranged in parallel separator of plating substrate of multiple tracks on its surface, each plating substrate is divided into multistage; Electroplate the capacitance pole flaggy, in each plating substrate surface and the zone that is not coated with separator be electroplate with conductive material to constitute the capacitance pole flaggy; Remove separator and plating substrate, after forming the capacitance pole flaggy, aforementioned each separator and plating substrate etching are removed, and on each contact zone, be formed with capacitor plate.

Implement prepared capacitor constructions behind the above-mentioned processing procedure, because of its battery lead plate is the periphery that vertically is formed at each top, contact zone and extends to the adjacent contact district, and because contact zone, the aforementioned left and right sides is and staggers, so its pole plate effective area greatly increases, even in highdensity memory process, still can obtain the electric capacity of high appearance value, in addition, because of each capacitor plate is to form by plating mode, so its processing procedure is easier to control, thereby unit still can obtain higher processing procedure acceptance rate in the memory cell of zonule.

For clearer understanding purpose of the present invention, characteristics and advantage, preferred embodiment of the present invention is elaborated below in conjunction with accompanying drawing.

(4) description of drawings

Fig. 1 is the schematic diagram that is formed with the alternating expression contact zone at a memory substrate.

Fig. 2 is the schematic diagram that deposition is formed with plating substrate on each alternating expression contact zone.

Fig. 3 is the schematic side view that deposition is formed with plating substrate on each alternating expression contact zone.

Fig. 4 reaches an embodiment schematic diagram that forms capacitor plate on the plating substrate side in depositing separator on the plating substrate.

Fig. 5 reaches another embodiment schematic diagram that forms capacitor plate on the plating substrate side in depositing separator on the plating substrate.

Fig. 6 is the schematic side view of electroplating capacitor plate on the plating substrate two sides.

The schematic diagram of Fig. 5 after to be capacitance structure shown in Figure 4 with separator and plating substrate remove.

The schematic diagram of Fig. 8 after to be capacitance structure shown in Figure 5 with separator and plating substrate remove.

Fig. 9 is with the schematic diagram of A-A direction side-looking among Fig. 5.

Figure 10 is with the schematic diagram of B-B direction side-looking among Fig. 5.

Figure 11 is with the schematic diagram of C-C direction side-looking among Fig. 8.

Figure 12 is with the schematic diagram of D-D direction side-looking among Fig. 8.

Figure 13 is an another embodiment of the present invention, electroplates the capacitor plate material earlier in the plating substrate side.

Figure 14 is an embodiment schematic diagram that is formed with separator and capacitor plate in Figure 13.

Figure 15 is the another embodiment schematic diagram that is formed with separator and capacitor plate in Figure 13.

(5) embodiment

Please refer to shown in Figure 1, earlier according to commonly use the memory process step on a memory substrate 10, painstakingly arrange to be formed with make the left and right sides adjacent service area (Active area) 20, the kenel that staggers each other in character line zone (Wordline) 21, after forming zones such as above-mentioned service area 20 and character line 21, carry out implementation step of the present invention again:

At first between two adjacent character line 21 zones, be formed with a plurality of contact zones (Contactarea) 22, each contact zone 22 is the formation directions that are parallel to service area 20, shown on the drawing, two adjacent contact zones 22 of the left and right sides are not to be located along the same line and to be staggered, the generation type of each contact zone 22 is as described below again: be to be formed with a contact hole (Contact hole) in an insulating thin layer such as SiN thin layer earlier, again in this contact hole inside deposition conductivity material, as compound crystal silicon (Poly), platinum (Pt), ruthenium (Ru) etc., and carry out a cmp step (CMP) again it is polished to form contact zone 22.

Please refer to Fig. 2, shown in 3, deposition is formed with one deck plating substrate 30 on aforementioned contact zone 22, can select TiN for use, materials such as W/TiN are as the deposition material, the end face of this plating substrate 30 is formed with an oxide layer 31, and then with the etched technology of light shield, make it to change into and be spaced, as shown in Figure 2, this oxide layer 31 at top layer is used as electroplating to isolate, its schematic perspective view as shown in Figure 2, its cross-sectional schematic then as shown in Figure 3, the height of deposition of this plating substrate 30 is promptly represented the height of capacitor plate again, and plating substrate 30 covers contact zone 22 for the part.

Please refer to shown in Fig. 4,5, after finishing aforementioned plating substrate 30, (as photoresistance, PR), each separator 40 is to be with plating substrate 30 to intersect direction and covering thereon to be formed with multiple tracks separator 40 again, each road separator 40 can be as shown in Figure 4, be covered in the middle position of each contact zone 22, each contact zone 22 is divided into two, also can be as shown in Figure 5, be not to be covered in each 22 top, contact zone, but the contact zone adjacent with another two row, the contact zone that two rows are adjacent separate to come mutually.

The surface that appears in each section plating substrate 30 (does not promptly have the zone that separator 40 covers and non-oxidation layer 31 covers, be the wall of plating substrate 30) be formed with capacitor plate 50 of the present invention with plating mode, each capacitor plate 50 electrodepositable is with conductive material, as platinum (Pt), please also refer to shown in Figure 6, it is the cross-sectional schematic after electroplating, by being to be formed with capacitor plate 50 as can be known on the two sides of this plating substrate 30 among the figure, the height of each capacitor plate 50 is promptly determined by the height of aforementioned plating substrate 30.

Please refer to shown in Figure 7, it is the step of carrying out a removal separator 40 and plating substrate 30 with capacitance structure shown in Figure 4, removing method is to carry out with RIE and Wet-type etching, and after removing, two ends vertically are formed with independently capacitor plate 50 above each contact zone 22.Please refer to shown in Figure 9, it is part schematic diagram for analysing and observe with the A-A direction among Fig. 7, by finding out among Fig. 9 that two capacitor plates, 50 its bottoms are to contact with contact zone 22, in Figure 10, then be the schematic diagram of analysing and observe with the B-B direction in Fig. 7, promptly 22 both sides, contact zone form the capacitor plate 50 of symmetry.

The with reference to shown in Figure 8, is to be schematic diagram after above-mentioned capacitance structure shown in Figure 5 is removed separator 40 and plating substrate 30, and Figure 11 is the part schematic diagram after analysing and observe with the C-C direction in Fig. 8, and for becoming a double area capacitance pole plate 50, effect is identical with Figure 10; And in Figure 12, be to be the part schematic diagram after analysing and observe with the D-D direction among Fig. 8.

Above implementation step is to be fabrication steps one specific embodiment of the present invention, and the present invention can also realize by another processing procedure embodiment that it is described in detail as follows:

This embodiment is also shown in Figure 2 as described above, after deposition plating substrate 30, the capacitor plate 50 of deposition formation earlier on the end face of each plating substrate 30 and the two sides, the deposition material can be selected platinum (Pt) for use, again with the sedimentary deposit etch-back of a dry-etching mode with plating substrate 30 end faces, the sedimentary deposit that only keeps two sides, as shown in figure 13.

Again to be across the direction of plating substrate 30, be coated with several separator 40 again at plating substrate 30 and capacitor plate 50 surfaces that deposited, wherein the covering scope of each separator 40 is (as shown in Figure 14) on the middle position in alignment with each contact zone 22, also two adjacent contact zones can be separated (as shown in figure 15) with another two adjacent contacting.

Through a wet etch step unlapped capacitor plate 50 parts of 40 of separators are removed again, again plating substrate 30 and separator 40 etchings that the top covered are removed afterwards, and can be obtained the capacitor plate shown in Fig. 7 and 8 50 as described above.

Claims

1. an extended capacitance method in a memory, characterized in that, comprising:

Forming a plurality of contact regions is to first form a plurality of contact regions arranged in a staggered pattern on a memory substrate;

Depositing the electroplating substrate is depositing the electroplating substrate on each of the staggered contact areas, and the electroplating substrate only covers a part of the contact area;

Depositing and etching the oxide layer, first depositing an oxide layer comprehensively on the memory substrate formed with the electroplating base, and then removing part of the oxide layer by photomask etching technology, leaving only the oxide layer covering the top surface of the electroplating substrate;

Depositing an isolation layer, forming multiple isolation layers on the aforementioned electroplating substrate, separating each electroplating substrate into multiple sections;

Electroplating the capacitor plate layer, electroplating conductive material on the two sides of each electroplating substrate and not covered by the isolation layer to form the capacitor plate layer;

The isolation layer and the electroplating base material are removed, and after the capacitor plate layer is formed, the aforementioned isolation layers and the electroplating base material are etched away to form a large-area chip capacitor plate on each contact area.

2 . The manufacturing method of extended capacitor in memory according to claim 1 , wherein in the step of removing the isolation layer and the electroplating substrate, the isolation layer and the electroplating substrate are removed by RIE and wet etching. 3 .

3 . The manufacturing method of an extended capacitor in a memory according to claim 1 , wherein the capacitor plates above each contact area extend toward both sides in a symmetrical manner, and do not contact the contact areas on both sides. 4 .

4 . The manufacturing method of extended capacitor in memory according to claim 1 , wherein the capacitor plate above each contact area extends in a single direction and does not contact with the contact area on the other side.

5. A method for manufacturing extended capacitance in a memory, characterized in that it comprises:

Forming a plurality of contact regions is to first form a plurality of contact regions in a staggered pattern on a memory substrate;

The electroplating capacitor plate layer is electroplated with conductive metal on the surface of the electroplating substrate as the capacitor plate;

Depositing an isolation layer, depositing an isolation layer on the aforementioned capacitor plate layer, dividing the capacitor plate layer into multiple sections;

Etching the capacitor plate layer, etching away the capacitor plate layer not covered by the isolation layer;

The isolation layer and the electroplating base material are removed, and the above isolation layer and the electroplating base material are completely removed, and vertical large-area chip capacitor plates are formed on each contact area.

6. The manufacturing method of extended capacitance in memory as claimed in claim 5, wherein before the step of depositing the isolation layer, the capacitor plate layer deposited on the top surface of the electroplating substrate is removed by dry etching, and only The capacitive plate layers on both sides of the plated substrate are retained.

7 . The manufacturing method of an extended capacitor in a memory according to claim 6 , wherein the capacitor plates above each contact area extend toward both sides in a symmetrical manner, and do not contact the contact areas on both sides. 8 .

8 . The manufacturing method of extended capacitor in memory according to claim 6 , wherein the capacitor plate above each contact area extends in a single direction and does not contact with the contact area on the other side.

9. The manufacturing method of extended capacitor in memory according to claim 5 or 6, characterized in that, in the step of removing the isolation layer and the electroplating substrate, the isolation layer and the electroplating substrate are removed by wet etching.

10. An extended capacitor device in a memory, characterized in that it includes:

A memory substrate, on which there are a plurality of staggered contact areas;

A plurality of capacitive plates, each capacitive plate is vertically formed above each contact area, is in the form of a sheet and extends outward across each contact area.

11. The extended capacitor device in memory according to claim 10, wherein the paired capacitor plates above each contact area extend toward both sides in a symmetrical manner, and do not overlap with adjacent contact areas. touch.

12. The extended capacitor device in memory according to claim 10, wherein a single capacitor plate is formed above each contact region, and extends outward in a single direction without interfacing with adjacent contact regions. touch.

13. The extended capacitor device in memory according to claim 11 or 12, wherein each contact area is formed by depositing a conductive material.

14. The extended capacitor device in memory according to claim 11 or 12, wherein each capacitor plate is deposited by conductive material.