CN1501449A - Method for manufacturing polycrystalline silicon layer - Google Patents

Abstract

A method for manufacturing a polysilicon layer includes the following steps: (a) providing a substrate; (b) forming a buffer layer having a plurality of trenches on the substrate; (c) forming an amorphous silicon layer on the buffer layer; and (d) performing a laser annealing process so that the amorphous silicon layer is melted and then crystallized from above the trenches to form a polysilicon layer. The present invention can be applied to the manufacture of low-temperature polysilicon thin-film transistor liquid crystal displays, and the polysilicon layer formed has a larger crystal size and better uniformity.

Description

Manufacturing method of polysilicon layer

technical field

The present invention relates to a manufacturing method of a polysilicon layer, and in particular to a polysilicon layer which uses an unmelted amorphous silicon layer in a trench (trench) as a nucleation site and undergoes lateral crystallization (lateral crystallization) Production Method.

Background technique

Low Temperature PolySilicon Liquid Crystal Display (LTPS LCD) is different from the general traditional amorphous silicon thin film transistor liquid crystal display (a-Si TFT-LCD), its electron mobility can reach 200cm ² /V-sec Therefore, the area occupied by the thin film transistor can be made smaller to meet the requirement of high aperture ratio, thereby improving the brightness of the display and reducing the overall power consumption. In addition, due to the increase in electron mobility, part of the driving circuit can be manufactured on the glass substrate together with the thin film transistor process, which greatly improves the reliability of the liquid crystal display panel and greatly reduces the panel manufacturing cost. Therefore, the manufacturing cost of low-temperature polysilicon TFT-LCDs is much lower than that of amorphous silicon TFT-LCDs. In addition, the low-temperature polysilicon thin film transistor liquid crystal display has the characteristics of thin thickness, light weight, and good resolution, and is very suitable for mobile terminal products that require light weight and power saving.

In low-temperature polysilicon thin film transistor liquid crystal display (LTPS-LCD), the channel layer of the thin film transistor is usually formed by Excimer Laser Annealing (ELA), and the quality of this channel layer usually depends on the size of the polysilicon crystal (grain size) And its uniformity, and the size of the crystal and the uniformity of the crystal are directly related to the energy control of the excimer laser.

FIG. 1A to FIG. 1C are schematic diagrams of the fabrication process of a conventional polysilicon layer. First, please refer to FIG. 1A , a substrate 100 is provided, and the substrate 100 is usually a glass substrate. Next, a buffer layer 102 is formed on the substrate 100, and the buffer layer 102 is generally a laminated structure including a silicon nitride layer and a silicon oxide layer.

Referring to FIG. 1B and FIG. 1C , after the buffer layer 102 is formed, an amorphous silicon layer 104 is then formed on the buffer layer 102 . Then carry out an excimer laser thermal annealing process, control the energy of the excimer laser irradiation on the amorphous silicon layer 104, so that the amorphous silicon layer 104 is almost completely melted, and only a little crystal nuclei remain on the surface of the buffer layer 102 ( seed of crystallization). Afterwards, the molten liquid silicon crystallizes from the aforementioned crystallization nuclei to form a polysilicon layer 106 , and the polysilicon layer 106 has crystal boundaries 108 that are not evenly distributed.

In the above-mentioned excimer laser thermal annealing process, if the energy of the excimer laser exceeds the SLG (Super Lateral Growth) point, the distribution density of crystal nuclei will drop very low instantly, resulting in a small grain size and uneven uniformity of the polysilicon layer. good. Therefore, the energy of the excimer laser must be controlled very precisely in order to produce a polysilicon layer with satisfactory crystal size and uniformity, so the process margin of this process is very small.

FIG. 2 is a schematic diagram of conventional polysilicon layer fabrication through openings in the buffer layer. Referring to FIG. 2 , a substrate 200 is provided, and the substrate 200 is usually a glass substrate. Next, a buffer layer 202 is formed on the substrate 200, and the buffer layer 202 is generally a laminated structure including a silicon nitride layer and a silicon oxide layer. In order to improve the crystal size, uniformity and process margin in the formed polysilicon layer, it is known to make a plurality of openings 204 arranged in an array in the buffer layer 202, and these openings 204 will be play a rather important role. During excimer laser thermal annealing, the amorphous silicon layer (not shown) on the area outside the opening 204 will be completely melted into liquid silicon, and the amorphous silicon layer (not shown) at the bottom of the opening 204 It is not completely melted, so the liquid silicon can crystallize (grow laterally) into a polysilicon layer from the bottom of the opening 204 . From the above, it can be seen that the position where the crystallization starts is the position of the opening 204, so the number of crystallization nuclei and the distribution position thereof can be effectively controlled.

FIG. 3 is a schematic diagram of crystal boundaries of a conventional polysilicon layer. Referring to FIG. 3 , since the amorphous silicon layer at the bottom of the opening 204 is not completely melted, liquid silicon will grow outward from the bottom of the opening 204 . Since the molten liquid silicon grows laterally from the openings 204 , there will be grain boundaries 300 between adjacent openings 204 , and these grain boundaries 300 will be directly limited by the distance between the openings 204 . Since the openings 204 are arranged in an array, the grain growth in the x direction and the y direction is restricted by the adjacent openings 204. Therefore, although this method can effectively control the distribution of crystal nuclei, it is not effective for the crystal grains. Size is still limited.

Contents of the invention

Therefore, the object of the present invention is to provide a method for manufacturing a polysilicon layer, and the formed polysilicon layer has a larger crystal size and better uniformity.

Another object of the present invention is to provide a polysilicon layer manufacturing method, which can greatly improve the process window of the laser thermal annealing process.

Another object of the present invention is to provide a method for fabricating a polysilicon layer, and the formed polysilicon layer has fewer grain boundaries.

In order to achieve the above-mentioned purpose of the present invention, a kind of preparation method of polysilicon layer is proposed, comprising the following steps: (a) providing a substrate; (b) forming a buffer layer with a plurality of first trenches on the substrate; (c ) forming an amorphous silicon layer on the buffer layer; and (d) performing a laser annealing process so that the amorphous silicon layer is melted and crystallized from above the first trenches to form a polysilicon layer.

In the present invention, the method for forming the buffer layer with the first trench includes the following steps: (a) forming a silicon nitride layer on the substrate; (b) forming a plurality of second trenches in the silicon nitride layer; and (c) forming a conformal silicon oxide layer on the silicon nitride layer to naturally form a plurality of first trenches corresponding to the second trenches in the silicon oxide layer.

In the present invention, the method for forming the buffer layer with the first trench includes the following steps: (a) forming a silicon nitride layer on the substrate; (b) forming a silicon oxide layer on the silicon nitride layer; and ( c) forming a plurality of first trenches in the silicon oxide layer.

In the present invention, the above-mentioned first trench and/or the second trench are formed by, for example, lithography/etching, and the above-mentioned laser annealing process is, for example, an excimer laser annealing process.

Description of drawings

1A to 1C are schematic diagrams of the production process of a known polysilicon layer;

Fig. 2 is a known schematic diagram of making a polysilicon layer through an opening on a buffer layer;

3 is a schematic diagram of crystal boundaries of a known polysilicon layer;

FIG. 4 is a schematic diagram of making a polysilicon layer through a trench on a buffer layer according to a preferred embodiment of the present invention;

5 is a schematic diagram of crystal boundaries of a polysilicon layer according to a preferred embodiment of the present invention;

6A to 6D are schematic diagrams of the fabrication process of the polysilicon layer according to a preferred embodiment of the present invention; and

7A to 7D are schematic diagrams of the fabrication process of the polysilicon layer according to another preferred embodiment of the present invention.

100, 200, 400, 600, 700: Substrate

102, 202, 402, 602, 702: buffer layer

104, 606, 706: amorphous silicon layer

106, 608, 708: polysilicon layer

108, 300, 500, 610, 710: crystal boundaries

204: opening

404, 604, 704b: First Ditch

602a, 702a: silicon nitride layer

602b, 702b: silicon oxide layer

704a: Second Ditch

Detailed ways

FIG. 4 is a schematic diagram of forming a polysilicon layer through a trench on a buffer layer according to a preferred embodiment of the present invention. Referring to FIG. 4 , a substrate 400 is provided, and the substrate 400 is usually a glass substrate. Next, a buffer layer 402 is formed on the substrate 400 . The buffer layer 402 is, for example, a laminated structure including a silicon nitride layer and a silicon oxide layer (details will be described later). In order to improve the crystal size, uniformity and process margin in the formed polysilicon layer, in this embodiment, a plurality of parallel first trenches 404 are formed in the buffer layer 402, and these first trenches 404 are formed in the subsequent excimer In the laser thermal annealing process, it will play the role of providing crystallization nuclei. During excimer laser thermal annealing, the amorphous silicon layer (not shown) on the region outside the first trench 404 will be completely melted into liquid silicon, and the amorphous silicon layer (not shown) at the bottom of the first trench 404 ( (not shown) is not completely melted, so the liquid silicon can crystallize (grow laterally) into a polysilicon layer from the bottom of the first trench 404 . From the above, it can be known that the position where crystallization begins is the position of the first trench 404 , so the distribution position of crystallization nuclei can be effectively controlled.

FIG. 5 is a schematic diagram of crystal boundaries of a polysilicon layer according to a preferred embodiment of the present invention. Referring to FIG. 5 , since the amorphous silicon layer at the bottom of the first trench 404 is not completely melted, liquid silicon will grow outward from the bottom of the first trench 404 . Since the molten liquid silicon grows laterally from the first trenches 404, there will be crystal boundaries 500 between adjacent first trenches 404, and these grain boundaries 500 will be directly limited by the distance between the first trenches 404. distance between. Since the first trenches 404 are arranged parallel to each other, for example, along the y direction, the grain growth is limited only by the adjacent first trenches 404 in the x direction. In other words, providing a plurality of linear crystallization nuclei through the first trench 404 can simultaneously take care of the grain size and uniformity of the polysilicon layer.

The fabrication of the entire polysilicon layer will be described in detail below. 6A to 6D are schematic diagrams of the fabrication process of the polysilicon layer according to a preferred embodiment of the present invention. First, referring to FIG. 6A , a substrate 600 is provided, and the substrate 600 is usually a glass substrate. Next, a buffer layer 602 is formed on the substrate 600, such as a laminated structure including a silicon nitride layer 602a and a silicon oxide layer 602b. The aforementioned silicon nitride layer 602 a and silicon oxide layer 602 b are formed by, for example, plasma chemical vapor deposition (Plasma Enhanced Chemical Vapor Deposition, PECVD).

6B, a plurality of first trenches 604 parallel to each other are formed in the buffer layer 602. These first trenches 604 are formed by lithography/etching, for example. In the silicon oxide layer 602b.

Please refer to FIG. 6C and FIG. 6D at the same time. After the first trench 604 is formed, an amorphous silicon layer 606 is then formed on the buffer layer 602. The amorphous silicon layer 606 is, for example, deposited by Low Pressure Chemical Vapor Deposition (Low Pressure Chemical Vapor Deposition, LPCVD) way to form. After the amorphous silicon layer 606 is formed, a laser thermal annealing process is performed, such as an excimer laser thermal annealing process. In the laser thermal annealing process, the energy of excimer laser irradiation on the amorphous silicon layer 606 is controlled, so that the amorphous silicon layer 606 on the region other than the first trench 604 is almost completely melted, and the amorphous silicon layer at the bottom of the first trench 604 Layer 606 is not completely melted, so liquid silicon can crystallize into a polysilicon layer 608 from the bottom of first trench 604 . In addition, the polysilicon layer 608 formed by the laser thermal annealing process has grain boundaries 610 , and the grain boundaries 610 only appear between adjacent first trenches 604 .

7A to 7D are schematic diagrams of the fabrication process of the polysilicon layer according to another preferred embodiment of the present invention. First, referring to FIG. 7A , a substrate 700 is provided, and the substrate 700 is usually a glass substrate. Next, a silicon nitride layer 702 a is formed on the substrate 700 , and the silicon nitride layer 702 a is formed by plasma chemical vapor deposition (PECVD), for example. Then, a plurality of second trenches 704a parallel to each other are formed in the silicon nitride layer 702a, and these second trenches 704a are formed by, for example, lithography/etching.

Referring to FIG. 7B, after the formation of the second trench 704a, a conformal silicon oxide layer 702b is formed on the silicon nitride layer 702a. The silicon nitride layer 702a and the silicon oxide layer 702b form a buffer layer 702. Since the silicon oxide layer 702b covers the silicon nitride layer 702a, a plurality of first trenches 704b are naturally formed on the silicon oxide layer 602b at the positions of the second trenches 704a. In addition, the width of these first trenches 704b will be smaller than the width of the second trenches 704a due to the step coverage (step coverage), so this embodiment can produce the first trenches 704b with a width smaller than the critical dimension (Critical Dimension, CD) .

7C and 7D, after the first trench 704 is formed, an amorphous silicon layer 706 is formed on the buffer layer 702. The amorphous silicon layer 706 is formed by low pressure chemical vapor deposition (LPCVD). After the amorphous silicon layer 706 is formed, a laser thermal annealing process is performed, such as an excimer laser thermal annealing process. In the laser thermal annealing process, the energy of excimer laser irradiation on the amorphous silicon layer 706 is controlled, so that the amorphous silicon layer 706 on the region other than the first trench 704b is almost completely melted, and the amorphous silicon layer at the bottom of the first trench 704b The layer 706 is not completely melted, so liquid silicon can crystallize into a polysilicon layer 708 from the bottom of the first trench 704b. In addition, the polysilicon layer 708 formed by the laser thermal annealing process has grain boundaries 710, and the grain boundaries 710 only appear between adjacent first trenches 704b.

In summary, the manufacturing method of the polysilicon layer of the present invention has at least the following advantages:

1. Since the incompletely melted amorphous silicon layer in the trench provides a good seed of crystallization, the grown polysilicon layer has the advantages of large crystal size and good uniformity.

2. The trenches can be easily fabricated with existing lithography/processing techniques or other techniques.

3. Since the incompletely melted amorphous silicon layer in the trench provides a good nucleation site, the process margin of the laser thermal annealing process is very large.

4. Since the trench provides continuous nucleation sites, the grown polysilicon layer has fewer crystal boundaries.

Claims (6)

1. A method for making a polysilicon layer, characterized in that the method comprises: providing a substrate; forming a buffer layer with a plurality of first trenches on the substrate; forming an amorphous silicon layer on the buffer layer; and A laser annealing process is performed to melt the amorphous silicon layer and start to crystallize from above the first trenches to form a polysilicon layer. 2. The manufacturing method of the polysilicon layer as claimed in claim 1, wherein the forming method of the buffer layer having the trenches comprises: forming a silicon nitride layer on the substrate; forming a plurality of second trenches in the silicon nitride layer; and A conformal silicon oxide layer is formed on the silicon nitride layer to naturally form the first trenches in the silicon oxide layer. 3. The method for fabricating the polysilicon layer as claimed in claim 2, wherein the second trenches are formed by lithography/etching. 4. The manufacturing method of polysilicon layer as claimed in claim 1, is characterized in that, the forming method of the buffer layer with these trenches comprises: forming a silicon nitride layer on the substrate; forming a silicon oxide layer on the silicon nitride layer; and The first trenches are formed in the silicon oxide layer. 5. The method for fabricating the polysilicon layer as claimed in claim 4, wherein the first trenches are formed by lithography/etching. 6. The manufacturing method of the polysilicon layer as claimed in claim 1, wherein the laser annealing process is an excimer laser annealing process.

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