CN1599051A - Formation method of junction-insulated active component - Google Patents

Abstract

The present invention provides a method for forming a junction-insulated active component. A semiconductor substrate is provided, on which a plurality of predetermined active regions are provided, and at least one predetermined isolation region is provided between any two active regions; a first gate structure is formed on a portion of the substrate in the active region, and a second gate structure is formed on the substrate in the isolation region; a first ion-doped region is formed in the substrate on both sides of the first and second gate structures; an anti-reflection film is formed on the substrate and the first and second gate structures; a portion of the anti-reflection film is anisotropically removed to expose the second gate structure; the second gate structure is removed to expose the substrate surface; a second ion-doped region is formed in the substrate in the isolation region; and the anti-reflection film is removed.

Description

Formation method of junction-insulated active component

technical field

The invention relates to semiconductor integrated circuit technology, in particular to a method for forming a junction-insulated active component.

Background technique

In an integrated circuit device, active components that are isolated from each other are included. Therefore, the component isolation process has become an important part of the semiconductor process.

Shallow trench isolation (shallow trench isolation, STI) or deep trench isolation has been often used in component isolation processes. The manufacturing method first uses dry etching to remove part of the silicon substrate to form a trench, then uses a deposition method to fill the trench with dielectric materials, and then uses, for example, chemical mechanical polishing to planarize the contour of the trench surface.

Since the trench process described above requires an etching process, a deposition-filling process, and a planarization process, there are many disadvantages. For example, the trench process is quite complicated and costly, voids are easily generated in the trench during the deposition process, and crystallographic defects such as dislocations are unavoidable in the hole digging process. . These will seriously affect the reliability and quality of components.

Contents of the invention

In view of this, the object of the present invention is to provide a method for forming a junction isolation region.

Another object of the present invention is to provide a method for forming a junction-isolated active device.

According to this purpose, the present invention provides a method for forming a junction-insulated active component, comprising the following steps: providing a semiconductor substrate with a plurality of predetermined active regions on the substrate, and between any two active regions with at least a predetermined isolation region; forming a first gate structure on a portion of the substrate of the active region, and forming a second gate structure on the substrate of the isolation region; forming a first ion-doped region on the substrate In the substrate on both sides of the first and second gate structures; forming an antireflection film on the substrate and the first and second gate structures; forming a photoresist pattern in the antireflection of the active region on the film; using the photoresist pattern as a mask, anisotropic etching removes part of the anti-reflection film to expose the second gate structure; using the photoresist pattern and the remaining anti-reflection film as a mask, anisotropic etching The etching removes the second gate structure to expose the surface of the substrate; forms a second ion-doped region in the substrate of the isolation region; removes the photoresist pattern; and removes the remaining anti-reflection film.

The present invention will be described in more detail below in conjunction with the accompanying drawings and preferred embodiments.

Description of drawings

1-6 are process sectional views according to a preferred embodiment of the present invention.

Detailed ways

Embodiments of the present invention will be described below using the cross-sectional process diagrams shown in FIGS. 1-6 .

First, as shown in FIG. 1 , it provides a semiconductor substrate 100 such as silicon, which has a plurality of predetermined active areas (active areas) 110 on the substrate 100, and at least one predetermined active area 110 between any two active areas 110. The isolation area (an isolation area)120.

In FIG. 1 , a first gate structure 130 is formed on a portion of the substrate 100 in the active region 110 , and a second gate structure 140 is formed on the substrate 100 in the isolation region 120 . An example is given here to illustrate the process of forming the first and second gate structures 130, 140. First, an insulating layer (not shown) such as a _SiO2 layer is formed on the substrate 100 by thermal oxidation or deposition. Then, a conductive layer (not shown in the figure) such as a polysilicon layer is formed on the insulating layer by a deposition method. Then, through a lithographic etching process, anisotropic etching removes part of the conductive layer and the insulating layer to form a gate layer 132 and a gate oxide layer 131 on the substrate 100 of the active region 110 and the isolation region 120 . That is to say, the first and second gate structures 130 and 140 can be formed on the substrate 100 simultaneously. It should be noted here that the second gate structure 140 is used as a dummy gate structure because the second gate structure 140 will be removed in a future process.

In FIG. 1 , a first ion-doped region 150 is formed in the substrate 100 on both sides of the first and second gate structures 130 and 140 by using an ion implantation process. Wherein, the first ion-doped region 150 is used as a source/drain. In this way, an active element having the first gate structure 130 and the first ion-doped region 150 is formed.

Next, as shown in FIG. 2 , for example, a bottom anti-reflection layer 210 is formed on the substrate 100 and the first and second gate structures 130 and 140 by using a coating method. Wherein, the anti-reflection film 210 may be an organic layer, such as AR2 organic material produced by Shipley Company.

In FIG. 2, a photoresist pattern 220 is formed on the bottom antireflection film 210 of the active region 110, and then the photoresist pattern 220 is used as a mask to remove part of the antireflection film by anisotropic etching. 210 to expose the top surface of the second gate structure 140 , as shown in FIG. 3 . Wherein, the etching gas used in the anisotropic etching process in this step is, for example, HBr and O ₂ .

Next, as shown in FIG. 4 , using the photoresist pattern 220 and the remaining bottom anti-reflection film 210 as a mask, anisotropic etching removes the second gate structure 140 to expose the surface of the substrate 100 . Wherein, the etching gas used in the anisotropic etching process in this step is, for example, CCl ₄ , HBr and O ₂ .

Next, as shown in FIG. 5, using the photoresist pattern 220 and the remaining bottom anti-reflection film 210 as a mask (mask), for example, using an ion implantation process 510, a second ion-doped region 520 is formed in the isolation region 120. in the substrate 100. The process conditions of the ion implantation procedure 510 are, for example, 40-80 KeV, and the ion dose concentration is 1E18-1E19 atom/cm ² .

It should be particularly noted here that when the first ion-doped region 150 is implanted with N-type ions, the second ion-doped region 520 is implanted with P-type ions. On the contrary, when the first ion-doped region 150 is implanted with P-type ions, the second ion-doped region 520 is implanted with N-type ions. Wherein, the N-type ions are, for example, phosphorous ions or arsenic ions, and the P-type ions are, for example, boron ions. Therefore, according to the above process, the second ion-doped region 520 is used as a P-N junction isolation region (P-N junction isolation region) of the junction-isolated active device.

Next, as shown in FIG. 6 , the photoresist pattern 220 is removed by dry etching or wet etching. Then, the bottom anti-reflection film 210 is removed by dry etching or wet etching.

The process of the present invention is characterized in that: the self-alignment of the gate structure is used to define the active region and the isolation region, wherein the gate structure located in the isolation region is a dummy gate structure; and then the dummy gate structure is removed. After the gate structure, ions are implanted into the base of the isolation region to form a junction isolation region.

Therefore, advantage of the present invention has at least:

(1) Compared with the known trench isolation process, since the present invention does not need to dig a hole or the like, it can effectively avoid void defects in the substrate, thereby improving the reliability of the product.

(2) Compared with the known trench isolation process, the present invention utilizes the self-alignment of the gate structure to simultaneously define the active region and the isolation region, so that the process is simpler and the cost can be reduced.

Although the present invention is disclosed as above with preferred embodiments, it is not intended to limit the present invention, any modification and modification made by those skilled in the art without departing from the spirit and scope of the present invention, All should be included within the scope of protection required by the claims of the present invention.

Claims (18)

1. A method for forming a junction-insulated active component, comprising the following steps: providing a semiconductor substrate with a plurality of predetermined active regions on the substrate and at least one predetermined isolation region between any two active regions; forming a first gate structure on a portion of the substrate in the active region, and forming a second gate structure on the substrate in the isolation region; forming a first ion-doped region in the substrate on both sides of the first and second gate structures; forming an anti-reflection film on the substrate and the first and second gate structures; anisotropically removing part of the anti-reflection film to expose the second gate structure; removing the second gate structure to expose the substrate surface; forming a second ion-doped region in the substrate of the isolation region; and Remove the anti-reflection film. 2 . The method for forming a junction-insulated active device as claimed in claim 1 , wherein the first gate structure and the second gate structure are formed simultaneously. 3. The method for forming a junction-insulated active device as claimed in claim 1, wherein the second gate structure is used as a dummy gate structure. 4. The method for forming a junction-insulated active device as claimed in claim 2, wherein the method for forming the first gate structure and the second gate structure comprises the following steps: forming an insulating layer on the substrate; forming a conductive layer on the insulating layer; and Anisotropically removing part of the conductive layer and part of the insulating layer to form a gate layer and a gate insulating layer on the substrate. 5. The method for forming a junction-insulated active device as claimed in claim 4, wherein the insulating layer comprises silicon dioxide. 6. The method for forming a junction-insulated active device as claimed in claim 4, wherein the conductive layer comprises polysilicon. 7 . The method for forming a junction-insulated active device according to claim 1 , wherein the first ion-doped region is implanted with N-type ions, and the second ion-doped region is implanted with P-type ions. 8 . The method for forming a junction-insulated active device as claimed in claim 1 , wherein the first ion-doped region is implanted with P-type ions, and the second ion-doped region is implanted with N-type ions. 9. The method for forming a junction-insulated active device as claimed in claim 1, wherein the anti-reflection film comprises organic matter. 10. A method for forming a junction-insulated active component, comprising the following steps: providing a semiconductor substrate with a plurality of predetermined active regions on the substrate and at least one predetermined isolation region between any two active regions; forming a first gate structure on a portion of the substrate in the active region, and forming a second gate structure on the substrate in the isolation region; forming a first ion-doped region in the substrate on both sides of the first and second gate structures; forming an anti-reflection film on the substrate and the first and second gate structures; forming a photoresist pattern on the antireflection film in the active region; Using the photoresist pattern as a mask, anisotropic etching removes part of the anti-reflection film to expose the second gate structure; using the photoresist pattern and the remaining anti-reflection film as a mask, anisotropically etching to remove the second gate structure to expose the surface of the substrate; forming a second ion-doped region in the substrate of the isolation region; removing the photoresist pattern; and The remaining antireflection film is removed. 11. The method for forming a junction-insulated active device as claimed in claim 10, wherein the first gate structure and the second gate structure are formed simultaneously. 12. The method for forming a junction-insulated active device as claimed in claim 10, wherein the second gate structure is used as a dummy gate structure. 13. The method for forming a junction-insulated active device as claimed in claim 11, wherein the method for forming the first gate structure and the second gate structure comprises the following steps: forming an insulating layer on the substrate; forming a conductive layer on the insulating layer; and Anisotropically removing part of the conductive layer and part of the insulating layer to form a gate layer and a gate insulating layer on the substrate. 14. The method for forming a junction-insulated active device as claimed in claim 13, wherein the insulating layer comprises silicon dioxide. 15. The method for forming a junction-insulated active device as claimed in claim 13, wherein the conductive layer comprises polysilicon. 16 . The method for forming a junction-insulated active device according to claim 10 , wherein the first ion-doped region is implanted with N-type ions, and the second ion-doped region is implanted with P-type ions. 17 . The method for forming a junction-insulated active device according to claim 10 , wherein the first ion-doped region is implanted with P-type ions, and the second ion-doped region is implanted with N-type ions. 18. The method for forming a junction-insulated active device as claimed in claim 10, wherein the anti-reflection film comprises organic matter.

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