CN1591143B - Manufacturing method of liquid crystal display device - Google Patents

Abstract

The invention discloses a method for manufacturing a liquid crystal display device capable of improving image quality by preventing grinding defects. The method includes: preparing first and second substrates; forming a thin film transistor on the first substrate; forming a first alignment layer on the first substrate including the thin film transistor; performing grinding on the first alignment layer process and alignment process to provide a consistent alignment direction; and forming a liquid crystal layer between the first and second substrates.

Description

Manufacturing method of liquid crystal display device

This application claims the benefit of Korean Application No. P2003-58803 dated August 25, 2003 and Korean Application No. P2004-39323 dated May 31, 2004, the contents of which are incorporated herein by reference.

technical field

The present invention relates to a liquid crystal display (LCD) device. More particularly, it relates to a method of manufacturing an LCD device that improves picture quality by preventing grinding defects.

Background technique

Due to the advantages of thin thickness, light weight, and low power consumption, LCD devices have become attractive alternatives to cathode ray tubes (CRTs). LCD devices are driven by changing optical anisotropy by applying an electric field to liquid crystals having liquid and optical properties.

LCD devices are classified into various modes according to the type of liquid crystal used in the device. In particular, LCD devices can be classified into a twisted nematic (TN) mode, which controls the liquid crystal director by applying a voltage to liquid crystals whose directors are twisted by 90°; a multi-region mode, which divides each pixel into multiple regions to Obtain a wide viewing angle; optically compensated birefringence (OCB) mode, which compensates the phase change of light in the direction of propagation by forming a compensation film on the outer surface of the substrate; in-plane switching (IPS) mode, which is formed on a substrate Two electrodes, forming an electric field parallel to the two substrates; and a vertical alignment (VA) mode, which uses a negative liquid crystal and a vertical alignment layer to place the longitudinal (main) axis of the liquid crystal molecules perpendicular to the plane of the alignment layer.

Generally, an LCD device includes an upper substrate of a color filter array, a lower substrate of a thin film transistor array, and a liquid crystal layer. The upper and lower substrates face each other, and a liquid crystal layer with dielectric anisotropy is formed between the two substrates. When an LCD device is used as an optical device, it is necessary to align liquid crystal molecules of a liquid crystal layer in a predetermined direction. Thereby, an alignment layer, an organic polymer layer is formed on the substrate, wherein the alignment layer has anisotropy by grinding. LCD devices can be divided into transmissive LCD devices that use backlight as a light source, reflective LCD devices that use ambient light without a backlight, and transflective LCD devices that overcome the shortcomings of transmissive and reflective LCD devices. The transmissive LCD device has the disadvantage of high power consumption caused by the backlight source, and the problem of the reflective LCD device is that it cannot be applied to occasions where the environment is dark.

The transflective LCD device has both transmissive and reflective parts within a unit pixel, and thus the transflective LCD device can be used as a transmissive or reflective LCD device as required. Therefore, the pixel electrode may be formed as a transmissive electrode or a reflective electrode according to the kind of LCD device. For example, a transmissive electrode may be formed in a transmissive portion of a transmissive LCD device and a transflective LCD device. Meanwhile, a reflective electrode may be formed in a reflective portion of the reflective LCD device and the transflective LCD device. The transmissive electrode of the transmissive LCD device and the transflective LCD device transmits the light emitted from the backlight, passes through the lower substrate to the liquid crystal layer, and obtains high brightness. Reflective electrodes of reflective LCD devices and transflective LCD devices reflect ambient light incident through an upper substrate to obtain high luminance.

A prior art IPS mode LCD device will be described below. FIG. 1 shows a plan view of a prior art IPS (In-Plane Switching) mode LCD device. FIG. 2 shows the voltage distribution of a prior art IPS mode LCD device. 3A and 3B illustrate plan views of an IPS mode LCD device under voltage on/off conditions.

In the prior art IPS mode LCD device shown in Figure 1, the gate line 12 and the data line 15 are formed crossing each other on the substrate to define a pixel area, and the common line 24a is formed in the pixel area and connected to the gate line 12. parallel. At the same time, a thin film transistor TFT is formed at the intersection of the gate line 12 and the data line 15 , and the common electrode 24 branched from the common line 24 a is formed in the pixel region parallel to the data line 15 . The pixel electrode 17 is connected to the drain of the thin film transistor TFT and is formed between the common electrodes 24 substantially in parallel. Meanwhile, a storage electrode 25 extending from the pixel electrode 17 is formed on the gate line 12 .

In the aforementioned IPS mode LCD device, if a voltage of 5V is applied to the common electrode 24, and a voltage of 0V is applied to the pixel electrode 17, as shown in Figure 2, an equipotential plane is formed in parallel with the electrode at the corresponding part of the electrode, and the equipotential plane is formed in parallel with the electrode. The portion between the two electrodes is vertical to the electrodes. In this way, since the direction of the electric field is perpendicular to the equipotential plane, a parallel electric field is generated between the common electrode 24 and the pixel electrode 17, a vertical electric field is generated on the electrodes, and a parallel electric field and a vertical electric field are generated at the corners of the electrodes.

For IPS mode LCD devices, the arrangement of liquid crystal molecules can be adjusted by an electric field. For example, as shown in FIG. 3A, if a voltage is applied to the liquid crystal molecules 31 initially aligned in the same direction as the transmission axis of the polarizer, then as shown in FIG. 3B, the longitudinal axes of the liquid crystal molecules 31 are aligned parallel to the direction of the electric field. In particular, first and second polarizers are formed on outer surfaces of the lower substrate and the upper substrate, wherein transmission axes of the first and second polarizers are perpendicular to each other. Since the alignment layer of the lower substrate is ground parallel to the transmission axis of either polarizer, it generally appears in a normally black mode. That is, if no voltage is applied to the device, the liquid crystal molecules 31 will be aligned as shown in FIG. 3A, displaying a black state. If a voltage is applied to the device, as shown in FIG. 3B, the alignment of the liquid crystal molecules 31 is parallel to the electric field, thereby displaying a white state. In FIGS. 3A and 3B , unexplained reference numerals "24" and "17" denote a common electrode and a pixel electrode, respectively. Therefore, the IPS mode LCD device has a wider viewing angle than the TN mode LCD device.

A method of manufacturing the aforementioned LCD device will be described in detail below. The TN mode LCD device, the transflective mode LCD device and the IPS mode LCD device have similar manufacturing processes. A method of manufacturing an IPS mode LCD device will be described below. 4A to 4D show cross-sectional views of a manufacturing process of a related art IPS mode LCD device.

As shown in FIG. 4A, a low-resistance metal layer is deposited on the lower substrate 11 by sputtering, which is then patterned to form gate lines (not shown) and gate electrodes 12a. A common line (not shown) parallel to the gate lines and a plurality of common electrodes 24 branched from the common line are formed simultaneously. Thereafter, the gate insulating layer 13 is formed by depositing a silicon nitride SiNx layer on the entire surface of the lower substrate 11 including the gate lines. Then, an amorphous silicon layer is deposited on the entire surface of the lower substrate 11 and selectively removed to form a semiconductor layer 14 on the gate insulating layer 13 on the gate electrode 12a.

Referring to FIG. 4B, a low-resistance metal layer is deposited on the gate insulating layer 13 by sputtering and then patterned to form data lines (not shown) and source/drain electrodes 15a and 15b. Next, a plurality of pixel electrodes 17 connected to the drain electrodes 15b and parallel to the data lines are formed. The pixel electrodes 17 are placed between each of the common electrodes 24 , so that the pixel electrodes 17 and the common electrodes 24 are arranged alternately. At this time, the pixel electrode 17 may be formed simultaneously with the metal data line, or additionally formed through a transparent conductive layer such as ITO. Also, the pixel electrode 17 and the common electrode 24 may be formed in a straight line or in a zigzag. Next, as shown in FIG. 4C , a passivation layer 16 is formed on the entire surface of the lower substrate 11 including the data lines 15 by depositing or coating a silicon nitride layer or an organic insulating layer of BCB. In addition, the first alignment layer 50 is formed on the passivation layer 16, which is then polished.

As shown in FIG. 4D, a metal black matrix layer 22 such as Cr or CrOx is used to form on the upper substrate 21 to prevent light leakage, and the R/G/B color filter layer 23 is deposited between each black matrix 22 by an electrodeposition method, Formed by a pigment jet method or a coating method to realize various colors. Next, a second alignment layer 60 is deposited thereon. Meanwhile, a sealant (not shown) is formed on the lower substrate 11 or the upper substrate 21 , and a spacer (not shown) is formed on either one of the two substrates 11 and 21 . Thus, the two substrates 11 and 21 are opposed to each other and bonded together. Then, the liquid crystal 30 is injected between the lower substrate 11 and the upper substrate 21 bonded together, and the first polarizer 81 and the second polarizer 82 are respectively formed on the outer surfaces of the lower and upper substrates 11 and 21, thus completing Fabrication of Prior Art IPS Mode LCD Devices. At this time, the transmission axes of the first polarizer 81 and the second polarizer 82 are perpendicular to each other, and one of the transmission axes is in the same direction as the electric field.

The grinding process is described in detail below. FIG. 5 shows a cross-sectional view for explaining a prior art grinding process. The lapping process involves forming an organic high-polymer layer called an alignment layer on a substrate and obtaining its internal anisotropy. That is, polyamic acid or soluble polyimide is coated on the substrate, and treated at a temperature between 60°C to 80°C and 80°C to 200°C, so that the coated polyamic acid or soluble polyimide A polyimide layer is formed. As shown in FIG. 5 , the polyimide layer is ground using a cylindrical grinding roll 70 . The grinding process mechanically grinds the surface of the polyimide layer by rotating a cylindrical grinding roll 70 coated with a grinding cloth 71 such as nylon or rayon. However, the seams on the grinding cloth 71 of the cylindrical grinding roll 70 can produce vertical or horizontal bands. Also, the end of the grinding cloth may come off from the grinding roller.

The aforementioned prior art IPS mode LCD device has the following disadvantages.

的阶梯镀层在像素电极和薄膜晶体管的漏极的接触部分形成。在定向层的研磨过程中，研磨布不与阶梯镀层相对低的部分接触，这样会产生研磨缺陷。参考图6，由于在没有定向图形的部分无法控制液晶的排列，在初始黑色状态下会发生光漏。图像的质量由于较低的对比度而受到损害。同时，由于研磨布的不均匀造成定向图形不均匀，在没有阶梯镀层的表面也会由于不充分研磨而发生光漏。Figure 6 shows a photograph of light leakage from a prior art LCD device on a surface with a step plating. Fig. 7 shows a photograph of light leakage of a prior art LCD device on a surface without a step plating. Referring to FIG. 6, the thin film transistor array substrate has step plating on the surface in each mode. That is, in a TN mode LCD device, the thin film transistor part and the crossing part of the gate line and the data line are relatively higher than other parts of the thin film transistor array substrate. In a transflective LCD device, for example, a step plating layer is formed between the transmissive part and the reflective part in the pixel region. Furthermore, in LCD devices such as IPS mode, with approximately The stepped plating layer is produced by the pattern of the common electrode 24 and the pixel electrode 17 . During the grinding process of the alignment layer 50, the grinding cloth 71 is not in contact with the relatively lower portion of the step plating layer, which may cause grinding defects. Furthermore, in IPS mode LCD devices employing three rounds of masking, approximately

A step plating layer is formed at the contact portion of the pixel electrode and the drain of the thin film transistor. During the grinding of the alignment layer, the grinding cloth does not come into contact with the relatively lower portion of the step coating, which may cause grinding defects. Referring to FIG. 6, since the alignment of the liquid crystal cannot be controlled at a portion without an orientation pattern, light leakage occurs in an initial black state. The quality of the image suffers due to the lower contrast. At the same time, due to the non-uniform orientation pattern caused by the unevenness of the abrasive cloth, light leakage will also occur due to insufficient grinding on the surface without step coating.

Contents of the invention

SUMMARY OF THE INVENTION Accordingly, it is an object of the present invention to provide a method of manufacturing a liquid crystal display (LCD) device that substantially overcomes one or more of the problems due to limitations and disadvantages of the related art.

An advantage of the present invention is to provide a manufacturing method of an LCD device, which can prevent light leakage due to grinding defects, and improve contrast by optimizing alignment processes such as grinding process and ion beam irradiation/light irradiation/plasma irradiation.

Additional features and advantages of the invention are set forth hereinafter, some of which can be learned from the description or learned by practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structures specifically described in the specification and claims hereof as well as the appended drawings.

In order to achieve these objects and other advantages, according to the present invention, as specifically and generally described herein, a method of manufacturing an LCD device includes: preparing first and second substrates; forming a thin film transistor on the first substrate; A first alignment layer is formed on the first substrate of the transistor; grinding and alignment processes are performed on the first alignment layer to provide a consistent alignment direction; a liquid crystal layer is formed between the first and second substrates, wherein the alignment The alignment process is to irradiate light on the first alignment layer, and wherein the light includes one of partially polarized light and linearly polarized light.

In another embodiment, a method for manufacturing an LCD device includes: preparing a first substrate and a second substrate; forming a thin film transistor on the first substrate; forming a first alignment layer on the first substrate including the thin film transistor; Grinding and alignment processes are performed on the first alignment layer to provide a consistent alignment direction; a second alignment layer is formed on the second substrate; grinding and alignment processes are performed on the second alignment layer; A liquid crystal layer is formed between the substrates, wherein the alignment process is to irradiate light on the first alignment layer, and wherein the light includes one of partially polarized light and linearly polarized light.

Both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the invention as claimed.

Description of drawings

The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this invention, illustrate various embodiments of the invention and together with the description serve to explain the principles of the invention.

FIG. 1 shows a plan view of a prior art IPS (In-Plane Switching) mode LCD device;

Fig. 2 shows the voltage distribution of the prior art IPS mode LCD device;

3A and 3B show plan views of an IPS mode LCD device when the voltage is on/off;

4A to 4D show cross-sectional views of the prior art IPS mode LCD device manufacturing process;

Figure 5 shows a cross-sectional view explaining the prior art grinding process;

Fig. 6 shows the photo that is used to explain light leakage on the surface of the prior art LCD device with step plating;

7 shows photographs used to explain light leakage from the surface of a prior art LCD device having no stepped portion;

FIG. 8 shows a plan view of an IPS mode LCD device based on the first embodiment of the present invention;

9A to 9E show a cross-sectional view of the manufacturing process of the IPS mode LCD device according to the first embodiment of the present invention, taken along the line I-I' shown in FIG. 8;

Fig. 10 shows a cross-sectional view of an ion beam irradiation device based on the present invention;

Figure 11 shows a schematic diagram of a light irradiation device based on the present invention;

12A to 12C are cross-sectional views showing a manufacturing process of an LCD device according to a second embodiment of the present invention.

FIG. 13A shows a plan view of another type of IPS mode LCD device based on the first and second embodiments of the present invention, and FIG. 13B shows another type of IPS mode LCD based on the first and second embodiments of the present invention. A plan view of the device;

FIG. 14 shows a cross-sectional view of another type of IPS mode LCD device based on the present invention;

15A to 15I show cross-sectional views taken along line II-II' in FIG. 8, showing a manufacturing process of an LCD device using a three-round mask process according to the third embodiment of the present invention;

16A to 16D show cross-sectional views of a manufacturing process of a TN mode LCD device based on a fourth embodiment of the present invention;

17A to 17E show cross-sectional views of the manufacturing process of the transflective LCD device based on the fifth embodiment of the present invention;

18A to 18D are cross-sectional views showing a manufacturing process of a VA mode LCD device according to a sixth embodiment of the present invention;

FIG. 19 shows photographs of light leakage in an LCD device based on the present invention.

Detailed ways

The preferred embodiments of the invention will now be described in detail, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers will be used throughout the drawings to refer to the same or like parts.

FIG. 8 shows a plan view of an IPS mode LCD device according to the first embodiment of the present invention. 9A to 9E show cross-sectional views of the manufacturing process of the IPS mode LCD device taken along line I-I' in FIG. 8 . Fig. 10 shows a cross-sectional view of an ion beam irradiation device based on the present invention. Fig. 11 shows a schematic diagram of a light irradiation device based on the present invention.

As shown in FIG. 8 , the LCD device according to the first embodiment of the present invention includes gate lines 112 , data lines 115 , common lines 124 a, thin film transistors TFT, common electrodes 124 , pixel electrodes 117 and storage electrodes 125 . The gate lines 112 and the data lines 115 are formed perpendicular to each other on the substrate to define a pixel area. The common line 124a is substantially parallel to the gate line 112 in the pixel area, and the thin-film transistor TFT is formed at the intersection of the gate line 112 and the data line 115. The thin-film transistor includes a gate 112a, a semiconductor layer 114 and a source/drain 115a/ 115b. In addition, the common electrode 124 branched from the common line 124a is parallel to the data line 115 in the pixel area. The pixel electrode 117 is formed between the substantially parallel common electrodes 124 and connected to the drain 115b of the thin film transistor TFT. The storage electrode 125 extending from the pixel electrode 117 is formed over the common line 124a.

A method of manufacturing an IPS mode LCD device based on the first embodiment of the present invention will be described below.

As shown in FIG. 9A, a low-resistance metal layer with specific impedance is formed on the lower substrate 111 to prevent signal delay, and then it is patterned by a photolithography process to form gate lines ('112' in FIG. 8) and slave gate lines. The gate 112a of the thin film transistor TFT branched out from the line. The low-resistance metal layer can be formed with copper (Cu), aluminum (Al), aluminum neodymium (AlNd), molybdenum (Mo), chromium (Cr), titanium (Ti), tantalum (Ta) or tungsten-molybdenum alloy (MoW) . When forming the gate line and the gate 112a, the common line ('124a' in FIG. 8) is parallel to the gate line, and a plurality of common electrodes 124 branched from the common line are formed at the same time. Furthermore, an inorganic insulating layer made of silicon nitride (SiNx) or silicon oxide (SiOx) is formed on the entire surface of the lower substrate 111 including the gate 112a by a PECVD (Plasma Enhanced Chemical Vapor Deposition) process, thereby forming gate insulating layer 113 . Then, an amorphous silicon layer is formed on the gate insulating layer 113 and is selectively removed to form an island-like (insulated) semiconductor layer 114 on the gate insulating layer 113 on the gate 112a. In addition, the ohmic contact layer can be patterned by implanting impurity ions into the amorphous silicon layer.

In FIG. 9B, a metal layer composed of Cr, Cu, Al, Mo, Ti, Ta, MoW or AlNd is formed on the entire surface of the gate insulating layer 113, and is patterned by photolithography, thereby simultaneously forming the data line 115. and source/drain 115a/115b. The data line 115 and the gate line vertically define a pixel area, and the source/drain 115a/115b are formed on both sides of the semiconductor layer 114 . Thereafter, a silicon nitride layer or BCB organic insulating layer forms a passivation layer 116 and a contact hole (not shown, FIG. 119 out of 8). Thereafter, a transparent conductive layer (ITO or IZO) is deposited on the entire surface of the lower substrate 111, which is patterned to form a plurality of pixel electrodes 117 between the common electrodes 124, each pixel electrode 117 being connected to the drain electrode 115b in parallel on the data line 115. Thus, the pixel electrodes 117 are formed alternately with the common electrodes 124 . Although not shown, if the pixel electrode 117 is formed using a metal material, before forming the passivation layer, the pixel electrode 117 may be formed simultaneously using the same material as the data line.

In FIG. 9C , polyimide resin having thermal resistance and strong affinity for liquid crystals is formed on the entire surface of the lower substrate 111 including the pixel electrodes 117 . Then, the printed polyimide resin is dried to form the first alignment layer 150 . By irradiating the device 190 with an ion beam, an ion beam is irradiated to the first alignment layer 150 . It is important that the ion beam is irradiated in the same direction as the milling direction. After the ion beam irradiated the first alignment layer 150, as shown in Figure 9D, the first alignment layer 150 is ground by a cylindrical roller 170, and the cylindrical roller is covered with a grinding cloth 171 of nylon or rayon, so that in the first polarized direction to form an orientation direction. By using a grinding process on the alignment layer, physical and chemical properties of the first alignment layer 150 are changed, thereby forming an alignment direction. The alignment direction can be uniformly formed on the entire surface of the substrate by an alignment direction alignment process (ion beam irradiation, light irradiation or plasma irradiation). In this way, even if the abrasive cloth cannot contact the alignment layer due to the step plating on the substrate, there will be no problem of abrasive defects.

As shown in FIG. 10 , ion beam 580 is generated by electron collision of neutral gas in plasma emission region 551 of the ion beam irradiation device, then accelerated through extraction region 571 , and then sent to lower substrate 111 through plasma beam region 591 . Specifically, ion beam 580 is generated by electron collisions of a neutral gas within plasma emission region 551 . The electrons are then emitted through the heating wire of the anode 553 and then accelerated by the potential difference between the anode 553 and the cathode 554 . Thus, the emitted plasma exists in the cavity 550 and the plasma grid, and is emitted to the outside through the extraction region 571 and the plasma beam region 591 . As a result, the plasma reaches the grounded target substrate 111 on which the alignment layer is deposited. The substrate 111 can be placed differently according to the irradiation direction of the ion beam 580 to control the alignment direction, so that the pretilt angle can be controlled by controlling the irradiation angle, irradiation time and energy density of the ion beam. Typically, argon ions are used in ion beam processes. Light irradiation may also be used instead of ion beam irradiation.

The alignment layer can be made of polyimide, polyamic acid, polyvinyl cinnamate, polyazobenzene (polyazobenzene), polyethyleneimine, polyvinyl alcohol, polyamide, polyethylene, polystyrene, polystyrene naphthalene Polyphenylenephthalamide, polyester, polyurethane or polymethylmethacrylate. Additionally, partially polarized, linearly polarized, or unpolarized light may be used. Also, light with a wavelength of 200nm to 450nm and an energy of 0.1J to 10J can be used for irradiation. Using light with an energy between 0.1 J and 5 J can reduce damage to the first alignment layer 150 . Thereafter, the light is irradiated obliquely with respect to the substrate or irradiated perpendicularly with respect to the substrate.

A brief introduction to the light irradiation device is given below. As shown in Figure 11, the light irradiation device comprises a lamp 201, a lampshade 202, a first plane mirror 203, a convex lens 204, a polarization system 205, a fly eye lens 206, a second plane mirror 207, a UV illumination photometer 211, a curved mirror 208 and a third plane mirror 209. The lamp 201 emits UV light in one direction, and the first flat mirror 203 reflects the UV light emitted by the lamp 201 . After that, the convex lens 204 focuses the UV light reflected by the first plane mirror 203, the polarized array system 205 performs partial or linear polarized array on the light focused by the convex lens 204, and the fly-eye lens 206 classifies and focuses the polarized array light. After that, the second plane mirror 207 reflects the light transmitted by the fly-eye lens 206, and the UV illumination photometer 211 is set in the second plane mirror 207 to detect the illumination intensity of the light. Also, the curved mirror 208 and the third flat mirror 209 transmit the light to the alignment layer. In this case, the partial array system 205 may or may not be used. That is, if irradiated with UV light, it is also possible to use unpolarized light.

If partially polarized light is irradiated, the polarization system 205 is formed by forming a quartz substrate, so that an appropriate polarization intensity can be obtained by controlling the number of quartz substrates. Thus, on a large-sized substrate, light can be easily irradiated onto the substrate. Furthermore, if unpolarized light is used, there is no need to provide a polarization system 205 . If linearly polarized light is used, a linear polarizer can be used. In the case of light irradiation, parallel light is preferable. Also, in the case of irradiating polarized light, it is important to make the polarization direction of the light the same as the direction of the alignment process. At this time, the polarization direction of the alignment process can adopt the polarized light perpendicular to the grinding direction.

As shown in FIG. 9E , a black matrix layer 123 is formed on the upper substrate 121 to prevent light leakage at portions corresponding to gate lines, data lines and thin film transistors, in which liquid crystals are not controlled. The black matrix layer 123 can be made of metal material with high elasticity, such as chromium Cr, chromium oxide CrOx or black resin. Next, the R/G/B color filter layer 122 realizes various colors by means of electrodeposition, pigment spraying or coating. Although not shown, on the upper substrate 121 including the color filter layer 122 , a protection layer is formed to protect the color filter layer 122 .

Next, a polyimide material having strong affinity for liquid crystal materials and strong photosensitive properties is formed on the protective layer, thereby forming the second alignment layer 160 . The second alignment layer 160 forms an alignment direction in a second polarization direction perpendicular to the first alignment layer 150 . Similar to the alignment process of the first alignment layer 150, the alignment process of the second alignment layer 160 is accomplished by jointly performing a grinding process and an alignment process (ion irradiation, light irradiation, or plasma irradiation). Next, column spacers 129 are formed on the upper substrate 121 or the lower substrate 111 , and the liquid crystals are distributed on the display area of the upper substrate 121 or the lower substrate. Next, a sealing layer without an injection port is formed on the periphery of the upper substrate 121 or the lower substrate 111, and the upper substrate 121 and the lower substrate 111 are bonded together in a vacuum state. Alternatively, the spacer may be distributed after forming a sealing layer with injection ports on the periphery of the upper substrate 121 or the lower substrate 111 , and then the upper substrate 121 and the lower substrate 111 are bonded to each other with a spacer formed therebetween. Then, the liquid crystal 130 is injected between the upper and lower substrates 121 and 111 in a vacuum state. In particular, the liquid crystal layer may be formed by a liquid crystal injection method or a liquid crystal distribution method. Next, first and second polarizers 181 and 182 are formed on the outer surfaces of the upper and lower substrates 121 and 111, thereby manufacturing an IPS mode LCD device.

The transmission axes of the polarization axes of the first and second polarizers 181 and 182 are perpendicular to each other, any of which is formed in the same direction as the electric field direction. When no voltage is applied to the LCD device, the polarization axis of the first or second polarizer formed on the upper or lower substrate is perpendicular to the longitudinal (main) axis of the liquid crystal molecules, thereby displaying a normally black mode. If a voltage is applied to the LCD device, the longitudinal axes of the liquid crystal molecules are twisted so that the incident light irradiated on the first polarization axis formed on the lower substrate is transmitted to the second polarization axis on the upper substrate, displaying a normally white mode . The normally black mode can be changed to the normally white mode by changing the direction of the polarization axis and the type of liquid crystal molecules. In the manufacturing method of the LCD device of the first embodiment, it is more effective to perform an alignment process (ion beam irradiation, light irradiation or plasma irradiation) after the grinding process.

12A to 12C are cross-sectional views showing a process of manufacturing an LCD device according to a second embodiment of the present invention. In the manufacturing process of the LCD device according to the second embodiment of the present invention, the gate 112a, the common electrode 124, the data line, the source/drain 115a/115b and the pixel electrode are formed as shown in FIGS. 9A and 9B.

As shown in FIG. 12A , polyimide resin with thermal resistance and strong affinity for liquid crystals is printed on the entire surface of the substrate, and dried to form polyimide, thereby forming the first alignment layer 150 . Subsequently, the first alignment layer 150 is ground using a cylindrical roller 170 attached with a nylon cloth 171 . The orientation direction is formed in the first polarization direction. The nylon cloth 171 may not be in contact with the alignment layer corresponding to the stepped portion on the substrate during the grinding process, therefore, the alignment layer corresponding to the stepped portion may not be aligned.

Therefore, as shown in FIG. 12B , by irradiating the device 190 with an ion beam, the ion beam is irradiated on the first alignment layer 150 polished by the polishing cloth 171 . The ion beam may be irradiated on the entire surface of the first alignment layer 150, or after the first alignment layer 150 is masked, irradiated on the first alignment layer 150 except the stepped portion formed by the common electrode and the pixel electrode. The remaining part. As shown in FIG. 12C, a light irradiation device 200 may be used instead of the ion beam irradiation device. The light is irradiated on the first alignment layer 150 polished by the polishing cloth 171 to complete the alignment process. In this case, the light can be irradiated on the entire surface of the first alignment layer 150, or after the first alignment layer 150 is masked, it can be irradiated on the first alignment layer except the step plating formed by the common electrode and the pixel electrode. to the remainder of layer 150. Ion beam irradiation or photoirradiation is performed under the same conditions as in the aforementioned first embodiment of the present invention.

As shown in FIG. 9E , the second alignment layer 160 is formed on the upper substrate 121 , where the second alignment layer 160 forms an alignment pattern as a second polarization direction perpendicular to that of the first alignment layer 150 . Similar to the first alignment layer 150, the alignment process (ion beam irradiation, light irradiation or plasma irradiation) can be performed after the grinding process, and then the two substrates are bonded together to form a liquid crystal layer between the two substrates. When the IPS mode LCD device is applied to the first and second embodiments of the present invention to form the zigzag common electrode 124 and the zigzag pixel electrode 117, the aforementioned grinding process and alignment process can be used together.

FIG. 13A shows a plan view of an alternative IPS mode LCD device based on the first and second embodiments of the present invention. FIG. 13B shows a plan view of another IPS mode LCD device based on the first and second embodiments of the present invention. As shown in FIGS. 13A and 13B , when the IPS mode LCD device includes a zigzag common electrode 124 and a zigzag pixel electrode 117 , the aforementioned grinding process and alignment process can be used together.

In the IPS mode LCD device based on the first and second embodiments of the present invention, the common electrode 124 can be formed from the same material as the gate line on the same layer, and the pixel electrode can be formed from the same material as the source/drain electrode on the same layer. Formed from the same material. The aforementioned grinding process can also be used in an IPS mode LCD device including a pixel electrode formed of a transparent conductive layer (ITO or IZO), and a common electrode formed of the same material as the pixel electrode (ITO or IZO) on the same layer And alignment process to increase the aperture ratio.

FIG. 14 shows a cross-sectional view of an IPS mode LCD device based on the present invention, wherein the pixel electrodes and common electrodes are formed of transparent conductive layers. That is, a gate line (not shown) having a gate 112a is formed on the substrate, and a gate insulating layer 113 is formed on the entire surface of the substrate including the gate 112a. Then, a semiconductor layer 114 is formed on the gate insulating layer 113 over the gate electrode 112a. Also, the data lines are formed vertically to the gate lines. Meanwhile, a source electrode 115 a and a drain electrode 115 b are formed on both sides of the semiconductor layer 114 . Then, a passivation layer 116 having a contact hole on the drain is formed on the entire surface of the substrate including the source 115a and the drain 115b. Then, a common electrode 124 and a pixel electrode 117 formed of a transparent conductive layer are formed on the passivation layer 116 in the pixel region. At this time, the pixel electrode 117 and the common electrode 124 are formed in parallel at a fixed interval. At the same time, the first alignment layer 150 is formed on the entire surface of the substrate. Similar to the first and second embodiments of the present invention, the grinding process and the alignment process may be used together to perform the alignment process on the first alignment layer.

In the manufacturing method of the LCD device of the IPS mode that adopts the three-round mask, because there is a stepped portion at the contact portion between the pixel electrode and the drain electrode of the thin film transistor, the grinding process and the alignment process (using, for example, ion beam irradiation , light irradiation or plasma irradiation) together, can prevent grinding defects. This embodiment will be described in detail with reference to FIGS. 15A to 15I. Among them, FIGS. 15A to 15I show cross-sectional views taken along the line II-II' in FIG. 8 of the LCD device according to the third embodiment of the present invention using a three-round mask.

As shown in FIG. 15A, a low-resistance metal layer with a specific low resistance is formed on the lower substrate 111 to prevent signal delay, and then it is patterned by a photolithography process to form the gate line and the gate 112a of the thin film transistor. 112a is branched from the gate line. The low-resistance metal layer can be made of copper (Cu), aluminum (Al), aluminum neodymium (AlNd), molybdenum (Mo), chromium (Cr), titanium (Ti), tantalum (Ta) or tungsten-molybdenum alloy (MoW) form. When forming the gate line and the gate 112a, a common line and a plurality of common electrodes are formed at the same time, the common line is parallel to the gate line, and a plurality of common electrodes 124 are branched from the common line. Furthermore, an inorganic insulating layer made of silicon nitride (SiNx) or silicon oxide (SiOx) is formed on the entire surface of the lower substrate 111 including the gate electrode 112a by PECVD (Plasma Enhanced Chemical Vapor Deposition), thereby forming the gate electrode 112a. Pole insulating layer 113. Then, an amorphous silicon layer 135 such as Cr, Cu, Al, Mo, Ti, Ta, MoW or AlNd and a metal layer 136 are sequentially formed on the gate insulating layer 113 , and a photoresist 137 is formed on the metal layer 136 . In addition, the ohmic contact layer can be patterned by implanting impurity ions into the amorphous silicon layer.

In FIG. 15B, photoresist 137 is patterned by exposure and development processes using a half-tone mask. That is, the photoresist 137 remains on the channel part, the source electrode, the drain region and the data line of the thin film transistor, and the photoresist 137 on other parts is removed. The part of the photoresist 137 in the channel region of the TFT is thinner than the photoresist in other regions.

As shown in FIG. 15C, the exposed metal layer 136 and the amorphous silicon layer 135 are selectively removed using the photoresist 137 as a mask, thereby forming the data line 115 and the semiconductor layer 114. The data line 115 is perpendicular to the gate line, A pixel area is defined. The photoresist 137 corresponding to the channel region of the thin film transistor is removed by ashing. Then, the metal layer 136 corresponding to the channel region of the TFT is selectively removed by using the photoresist 137 as a mask, so as to form the source 115 a and the drain 115 b on both sides of the semiconductor layer 114 .

As shown in FIG. 15D , a silicon nitride layer or an organic insulating layer such as BCB is formed on the entire surface of the lower substrate 111 including the data line 115 , thereby forming a passivation layer 116 . A photoresist 138 is then formed on the passivation layer 116 . Referring to FIG. 15E, the photoresist 138 is patterned by exposure and development processes, and the passivation layer 116 is selectively removed using the photoresist 138 as a mask to form a contact hole on the drain 115b. Next, the passivation layer 116 of the pixel area is removed.

Referring to FIG. 15F , a transparent conductive layer 139 is formed on the entire surface of the lower substrate 111 including the photoresist 138 . Next, as shown in FIG. 15G , the photoresist 138 is removed by a lifting method, and at the same time, the transparent conductive layer 139 on the photoresist 138 is removed, thereby forming a pixel electrode 117 connected to the drain electrode 115b in the pixel region. The pixel electrodes 117 are parallel to the data lines 115 and formed between the common electrodes. In particular, a plurality of pixel electrodes 117 and common electrodes are formed in an alternating pattern. In addition to transparent conductive layers, metal layers can also be used to form pixel electrodes by depositing and removing them using a lift-off method. On top of this, polyimide resin having a strong affinity for liquid crystals is printed on the substrate, and dried to form imide, and then the first alignment layer 150 is formed.

As shown in FIG. 15H , the first alignment layer 150 is ground by a cylindrical roller 170 on which a grinding cloth 171 of nylon or rayon is attached. As shown in FIG. 15I , the ion beam or light is irradiated on the first alignment layer 150 polished by the polishing cloth 171 , and the alignment direction is aligned by using the ion beam emitter 190 or the light irradiator 200 . Ion beam or light can be irradiated on the whole surface of the first alignment layer 150, or after the mask is processed on the first alignment layer 150, it is irradiated to the step plating layer except the contact portion between the pixel electrode and the drain electrode of the thin film transistor. The rest of the outer first alignment layer 150. The ion beam or light is irradiated in the same direction as the milling direction.

As in the first embodiment of the present invention, plasma irradiation may be used. In the case of using light to form an alignment layer, partially polarized light, linearly polarized light, or non-polarized light is irradiated under the same conditions as in the first embodiment of the present invention. In this case, after ion beam irradiation, light irradiation, or plasma irradiation, a grinding process is performed. In the third embodiment of the present invention, the irradiation conditions of ion beams or light are the same as those of the first embodiment of the present invention. Thereby, in the IPS mode LCD device adopting the three-wheel mask of the present invention, it is possible to avoid the light leakage caused by the inconsistency of the alignment direction of the liquid crystal caused by the grinding defect and the generation of the step portion at the contact portion between the pixel electrode and the drain electrode. of light leaks. This results in high contrast.

The orientation alignment process can also be applied to various LCD devices using grinding processes, such as TN (twisted nematic) mode, OCB (optical control birefringence) mode, VA (vertical alignment) mode, COT (color filter in TFT On Array) mode and TOC (TFT Array On Filter) mode, and IPS mode. The problem of grinding defects can be solved by adopting alignment alignment process. The manufacturing methods of TN mode, transflective and VA mode LCD devices are introduced below.

16A to 16D show cross-sectional views of a TN mode LCD device according to a fourth embodiment of the present invention. As shown in FIG. 16A, a low-resistance metal layer with a specific low resistance is formed on the lower substrate 111, and then it is patterned by a photolithography process to form a gate line (not shown) and a gate 112a of a thin film transistor. 112a is branched from the gate line. The low-resistance metal layer can be formed with copper (Cu), aluminum (Al), aluminum neodymium (AlNd), molybdenum (Mo), chromium (Cr), titanium (Ti), tantalum (Ta) or tungsten-molybdenum alloy (MoW) . Furthermore, an inorganic insulating layer made of silicon nitride (SiNx) or silicon oxide (SiOx) is formed on the entire surface of the lower substrate 111 including the gate electrode 112a by PECVD (Plasma Enhanced Chemical Vapor Deposition), thereby forming the gate electrode 112a. Pole insulating layer 113. Then, an amorphous silicon layer is formed on the gate insulating layer 113 and is selectively removed to form an island-shaped semiconductor layer 114 on the gate insulating layer 113 on the gate 112a. In addition, the ohmic contact layer can be patterned by implanting impurity ions into the amorphous silicon layer. A metal layer made of Cr, Cu, Al, Mo, Ti, Ta, MoW or AlNd is formed on the entire surface of the gate insulating layer 113, and it is patterned by photolithography, thereby simultaneously forming the data line 115 and the source pole/drain 115a/115b. The data line 115 and the gate line vertically define a pixel area, and the source/drain 115a/115b are formed on both sides of the semiconductor layer 114 . Thereafter, a passivation layer 116 is formed on the entire surface of the lower substrate 111 including the data lines 115 .

Referring to FIG. 16B, the part of the passivation layer 116 corresponding to the drain electrode 115b is removed to form a contact hole. Next, a transparent conductive layer is deposited on the entire surface of the lower substrate 111, wherein the transparent conductive layer is electrically connected to the drain 115b through the contact hole. In addition, the transparent conductive layer is selectively removed, and the remaining part forms the pixel electrode 117 in the pixel area. Then, polyimide resin having thermal resistance and strong affinity to liquid crystals is formed on the entire surface of the lower substrate 111 including the pixel electrodes 117 . Then, the printed polyimide resin is dried into imide to form the first alignment layer 150 .

As shown in FIG. 16C , the first alignment layer 150 is ground by a cylindrical roller 170 on which a nylon or rayon grinding cloth 171 is attached, thereby forming a first polarization direction on the first alignment layer 150 . As shown in FIG. 16D , the alignment direction of the first alignment layer 150 is aligned using an ion beam irradiator 190 or a light irradiator 200 . The ion beam can be irradiated on the entire surface of the first alignment layer 150, or after the masked first alignment layer 150, irradiate the stepped part except the intersection of the gate line and the data line and the step plating layer of the thin film transistor. the remainder of . At this time, the irradiation direction of the ion beam or light is the same as the polishing direction.

As described in the first embodiment of the present invention, plasma irradiation may be used. In the case of using light, the alignment layer is deposited and irradiated with partially polarized light, linearly polarized light or non-polarized light under the same conditions as in the first embodiment of the present invention. In this case, after ion beam irradiation, light irradiation, or plasma irradiation, a grinding process is performed. In the fourth embodiment of the present invention, the irradiation conditions of ion beams or light are the same as those of the first embodiment of the present invention. Thus, the same process as that of the first embodiment of the present invention is carried out. Therefore, for LCD devices in TN mode, it is possible to avoid light leakage due to inconsistency of liquid crystal orientation caused by grinding defects, light leakage at the intersection of gate lines and data lines, and light leakage at the step plating of thin film transistors , resulting in high contrast.

In addition, although not shown, the manufacturing method of the fourth embodiment of the present invention can be applied to the TOC mode using the TN mode process by forming the color filter layer on the substrate, and by forming the color filter layer on the passivation layer after Forming pixel electrodes applied to COT mode. In this way, an additional protective layer can be formed on the above-mentioned TOC mode and COT mode.

17A to 17E are cross-sectional views showing a manufacturing process of a transflective LCD device according to a fifth embodiment of the present invention. In the transflective LCD device according to the fifth embodiment of the present invention, the pixel area is divided into a transmissive part and a reflective part.

As shown in FIG. 17A, a low-resistance metal layer with a specific low resistance is formed on the lower substrate 111 to prevent signal delay, and then it is patterned by a photolithography process to form gate lines (not shown) and slave gate lines. The gate 112a of the bifurcated thin film transistor. The low-resistance metal layer can be formed with copper (Cu), aluminum (Al), aluminum neodymium (AlNd), molybdenum (Mo), chromium (Cr), titanium (Ti), tantalum (Ta), or tungsten-molybdenum alloy (MoW) . Furthermore, an inorganic insulating layer made of silicon nitride (SiNx) or silicon oxide (SiOx) is formed on the entire surface of the lower substrate 111 including the gate electrode 112a by PECVD (Plasma Enhanced Chemical Vapor Deposition), thereby forming the gate electrode 112a. Pole insulating layer 113. Then, an amorphous silicon layer is formed on the gate insulating layer 113 and is selectively removed to form an island-shaped semiconductor layer 114 on the gate insulating layer 113 on the gate 112a. In addition, the ohmic contact layer can be patterned by implanting impurity ions into the amorphous silicon layer. A metal layer composed of Cr, Cu, Al, Mo, Ti, Ta, MoW, or AlNd is formed on the entire surface of the gate insulating layer 113, and it is patterned by photolithography, thereby forming the data line 115 and the source line at the same time. pole/drain 115a/115b. The data line 115 and the gate line vertically define a pixel area, and the source/drain 115a/115b are formed on both sides of the semiconductor layer 114 . In this way, the passivation layer 116 is formed on the entire surface of the substrate including the data line 115 .

As shown in FIG. 17B, the portion of the passivation layer 116 corresponding to the drain electrode 115b is removed to form a contact hole. At the same time, the passivation layer 116 of the transmissive portion is removed. Next, the metal layer connected to the drain electrode 115 through the contact hole is patterned, and the part on the reflective part of the pixel area is reserved, so as to form the reflective electrode 117a of the reflective part of the pixel area. In addition, an insulating layer 119 is formed on the entire surface of the substrate.

As shown in FIG. 17C, a part of the insulating layer 119 is removed to form a contact hole leading to the reflective electrode 117a. Next, a transparent conductive layer is formed on the insulating layer 119, wherein the transparent conductive layer is electrically connected to the reflective electrode 117a through the contact hole. Thereafter, the transparent conductive layer is selectively removed, leaving a portion on the transmissive portion of the pixel area, thereby forming the transparent electrode 117b. Subsequently, a polyimide resin having thermal resistance and a strong affinity for liquid crystals is printed on the substrate, and dried to form polyimide, thereby forming the first alignment layer 150 .

As shown in FIG. 17D , the first alignment layer 150 is ground by a cylindrical roller 170 on which a nylon or rayon grinding cloth 171 is attached to form an alignment direction in the first polarization direction. As shown in FIG. 17E , an ion beam emitter 190 or a light irradiator 200 is used to align the alignment direction of the first alignment layer 150 polished by the polishing cloth 171 . The ion beam may be irradiated on the entire surface of the first alignment layer 150, or after the first alignment layer 150 is masked, the rest of the first alignment layer 150 except the stepped portion between the transmissive part and the reflective part may be irradiated. part. The ion beam or light is irradiated in the same direction as the milling direction.

As described in the first embodiment of the present invention, plasma irradiation may be used. In the case of irradiation with light, an alignment layer is deposited, and it is irradiated with partially polarized light, linearly polarized light or non-polarized light under the same conditions as in the first embodiment of the present invention. In this case, a grinding process may be employed after ion irradiation, light irradiation, or plasma irradiation. In the fifth embodiment of the present invention, ion beams or light are irradiated under the same conditions as in the first embodiment of the present invention. Then, the same steps as in the first embodiment of the present invention are performed. Thus, for a transflective LCD device, light leakage due to inconsistency in alignment of liquid crystals caused by grinding defects and light leakage at the stepped portion of the transmissive part and the reflective part can be avoided, thereby obtaining high contrast.

18A to 18D are cross-sectional views showing a manufacturing process of a VA mode LCD device according to a sixth embodiment of the present invention.

As shown in FIG. 18A, a low-resistance metal layer with a specific low resistance is formed on the lower substrate 111 to prevent signal delay, and then it is patterned by a photolithography process to form gate lines (not shown) and slave gate lines. The gate 112a of the bifurcated thin film transistor. The low-resistance metal layer can be formed with copper (Cu), aluminum (Al), aluminum neodymium (AlNd), molybdenum (Mo), chromium (Cr), titanium (Ti), tantalum (Ta), or tungsten-molybdenum alloy (MoW) . Furthermore, an inorganic insulating layer made of silicon nitride (SiNx) or silicon oxide (SiOx) is formed on the entire surface of the lower substrate 111 including the gate electrode 112a by PECVD (Plasma Enhanced Chemical Vapor Deposition), thereby forming the gate electrode 112a. Pole insulating layer 113. An amorphous silicon layer is formed on the gate insulating layer 113 and selectively removed to form an island-shaped semiconductor layer 114 on the gate insulating layer 113 on the gate 112a. In addition, the ohmic contact layer can be patterned by implanting impurity ions into the amorphous silicon layer. A metal layer of Cr, Cu, Al, Mo, Ti, Ta, MoW or AlNd is formed on the entire surface of the gate insulating layer 113, and it is patterned by photolithography, and the data line 115 and the source/source electrode are simultaneously formed. Drain 115a/115b. The data line 115 and the gate line vertically define a pixel area, and the source/drain 115a/115b are formed on both sides of the semiconductor layer 114 . Thus, a passivation layer 116 is formed on the entire surface of the substrate including the data line 115 .

As shown in FIG. 18B , the portion of the passivation layer 116 corresponding to the drain 115 b is removed to form a contact hole. Next, a transparent conductive layer is formed on the entire surface of the substrate, and the transparent conductive layer is electrically connected to the drain electrode 115b through the contact hole. Next, the transparent conductive layer is selectively removed, and the remaining part forms the pixel electrode 117 in the pixel area. Meanwhile, a slit 118 is formed by removing a predetermined portion of the pixel electrode. In addition, a dielectric grid of organic insulating material is formed on the same layer as the passivation layer 116 . Also, a dielectric lattice made of an organic insulating material is formed on the same layer as the passivation layer 116 . Alternatively, a dielectric lattice may be formed on the common electrode of the opposite substrate, or a slit may be formed on a predetermined portion of the common electrode of the opposite substrate. Then, polyimide resin having thermal resistance and strong affinity to liquid crystal is formed on the entire surface of the substrate including the pixel electrode 117 . Then, the printed polyimide resin is dried into imide, thereby forming the first alignment layer 150 .

As shown in FIG. 18C , the first alignment layer 150 is ground by a cylindrical roller 170 on which a nylon or rayon grinding cloth 171 is attached. The first alignment layer is ground to have a first polarization direction. As shown in FIG. 18D , the ion beam or light is irradiated on the first alignment layer 150 polished by the polishing cloth 171 , and the alignment direction is aligned by using the ion beam emitter 190 or the light irradiator 200 . Ion beams or light can be irradiated on the entire surface of the first alignment layer 150, or after the first alignment layer 150 is masked, irradiated except the stepped portion of the crossing portion of the gate line and the data line, the stepped portion of the thin film transistor, and The rest of the first alignment layer 150 of the stepped portion of the slit 118 . The ion beam or light is irradiated in the same direction as the milling direction.

As in the first embodiment of the present invention, plasma irradiation may be used. In the case of using light, the alignment layer is deposited and irradiated with partially polarized light, linearly polarized light or non-polarized light under the same conditions as in the first embodiment of the present invention. In this case, after ion beam irradiation, light irradiation, or plasma irradiation, a grinding process is performed. In the sixth embodiment of the present invention, the irradiation conditions of ion beams or light are the same as those of the first embodiment of the present invention. The remaining steps are the same as the first embodiment of the present invention. However, a protrusion may be formed on the common electrode.

Thereby, in the VD mode LCD device based on the present invention, can avoid the light leakage that produces because of the inconsistency of liquid crystal alignment direction that the grinding defect causes, the light leakage that produces in the step portion that gate line crosses with data line and thin film transistor and narrow High contrast can be obtained by eliminating the light leakage generated by the stepped part of the slit.

FIG. 19 shows photographs of light leakage in an LCD device based on the present invention. In FIG. 19, light leakage did not occur in the LCD device fabricated through the additional alignment process.

As described above, the LCD device and its manufacturing method according to the present invention have the following advantages.

When manufacturing the LCD device based on the present invention, the alignment process is combined with the grinding process. Thus, it is possible to achieve a uniform orientation direction over the entire substrate by resolving polishing defects due to unevenness of the polishing cloth. In addition, liquid crystals are uniformly controlled by consistent alignment directions, preventing light leakage due to grinding defects.

In addition, it is possible to obtain a uniform orientation direction at the stepped portion by ion beam irradiation, light irradiation, or plasma irradiation, thereby preventing grinding defects caused by the grinding roll not being in contact with the stepped portion during the grinding process. At the same time, the liquid crystal molecules are controlled by an alignment process at the stepped part of the alignment layer, thereby preventing light leakage at the stepped part. By preventing light leakage, the LCD device can reduce the black level and achieve higher contrast ratio, thereby improving the image display quality.

When the lapping process generates alignment defects at the stepped portion, a stepped portion is generated on the column spacer. If the alignment defect area is not covered by the black matrix layer, this alignment defect area will generate light leakage. In addition, since the embodiment of the present invention uses both the grinding process and the alignment process, even if the stepped portion is generated in the column spacer portion, grinding defects and light leakage in the stepped portion not covered by the black matrix can be prevented.

Although the embodiments of the present invention have been explained above with reference to the accompanying drawings, it should be said that those skilled in the art can understand that the present invention is not limited to these embodiments, and various modifications and modifications can also be made to it without departing from the principles of the present invention. change. Accordingly, the scope of the present invention should be determined only by the claims and their equivalents.

Claims (36)

1. A method for manufacturing a liquid crystal display device, comprising: preparing first and second substrates; forming thin film transistors on the first substrate; forming a first alignment layer on a first substrate including thin film transistors; performing a grinding and alignment process on the first alignment layer to provide a consistent alignment direction; and forming a liquid crystal layer between the first and second substrates, wherein the alignment process is irradiating light on the first alignment layer, and wherein the light includes one of partially polarized light and linearly polarized light, and Wherein the light is polarized perpendicular to the grinding direction of the grinding process. 2. The method according to claim 1, wherein the alignment process is performed before the grinding process is performed. 3. The method according to claim 1, wherein the alignment process is performed after the grinding process is performed. 4. The method according to claim 1, wherein an alignment process is performed on the entire surface of the first alignment layer. 5. The method according to claim 1, wherein an alignment process is performed on the remaining portion of the first alignment layer except the stepped portion using a mask. 6. The method according to claim 1, wherein the alignment direction on the entire surface of the first alignment layer is the same as the alignment direction of the alignment process. 7. The method according to claim 1, wherein the pretilt angle on the entire surface of the first alignment layer is the same as the pretilt angle in the alignment process. 8. according to the described method of claim 1, it is characterized in that, described first alignment layer is made of polyimide, polyamic acid, polyethylene cinnamate, polyazobenzene, polyethyleneimine, polyethylene Alcohol, polyamide, polyethylene, polystyrene, polystyrene naphthalimide, polyester, polyurethane or polymethyl methacrylate. 9. The method of claim 1, wherein the light has a wavelength between 200 nm and 450 nm. 10. The method of claim 1, wherein the light is irradiated perpendicular to the first substrate. 11. The method of claim 1, wherein the light is irradiated obliquely relative to the first substrate. 12. The method according to claim 1, wherein a grinding process and an alignment process are performed on the first alignment layer together. 13. The method of claim 1, further comprising: forming a second alignment layer on the second substrate; and A grinding process and an alignment process are performed on the second alignment layer. 14. The method according to claim 13, wherein the alignment direction of the first alignment layer and the alignment direction of the second alignment layer are the same process. 15. The method according to claim 13, wherein the pretilt angle of the first alignment layer is the same as the pretilt angle of the second alignment layer. 16. The method according to claim 1, wherein said forming a thin film transistor comprises: forming a gate line, a gate, a common line and a plurality of common electrodes on the first substrate; forming a gate insulating layer on the first substrate; forming a semiconductor layer on the gate insulating layer; forming data lines and source/drain electrodes on the first substrate; forming a passivation layer on the first substrate; and A plurality of pixel electrodes are formed on the passivation layer. 17. The method according to claim 1, wherein said forming a thin film transistor comprises: forming a gate line, a gate, a common line and a plurality of common electrodes on the first substrate; forming a gate insulating layer on the first substrate; forming a semiconductor layer on the gate insulating layer; forming data lines, source/drain electrodes, and a plurality of pixel electrodes on the first substrate; and A passivation layer is formed on the first substrate. 18. The method according to claim 1, wherein said forming a thin film transistor comprises: forming gate lines and gates on the first substrate; forming a gate insulating layer on the first substrate; forming a semiconductor layer on the gate insulating layer; forming data lines and source/drain electrodes on the first substrate; forming a passivation layer on the first substrate; and A plurality of pixel electrodes and a plurality of common electrodes are formed on the passivation layer. 19. The method according to claim 18, wherein the pixel electrode and the common electrode are formed of a transparent conductive material. 20. The method of claim 19, wherein the transparent conductive material comprises one of steel tin oxide and indium zinc oxide. 21. The method according to claim 1, wherein said forming a thin film transistor comprises: forming a gate line, a gate, a common line and a plurality of common electrodes on the first substrate; sequentially forming a gate insulating layer, a semiconductor layer and a metal layer on the first substrate; Forming data lines and source/drain electrodes by selectively removing metal and semiconductor layers using a screen mask; sequentially forming a passivation layer and a photoresist on the first substrate; removing the passivation layer over the drain using an exposure and development process; and A plurality of pixel electrodes are formed by forming a conductive layer on the first substrate, and the photoresist and the conductive layer are removed by using a lifting method. 22. The method of claim 21, wherein the conductive layer is formed of one of a transparent conductive layer and a metal layer. 23. The method according to claim 1, wherein said forming a thin film transistor comprises: forming gate lines and gates on the first substrate; forming a gate insulating layer and a semiconductor layer on the first substrate; forming data lines and source/drain electrodes on the first substrate; forming a passivation layer on the first substrate; and A plurality of pixel electrodes are formed on the passivation layer, and the pixel electrodes are connected to the drain. 24. The method of claim 23, further comprising forming a slit in the pixel electrode. 25. The method of claim 23, further comprising forming a common electrode on the second substrate and forming a slit in the common electrode. 26. The method of claim 23, further comprising forming a common electrode on the second substrate and forming a dielectric lattice in the common electrode. 27. The method of claim 23, further comprising forming a dielectric lattice on at least one of the first and second substrates. 28. The method of claim 27, wherein the dielectric grid is formed in the form of a passivation layer. 29. The method of claim 23, further comprising forming a color filter layer on the first substrate. 30. The method of claim 23, further comprising forming a color filter layer on the passivation layer. 31. The method according to claim 1, wherein said forming a thin film transistor comprises: forming gate lines and gates on the first substrate; forming a gate insulating layer on the first substrate; forming a semiconductor layer on the gate insulating layer; forming data lines and source/drain electrodes on the first substrate; forming a passivation layer on the first substrate; forming a reflective electrode on the passivation layer of the reflective portion of the pixel region, the reflective electrode being connected to the drain; and A transparent electrode is formed in the transmissive part of the pixel area, and the transparent electrode is connected to the reflective electrode. 32. A method of manufacturing a liquid crystal display device, comprising: preparing first and second substrates; forming thin film transistors on the first substrate; forming a first alignment layer on the first substrate; performing a grinding process and an alignment process on the first alignment layer to provide a consistent alignment direction; forming a second alignment layer on the second substrate; forming a liquid crystal layer between the first and second substrates, wherein the alignment process is irradiating light on the first alignment layer, and wherein the light includes one of partially polarized light and linearly polarized light, and Wherein the light is polarized perpendicular to the grinding direction of the grinding process. 33. The method of claim 32, wherein an alignment process is performed using a mask on the remaining portion of the first alignment layer except the stepped portion. 34. The method according to claim 32, wherein the alignment direction of the entire surface of the first alignment layer is the same as that of the alignment process. 35. The method according to claim 32, wherein the pretilt angle of the entire surface of the first alignment layer is the same as the pretilt angle of the alignment process. 36. according to the described method of claim 32, it is characterized in that, described first and second alignment layer are made of polyimide, polyamic acid, polyethylene cinnamate, polyazobenzene, polyethylene imine, Formed from one of polyvinyl alcohol, polyamide, polyethylene, polystyrene, polystyrene naphthalimide, polyester, polyurethane, or polymethylmethacrylate.

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