Infra-frame prediction device and Forecasting Methodology based on pixel flowing
Technical field
The present invention relates to digital TV image handle in system (SOC, System on Chip) on the encoding and decoding technique of digital video and the core, especially relate in a kind of video decoding chip infra-frame prediction device and Forecasting Methodology based on pixel flowing.
Background technology
Video coding technique is mainly attempted to solve with few information bit of trying one's best and is represented one section video, and recovers or roughly recover original image by these information potential energies fully.In order to pursue higher compression efficiency, Predicting Technique has obtained development fast.H.264 among (the up-to-date video encoding and decoding standard of International Telecommunications Union) and the AVS (Chinese audio/video encoding/decoding national standard), all introduced the infra-frame prediction on the multimodal spatial domain at up-to-date video standard.Infra-frame prediction utilizes the most contiguous decoded pixel value in the left side and top of current block to predict all pixels of current block.
See also Fig. 1,9 of infra-frame prediction kinds of predictive mode schematic diagrames on the spatial domain.Be different from the infra-frame prediction on transform domain that adopts in motion picture expert group standard MPEG-4 and the former video encoding standard, H.264 standard takes the lead in adopting the infra-frame prediction on the original image spatial domain, utilize the value of decoded pixel that is close to current block, predict the pixel value of current block.The infra-frame prediction of this mode can utilize the direction continuity of texture in the image better, comes image block is carried out adaptive prediction by different directions.This standard has defined 9 kinds of predictive modes altogether, uses 8 kinds of prediction direction and a kind of direct current DC respectively, direct current) pattern, the DC pattern adopts the mean value of edge pixel as the predicted value of being had a few.
Chromatic component has adopted 4 kinds of predictive modes, is respectively DC, level, vertical and plane prediction mode, as shown in Figure 2.Vertical mode is to predict with V.Horizontal pattern is to advance the survey pattern with H, as shown in Figure 2.Vertical mode is to predict with V.Horizontal pattern is to predict with H.Direct current DC pattern is to predict with the mean value of all H and V.Plane mode is to predict that with the linear interpolation of H and V decision this pattern is suitable for the piece of smooth change in the image.
Owing to adopted multiple predictive mode, these pattern informations must allow decoder obtain, so that be correctly decoded.And these predictive modes of encoding also need certain code check.View data is analyzed, can be found that the trend of texture has certain continuity, this makes can also predict between the predictive mode between the adjacent block.The predictive mode prediction is seen shown in Figure 3.When A, B exist, when promptly current block C was not in image boundary, the smaller value of predictive mode that uses A, two modules of B was as predicted value, because less pattern has the higher probability of choosing.If the mode value that code stream analyzing goes out is less than the predictive mode value, then realistic model equals the code stream analyzing value, adds 1 otherwise realistic model equals the code stream analyzing value.Have a mark to show whether use the code stream analyzing value in the code stream in addition, if this is labeled as 0 then encoding stream analytic value not in the code stream, realistic model equals predictive mode.In addition, the colourity schema category is less, does not carry out model prediction.
For satisfying the demand of HD image real-time decoding, special-purpose very lagre scale integrated circuit (VLSIC) is used to realize decoder chip.The entire decoder chip is divided into a lot of modules, and as other modules, the design of intra-framed prediction module also will be pursued area, speed, the optimum balance of power consumption.What prior art adopted is to handle with behavior unit, the parallel infra-frame prediction that carries out of 8 pixels of delegation, and 8 times walk abreast though improved the throughput of system, makes the processing unit number improve 8 times, makes capable process chip area big.The needs of infra-frame prediction can not be really satisfied in the device design of the infra-frame prediction of prior art.
Another kind of way is that serial is according to pixels carried out, finish the prediction of a pixel, carry out the prediction of next pixel again, all like this pixels can shared processing unit, can reduce chip area greatly, but it is slower that the problem that serial process is brought is a processing speed, could flow out a pixel data with a plurality of clock cycle usually, be difficult to reach video particularly the high definition video picture decoding to the requirement of real-time.
Summary of the invention
In order to overcome above-mentioned the deficiencies in the prior art, the purpose of this invention is to provide a kind of infra-frame prediction device and Forecasting Methodology, to satisfy the needs of infra-frame prediction based on pixel flowing.
Another object of the present invention provides a kind of infra-frame prediction device and Forecasting Methodology based on pixel flowing, makes intra-framed prediction module reach the better balance of area, speed, power consumption.
In order to finish the foregoing invention task, the overall technological scheme that the present invention adopts is: a kind of infra-frame prediction device based on pixel flowing comprises:
The intra prediction mode derivation module, it is used to derive actual intra prediction mode, the direction and the pattern of decision infra-frame prediction, this module comprises the minimum value device, comparator, adder, data multiplexer, the minimum value device connects line buffer and left mode memory, its output connects an end of data multiplexer, comparator connects fifo queue and minimum value device output, the output of comparator connects an end of adder, the other end of adder links to each other with fifo queue, and the output of data multiplexer connects the reference pixel acquisition cuicuit of predictive mode line buffer and infra-frame prediction pixel generation module;
The predict pixel generation module, this module is used for the intra prediction mode travel direction prediction according to adjacent pixel values and pattern derivation module input on every side, obtain the interior infra-frame prediction pixel value of being had a few of macro block, it comprises reference pixel acquisition cuicuit, the Pixel-level three class pipeline circuit that connects intra prediction mode derivation module line buffer, the three class pipeline circuit comprises address calculating circuit, filter circuit and prediction and refresh circuit, and prediction links to each other with reconstruction and update module with refresh circuit;
Rebuild and update module, this module is used to generate actual decoding and rebuilding value, and these reconstructed value are write the input block of downstream module, two inputs of its adder connect the output of pixel generation module intra prediction value output and inverse transform block circuit predicts residual values respectively, and the reconstructed value output of adder connects the line buffer of intra prediction mode derivation module.
A line buffer is arranged in the described intra prediction mode derivation module, to deposit the frame mode information of a last whole image line, reference when being used for the pattern derivation.
When drawing high, the macro block commencing signal that described intra prediction mode derivation module provides at the pixel generation module starts working.
Described intra prediction mode derivation module is finished predictive mode and is derived in three continuous clock cycle, first cycle is finished reading of reference model, second period is finished the calculating of predictive mode, and the 3rd cycle deposits the mode decoding value in the line buffer in.
A kind of Forecasting Methodology of the infra-frame prediction device based on pixel flowing comprises the steps:
The pattern information that step 1, intra prediction mode derivation module are come out by code stream analyzing and derive actual intra prediction mode according to the prediction mode information of pattern on every side, and the result passed to the pixel generation module, with the direction and the pattern of decision infra-frame prediction;
Step 2, predict pixel generation module according to around the intra prediction mode travel direction prediction of adjacent pixel values and the input of pattern derivation module, obtain the infra-frame prediction pixel value of being had a few in the macro block, and give reconstruction circuit and rebuild and upgrade;
Step 3, reconstruction and update module are with the intra prediction value and the prediction residual value addition of being exported by the inverse transform block circuit of the output of pixel generation module, obtain actual decoding and rebuilding value, then these reconstructed value are stored in the row buffering, so that the pixel generative circuit uses later on, and these reconstructed value are spliced into delegation, write the input block of downstream module.
Above-mentioned described step 1 further comprises the steps:
Step 11, get the mode decoding value in the predictive mode line buffer and the smaller value of left mode decode value;
Step 12, smaller value is compared by comparator with the mode value of taking out from fifo queue;
Step 13, with the comparative result input summer;
Step 14, judge that the mode value take out is whether more than or equal to the output valve of minimum value device from formation, if then the mode value that will take out from formation adds 1 as real output value, otherwise the output valve of output minimum value device, and by data multiplexer with in the output valve writing line buffer.
Above-mentioned described step 2 further comprises the steps:
Step 21, before the flowing water of each macro block begins, from the pixel column buffer of rebuilding module circuit, take out needed prediction reference point, be stored in the internal register;
Step 22, judging whether reference pixel obtains and finish, is then to send a signal to a three class pipeline to carry out infra-frame prediction;
The first order of step 23, three class pipeline utilizes look-up table to obtain the position of the left side reference pixel and the top reference pixel of needs according to mode value and current pixel coordinate, filtering is carried out in the second level, obtain the pixel reference value from the register of corresponding address, obtain filtered predicted value through adder and shift unit, the third level produces a control signal according to predictive mode, by data multiplexer of this control signal control filter value and original value are screened, afterwards the predicted value that obtains is latched, and be written out in the rebuilding module circuit.
In the address computation in the described step 23, be used to predict that the reference point locations of some pixels is two, one is used for reference position, mark top, another reference position, mark left side, and these two positions are calculated according to predictive mode and the position calculation of current future position gets.
Three class pipeline in the described step 3 takes out needed prediction reference point from the pixel column buffer of rebuilding module circuit be to finish with 5 clock cycle, period 1 waits for that lastblock flowing water finishes, read the top pixel second round, the 3rd cycle read upper right pixel, period 4 is latched the top pixel, and the 5th cycle latchs upper right pixel and start streamline.
The present invention adopts Pixel-level flowing water to carry out infra-frame prediction, has tangible advantage and good effect.Satisfied needs, but also left enough allowances for high definition TV decoding real-time.Simultaneously, owing to adopt the Pixel-level pipeline organization, the processing of same pixel is dispersed in three ranks to be carried out in proper order, and the treatment step in succession of successive pixels carries out at one time, under the situation that only increases a little register, but improved throughput greatly based on the intra-frame prediction method of pixel.Than parallel processing way, because only adopted a cover arithmetic unit, so significantly reduced taking of chip area based on row.
Description of drawings
Fig. 1 is 9 of infra-frame prediction kinds of infra-frame prediction luminance patterns schematic diagrames on the spatial domain in the prior art;
Fig. 2 is 4 kinds of predictive mode schematic diagrames of chromatic component in the prior art;
Fig. 3 is intra-frame prediction method figure in the prior art;
Fig. 4 is the top-level module structural representation of infra-frame prediction device of the present invention;
Fig. 5 is an intra prediction mode derivation module structural representation of the present invention;
Fig. 6 is an infra-frame prediction pixel generation module structural representation of the present invention;
Fig. 7 is the predict pixel streamline schematic diagram of infra-frame prediction device of the present invention.
Embodiment
The present invention is further detailed explanation below in conjunction with the drawings and specific embodiments.
Consult Fig. 4, the top-level module structural representation of infra-frame prediction device of the present invention, infra-frame prediction device of the present invention comprise pattern derivation, pixel generation and reconstruct and renewal three big modules.
Fig. 5 is an intra prediction mode derivation module structural representation of the present invention.The intra prediction mode derivation module is derived actual intra prediction mode, the direction and the pattern of decision infra-frame prediction, this module comprises the minimum value device, comparator, adder, data multiplexer, the minimum value device connects line buffer and left mode memory, its output connects an end of data multiplexer, comparator connects fifo queue and minimum value device output, the output of comparator connects an end of adder, the other end of adder links to each other with fifo queue, and the output of data multiplexer connects the reference pixel acquisition cuicuit of predictive mode line buffer and infra-frame prediction pixel generation module.The pattern information that the derived circuit of intra prediction mode derivation module comes out by code stream analyzing and according to the prediction mode information of pattern on every side, derive actual intra prediction mode, and the result passed to pixel generative circuit module, with the direction and the pattern of decision infra-frame prediction.Comprise a line buffer in the pattern derivation module, the reference when being used for the pattern derivation with the frame mode information of depositing a last whole image line.
The working method of pattern derivation module is:
At first, wait for that the pixel generation module provides macro block (macro block) commencing signal, starts working when this signal is drawn high.Then, 3 states start, and finish predictive mode and derive in three continuous clock cycle.First cycle is finished reading of reference model, and second period is finished the calculating of predictive mode, and the 3rd cycle of the circuit of calculating deposits the mode decoding value in row buffering.After the macro block commencing signal is drawn high, calculate the mode value of all pieces in the macro block continuously, finish up to macro block, wait for next macro block commencing signal.
Mode computation process shown in Figure 5 is: the smaller value of going up edge mode and left mode is compared by the pattern of comparator and formation taking-up, and it is input summer as a result.If the pattern of taking out in the formation is more than or equal to the output of minimum value device, then the pattern that formation is taken out adds 1 as real output value.The output prime has a data multiplexer, and being selected by coded markings is to adopt predicted value output, or the output of formation taking-up value.The result who calculates upgrades line buffer.
As shown in Figure 6, the predict pixel generation module comprises reference pixel acquisition cuicuit, the Pixel-level three class pipeline circuit that connects intra prediction mode derivation module line buffer, the three class pipeline circuit comprises address calculating circuit, filter circuit and prediction and refresh circuit, and prediction links to each other with reconstruction and update module with refresh circuit.The predict pixel generation module according to around the intra prediction mode travel direction prediction of adjacent pixel values and pattern derivation module input, obtain the infra-frame prediction pixel value of being had a few in the piece, and give rebuilding module and rebuild and upgrade.Streamline is in case operation is got up, and each clock cycle is exported a predicted value, and all pixels are all predicted and finished in a piece.
In order to save the time loss of memory access, before the flowing water of each piece began, at first the reference pixel acquisition cuicuit took out needed prediction reference point from the pixel column buffer of reconstruction and update module, is stored in the internal register.This process is finished the reading of data by state exchange in 5 cycles in succession by the state machine of one 5 states.When desired data all has been equipped with, send a signal to a three class pipeline, carry out infra-frame prediction.
In Fig. 7, the forecasting process of pixel is undertaken by a three class pipeline.The first order is carried out address computation, according to mode value and current pixel coordinate, utilize look-up table to obtain the left side reference pixel of needs and the position of top reference pixel, filtering is carried out in the second level, obtain the pixel reference value from the register of corresponding address, obtain filtered predicted value through adder and shift unit.The third level produces a control signal according to predictive mode, by data multiplexer of this control signal control filter value and original value is screened, and afterwards the predicted value that obtains is latched, and is written out in the rebuilding module circuit.
After streamline starts, the address computation of first pixel was finished in first clock cycle, enter the second level then, calculate the filter value of first pixel at second period, meanwhile promptly at second period, second pixel enters streamline, and its address computation is also finished in the first order of streamline.From the time, the forecasting process of a pixel needs three cycles, by three grades of streamline, exports at last respectively; From the space, synchronization, three grades of different phases of handling the infra-frame prediction of three successive pixels at the same time of streamline.Use the register holds median between the different ranks.
Again as shown in Figure 6, two inputs of reconstruction and update module adder connect the output of pixel generation module intra prediction value output and inverse transform block circuit predicts residual values respectively, and the reconstructed value output of adder connects the line buffer of intra prediction mode derivation module.Reconstruction and update module are passed through the adder addition with the intra prediction value of pixel generation module output and by inverse transform circuit prediction of output residual values, obtain actual decoding and rebuilding value.On the one hand these reconstructed value are stored in the line buffer, so that the pixel generation module uses later on; On the other hand, these reconstructed value are spliced into delegation, and write in the input block of downstream module.This will rebuild and infra-frame prediction is placed on the mechanism of a module, the exchanging visit that can save intermodule.
Intra-frame prediction method based on the infra-frame prediction device of pixel flowing mainly contains following steps:
The pattern information that step 1, intra prediction mode derivation module are come out by code stream analyzing and derive actual intra prediction mode according to the prediction mode information of pattern on every side, and the result passed to the pixel generation module, with the direction and the pattern of decision infra-frame prediction;
Step 2, predict pixel generation module according to around the intra prediction mode travel direction prediction of adjacent pixel values and the input of pattern derivation module, obtain the infra-frame prediction pixel value of being had a few in the macro block, and give rebuilding module and rebuild and upgrade;
Step 3, reconstruction and update module are with the intra prediction value and the prediction residual value addition of being exported by the inverse transform block circuit of the output of pixel generation module, obtain actual decoding and rebuilding value, then these reconstructed value are stored in the row buffering, so that the pixel generative circuit uses later on, and these reconstructed value are spliced into delegation, write in the input block of downstream module.
The infra-frame prediction of embodiment 1:AVS standard.The AVS standard adopts the block size of 8x8, and intra prediction mode brightness has 5 kinds, is respectively level, and is vertical, direct current, tiltedly diagonal angle, lower-left, tiltedly lower-right diagonal position; Colourity has 4 kinds, direct current, and level, vertical, the plane interpolation.For high definition TV such as resolution is the requirement of 1920x1088, and row buffering bit wide 64 bits can be deposited the data of a macro-block line, the degree of depth 480, and its brightness is 240, colourity is 240.Calculating a 8x8 piece needs pipeline cycle 64+2=66, calculates 432 cycles of clock cycle of whole macro block, has satisfied the needs for high definition TV decoding real-time, but also has left enough allowances.Owing to adopt the Pixel-level pipeline organization, significantly reduced taking of chip area simultaneously.
The infra-frame prediction of embodiment 2:H.264 standard.H.264 the infra-frame prediction of standard and AVS standard class seemingly, but it uses the block size of 4x4, intra prediction mode brightness has 9 kinds, is respectively level, and is vertical, direct current, oblique diagonal angle, lower-left, oblique lower-right diagonal position, level on the upper side, level is vertically taken back on the lower side, vertically takes over; Colourity also is 4 kinds, direct current, and level, vertical, the plane interpolation.Though predictive mode increases, utilize framework among the present invention still can realize the module of its infra-frame prediction efficiently.In the decoding real-time, area of chip and cost have been reduced.
It should be noted last that: above embodiment is the unrestricted technical scheme of the present invention in order to explanation only, although the present invention is had been described in detail with reference to the foregoing description, those of ordinary skill in the art is to be understood that: still can make amendment or be equal to replacement the present invention, and not breaking away from any modification or partial replacement of the spirit and scope of the present invention, it all should be encompassed in the middle of the claim scope of the present invention.