CN1588554A - USB large volume storage device - Google Patents

Abstract

The invention is a USB large-capacity storage device, which is composed of hardware and control software. The hardware adopts general-purpose components, which are composed of USB interface devices, cheap high-speed PIC-compatible MCU single-chip microcomputers, and large-capacity storage chips. The disadvantage of this scheme is that the connection is slightly more complicated, and the advantage is that there are many possible combinations and a large choice. The present invention provides a detailed software solution, utilizes the features of large-capacity storage chip block erasing and page copying, and proposes a characteristic "backup-direct writing-recovery" writing process, which ensures that USB mass storage devices have The characteristics of long life, always correctness and strong compatibility make the U disk manufactured based on the invention have the advantages of easy upgrading and reliable performance.

Description

A USB mass storage device

technical field

The invention belongs to the technical field of computer storage devices, and in particular relates to a USB large-capacity storage device (U disk for short).

Background technique

As an auxiliary tool for computers, floppy disks have been gradually replaced by U disks due to their shortcomings such as small capacity, slow speed, and short life. The biggest feature of U disk different from floppy disk is that there is no mechanical part, so it can achieve fast speed, large capacity, long service life, and safe and reliable data.

The U disk is generally composed of a dedicated control chip and a large-capacity storage chip. The advantage of this solution is that manufacturers can directly produce and process according to the drawings provided by the dedicated control chip supplier. However, some manufacturers’ U disks only support their own formatting operations; some manufacturers’ U disks do not fully support WINDOWS98/2X’s FAT, FAT32, NTFS formatting operations; and some manufacturers’ U disk data are often destroyed for no reason; In addition, there is a problem that the lifespan is not long enough. The reason is that there is a problem with the control writing software.

Contents of the invention

The object of the present invention is to provide a USB storage device with large capacity, long service life and capable of supporting multiple formatting operations.

The USB large-capacity storage device designed by the present invention is composed of hardware and control software for reading and writing. The hardware (circuit) is formed by connecting a USB interface with a power generator circuit, an oscillation circuit, a USB communication circuit, a single-chip microcomputer control circuit and a large-capacity memory interface circuit through the circuit. The block diagram of the circuit structure is shown in Figure 6. Among them, the USB interface and the power generator circuit provide a USB interface with the USB communication circuit, and derive a power supply of about 3.3 volts from the USB power supply for the rest of the circuit to work; the oscillation circuit drives the USB communication circuit to work; the USB communication circuit is responsible for sending and receiving USB data packets The single-chip microcomputer control circuit is responsible for allowing the computer to identify itself as a large-capacity storage device through the USB communication circuit, and intelligently controls the reading and writing of the large-capacity storage interface circuit; Under the action of the single-chip microcomputer control circuit, the block data is transmitted to the computer via the USB communication circuit. In the design scheme of the USB large-capacity storage device designed by the present invention, there is no special control chip adopted by the U disk, but a cheap chip commonly used in the industry, which is easier to upgrade and more reliable in performance.

In the above-mentioned USB storage device, the power generation circuit is composed of 3 diodes connected in series, and a 3.4-volt power supply is obtained from a 5-volt USB power supply; the single-chip microcomputer adopts a high-speed PIC compatible MCU single-chip microcomputer MDT10P20, the USB interface device adopts a PDIUSB12D chip, and the large-capacity storage adopts FLASH chip, the three form a USB mass storage component.

In the present invention, the control software is composed of two parts: a USB device identification part and a large-capacity storage read-write part. Among them, the USB device identification part is completed by the control endpoint 0, which conforms to the USB specification 1.1; the mass storage read and write part is completed by the endpoint 2, which complies with the USB MASS STORAGE CLASS BULK-ONLY TRANSPORT specification. In addition, it must comply with the usage specifications of USB interface devices and mass storage chips.

Description of drawings

Figure 1 shows the USB interface and power generator circuit.

Figure 2 is the USB communication circuit.

Figure 3 shows the microcontroller control circuit.

Figure 4 is a large-capacity memory interface circuit.

Figure 5 is

FIG. 6 is a block diagram of the circuit structure of the storage device.

FIG. 7 is a block diagram of the control software of the storage device.

Numbers in the figure: 1 is a USB interface and power generator circuit, 2 is a USB communication circuit, 3 is an oscillation circuit, 4 is a single-chip microcomputer control circuit, 5 is a large-capacity memory interface circuit.

Detailed ways

The present invention will be described in detail below by means of embodiments and accompanying drawings.

The USB interface and power generator circuit shown in Figure 1 provides a USB interface with the USB communication circuit, and derives a power supply of about 3.3 volts from the USB power supply for the rest of the circuits to work. J1 is a USB socket, the 1st pin is the USB ground, the 2nd pin is the USB data line DP, the 3rd pin is the USB data line DN, and the 4th pin is the USB 5V power line. D2, D3 are two silicon diodes 1N4007, D1 is a germanium diode AK15. Three diodes are connected in series, as shown in the figure, connected between pin 4 of J1 and signal V3.3. The voltage drop of the three diodes is about 0.65*2+0.3=1.6 volts. Starting from the 4-pin 5-volt power supply, V3.3 is about 3.4 volts, which is used to drive the rest of the circuit. We choose the rest of the components so that they operate between 2.7 volts and 3.6 volts. The function of capacitor C3 is to stabilize the V3.3 power supply signal.

The USB communication circuit shown in Figure 2 is responsible for sending and receiving USB data packets. Using USB interface device PDIUSB12D, the chip complies with USB1.1 specification, has 12Mbit/s full-speed USB communication function, and has 8-bit parallel interface, which is convenient for single-chip control. Working mode 0 of the chip provides endpoint 0 and endpoint 2, endpoint 0 has input/output function, the maximum data packet length is 16 bytes, used for LSB control transmission; endpoint 2 has input/output function, the maximum data packet length is 64 bytes, with dual 64-byte data buffers, suitable for full-speed block transfers. Its pin connections are as follows:

① 5 and 24 pins are the power supply pins, 5 pins are grounded, and 24 pins are connected to the V3.3 signal;

② Pins 22 and 23 are its oscillation pins, which are connected to both ends of the ceramic oscillator Y1 with built-in stable capacitors as required. The frequency of Y1 is 6MHz, as shown in Figure 5;

③ Pins 25 and 26 are the USB signal DN and DP pins of the chip respectively, and are connected to pins 3 and 2 of the USB socket through 18Ω resistors R3 and R18. The function of R3 and R18 is to match the impedance of the differential circuit;

④ 1, 2, 3, 4, 6, 7, 8, 9 are its parallel interfaces, which are connected to the 8-bit data bus AD[0..7]. The capacity storage FLASH chip can exchange data with the chip;

⑤ Pin 10 is the address latch input signal, which is grounded if not used; pin 14 is the output signal of the interrupt flag for data transmission and reception, which is not used, so it is suspended; pin 12 is the input signal to make the chip enter the suspend state, open drain, and the chip is never used in this design. Enter the suspended state, so it can be suspended; pins 17, 18, and 19 are the DMA request output, acknowledge input, and interrupt input signals of the chip. This design does not use the DMA function, so they are respectively suspended and connected to the V3.3 signal; Vout33 It is the 3.3 volt power output pin of the chip. If not used, it can be left floating or connected to the V3.3 signal;

⑥Pin 11 is the chip selection signal, which is low and effective. Since the bus is shared between the USB interface chip, MCU single-chip microcomputer, and large-capacity storage FLASH chip, when the latter two exchange data and occupy the bus, the USB interface chip needs to give up bus control. , so the pin is connected to the signal nCS to be controlled by the MCU microcontroller;

⑦The 28th pin is the address bit input signal. When the signal on this pin is 0, it means that the input is data, otherwise it is a command command, so it is connected to the CLE signal and controlled by the single-chip microcomputer;

⑧Pin 13 is a programmable oscillating signal output pin, the frequency is 48MHz/(n+1), where n is a positive number between 1 and 11, and it is 11 at the beginning. This signal is connected to Clk to drive the MCU microcontroller;

⑨Pins 15 and 16 are read and write control input pins respectively, low effective, connected to nRD and nWR signals, and controlled by MCU single-chip microcomputer;

⑩Pin 21 is the USB connection status indicator light, which is low effective and can absorb 8mA current, so it is connected to the light-emitting diode LP1 through the resistor R4, and the other end of the diode is connected to the V3.3 signal. The function of R4 is to control the magnitude of the current. Note that the direction of the diode cannot be reversed;

The single-chip microcomputer control circuit shown in Figure 3 is responsible for allowing the computer to identify itself as a mass storage device through the USB communication circuit, and intelligently controls the reading and writing of the mass storage interface circuit. It is realized by PIC compatible MCU MCU MDT10P20, and the operating voltage is between 2.3 volts and 5 volts. Of course, you can also choose other chips, such as EM78P257. In fact, as long as it has more than 14 IO ports, a RISC microcontroller that can execute about 5M instructions per second at a working voltage of 3.3 volts can do it. The pin connection of MDT10P20 is as follows:

①The power supply pins 6 and 15 are respectively grounded and V3.3 signal;

②17 is the oscillation input pin, connected to the Clk oscillation signal from PDIUSB12D, 16 is the oscillation output pin, no need, suspended;

③5 is the reset input pin, low effective, using the internal power-on reset function of the chip, so it is connected to the V3.3 signal because the function of this pin is not used;

④ 8 IO ports from pins 7 to 14 are used as bus interfaces, connected to the bus AD[0..7]. When inputting data, these pins must be set to input status, and when outputting data/commands, they must be set to output status;

⑤Pin 18 is used to select PDIUSB12D, set it as an output state, and connect it to the signal nCS;

⑥Pin 19 is used to select a large-capacity storage FLASH chip, set it to an output state, and connect it to the signal nCE;

⑦ Pins 20 and 1 are used to control writing and reading, set to output state, and connect to nWR and nRD signals respectively;

⑧Pin 2 is used for command indication bit, set to output state, used to notify PDIUSB12D and mass storage FLASH chip when issuing commands;

⑨Pin 3 is used for the address indication bit, which is set to the output state, and is used to notify the mass storage FLASH chip when sending out the address;

⑩Pin 4 is the external pulse input port, which is connected to the operation completion/waiting signal nINT from the mass storage FLASH chip, and 1 indicates completion, which is used to speed up the completion of the memory write operation.

The large-capacity memory interface circuit shown in Figure 4 saves the block data sent by the computer via the USB communication circuit, and at the same time transmits the block data to the computer via the USB communication circuit under the action of the single-chip microcomputer control circuit. Use a large-capacity storage FLASH chip commonly used in U disks: for example, K9F1208UOC, which is a 64MByte storage chip produced by SAMSUNG, with an operating voltage of 2.7 volts to 3.6 volts. The chip is based on pages, each page size is 512Byte, 32 pages form a block, and there are 4096 blocks in total. It has the function of reading and writing in units of pages, and the unit of erasing is in blocks, and no special erasing voltage is required. The chip also has a page copy function. The hardware connection is as follows:

①Pins 13 and 36 are power ground and ground signal; pins 12 and 37 are connected to V3.3 signal;

②29, 30, 31, 32, 41, 42, 43, 44 are 8-bit parallel IO interfaces, connected to the bus AD[0..7];

③Pin 9 is the chip selection input signal, connected to the nCE signal, controlled by the single-chip microcomputer;

④ 16 and 17 are command and address input signals, which are respectively connected to CLE and ALE signals and controlled by a single-chip microcomputer;

⑤ Pins 8 and 18 are read and write input signals, which are respectively connected to nWR and nRD signals and controlled by a single-chip microcomputer. The advantage of the bypass connection here is that the data can be directly transmitted between the USB interface chip and the mass storage FLASH chip, and the single-chip microcomputer only needs to be responsible for generating nWR and nRD pulse signals. The reading of the USB interface chip is the writing of the mass storage FLASH chip, and vice versa;

⑥Pin 19 is the write protection input signal, which is active low and not used, so it is connected to the V3.3 signal;

⑦ Pin 7 is the operation completion/need to wait for the output signal. When it is connected to nINT, it notifies the microcontroller of the next operation. It is mainly used to accelerate the completion of the read and write tasks of the large-capacity storage FLASH chip.

The control software block diagram of the USB mass storage device designed by the present invention is as shown in Figure 7, and is made up of 2 parts: the USB device recognition part is completed by the control endpoint 0 reading and writing, and meets USB specification 1.1; the mass storage reading and writing part is composed of The reading and writing of endpoint 2 is completed, which conforms to USB MASS STORAGE CLASS BULK-ONLY TRANSPORT. In addition, it must comply with the usage specifications of USB interface devices and mass storage chips.

The detailed process of the first part of USB device identification is as follows:

(1) Initialization. Set the control port of the single-chip microcomputer to the output state, do not select the USB interface device and the mass storage chip; set the bus port of the single-chip microcomputer to the input state, and give up the bus control right;

(2) Self-expression full-speed USB device. Pull down the DP pin of the USB interface device, tell the computer that a full-speed USB device is plugged into the USB interface, and set the appropriate output oscillation frequency:

①Call the D12_SetMode function provided in the instruction file of the device to disconnect the device. Note that D12_SetMode calls the underlying D12_Output function. When the MCU writes data to the USB interface device, it should first set the bus to the output state, then select the USB interface device through the nCS signal, and then send commands sequentially through the combination of CLE, nWR, and nRD signals. data. After completion, the bus is restored to the input state, and the USB interface device is not selected. The operation of another underlying D12_Input function is similar to this, and will not be described again;

② Wait for 50 milliseconds;

③Call the D12_SetDMA function to turn off the DMA function;

④Call the D12_SetMode function again, turn on the device and set the appropriate output oscillation frequency;

(3) Check whether endpoint 0 has received data. Call the D12_ReadEndpoint function to only read the length of the data received by the input buffer of endpoint 0 (data that cannot be cleared). If the length is greater than 0, it means that the computer has sent data to the USB device. Read the packet type to determine whether it is a SETUP packet. Through the function D12_ReadLastTransactionStatus, the interrupt flag bit input by the endpoint 0 of the USB interface device is cleared, and the type of the data packet of the endpoint is obtained at the same time. If not creating a packet, set the idle bit. Otherwise, further processing is required.

(4) Read the buffer 8 bytes and clear the buffer. Call the D12_ReadEndpoint function to read 8 bytes of the endpoint 0 buffer, and clear the buffer for the next read-in data. If the read data is less than 8 bytes, it means that the passed data is incorrect, set the idle bit, and call the function D12_SetEndpointStatus to block the input/output of endpoint 0; otherwise, further specific analysis is required.

(5) Analyze the USB request. Call the D12_AcknowledgeEndpoint function to unlock the input/output of endpoint 0, and extract the data length of the next operation from the length field of the establishment packet (if it is greater than 127, it will be intercepted as 127). Check the direction bit in the packet type field. If it is set, the direction of the next data transmission is from the device to the computer. This may be the standard USB request of GetConfiguration, Get Descriptor, Get Interface, and Get status. On the contrary, it is from the computer to the device, check the data length of the next operation:

1. Equal to 0, it may be Set Address, Set Configuration, Set Feature, Set Interface, SetDescriptor standard USB request.

2. Not greater than 8, it is to output data to the device, clear the idle bit, and set the receiving bit to prepare to receive data.

3. If it is greater than 8, call the function D12_SetEndpointStatus to block the input/output of endpoint 0.

(6) Respond to all USB requests. Check the Create Packet Request Type field:

①Standard request, make a specific response according to the request field of the establishment package.

I.GET_STATUS, there are 3 situations to create a package request type field, and return 2 bytes of information respectively:

0x00: 0x00 0x00 (remote wake-up forbidden \ bus power), 0x02 0x00 (allowed);

0x01: 0x00 0x00 (interface status);

0x02: 0x01 0x00 (endpoint disabled), 0x00 0x00.

II. CLEAR_FEATURE, divided into two cases: device remote wake-up and endpoint prohibition, record and call D12_SetEndpointStatus to make corresponding settings, return 0 length data to indicate completion.

III.SET_FEATURE, according to the record, returns one byte of data to reflect the two situations of device remote wakeup and endpoint prohibition.

IV.SET_ADDRESS, extract the new address from the value field of the packet, call the D12_SetAddressEnable function to set the device to this address, and return 0-length data to indicate completion.

V.GET_DESCRIPTOR, depending on the situation, return the device descriptor, or return all configuration, interface, class, and endpoint descriptors.

VI.GET_CONFIGURATION, Return Returns one byte of configuration/clear data.

VII.SET_CONFIGURATION, extract the configuration/clear flag from the value field of the package, call the function D12_SetEndpointEnable to set/clear the configuration, and return 0 length data to indicate completion.

VIII.GET_INTERFACE, returns a byte of data 0 to indicate completion.

IX.SET_INTERFACE, returns 0-length data to indicate completion.

In other cases, call the function D12_SetEndpointStatus to block the input/output of endpoint 0.

② Type request, if it is a USB_CLASS_MASS_BulkOnly_Reset request, return 0 length data to indicate OK; if it is a USB_CLASS_MASS_BulkOnly_GetMaxLun request, return a byte of data 0 as required, indicating that only 1 LUN is supported.

(7) Endpoint 0 has data to send: send data. Call the function D12_ReadLastTransactionStatus to output the status of USB interface device endpoint 0, and clear the interrupt flag bit. If the idle bit=0 and the send bit=1, it means that there is data to be sent. Call the function D12_WriteEndpoint to further send up to 16 bytes of data. The last sending must be less than 16 bytes, indicating the end of sending.

The detailed process of the second part of the mass storage read and write part is as follows:

Check if endpoint 2 received data. Read the buffer 36 bytes, clear the buffer, match check the first 4 bytes, and parse the SCSIOP command. Call the D12_ReadEndpoint function to read up to 36 bytes of data received by the input buffer of endpoint 2 and clear the buffer. If the length is not 0, it means that the computer has sent data to the USB device. Match check whether the 0th, 1st, 2nd, 3rd bytes are 0x55, 0x53, x042, 0x43, if they do not match, no further processing. Back up the packet signature of the 4th to 7th bytes for reply; the 15th byte is a mass storage command. To complete the remaining write operations between the last write operation and this operation, execute the following PreRestore program:

           
Procedure PreRestore

begin

If the flag is set once per block operation,
If another write command is encountered, and the logical area address falls between the last logical area address and the upper boundary of the block

        if,

Restore the data in the unwritten area in the middle of the block from the backup block;
Else

Restore the data in the unwritten area at the end of the block from the backup block, and clear the operation once flag for each block;

fi

fi

end

        

Extract the high and low bytes of the logical area address from 19 and 20 bytes respectively; extract the high and low bytes of the logical area length from 22 and 23 bytes respectively. According to the mass storage command, corresponding processing is performed as follows.

(1).SCSIOP_WRITE write command: Execute the following Backup_DirectWrite__Restore backup_direct write_recovery program, the reliability and life of the USB mass storage device all depend on it:

           
Procedure Backup_DirectWrite_Restore

begin

if start writing a page,

1. If the flag is cleared once per block operation,

Record the current logical area address and the relative address in the block where the logical area is located;

If the end address of the area to be written falls within the block where the logical area is located,

Erase the backup block (set an area of appropriate size behind the mass storage);

Back up the data that does not want to be written in the back area to the backup block;

If the relative address in the else if logical block is not 0, erase the backup block;

fi
If the relative address in the logical block is not 0,
        <!-- SIPO <DP n="7"> -->
        <dp n="d7"/>
Back up the data that does not want to be written in the front area to the backup block;

Erase the current block to be written;
Restore the previous area that you do not want to write from the backup;

fi

2. If the relative address in the logical block is not 0, erase the current block;

fi

Call D12_ReadEndpoint to read 64 bytes of the input port of endpoint 2 and write to the mass storage; complete 8 times

During operation, after writing a logical area, the address of the logical area increases by 1 accordingly;

if the logical area address is still in the same block
Set the flag for one operation per block;

Else

Clear the flag for one operation per block;

fi

end

        

(2).SCSIOP_READ, starting from the logical area address, if at least one of the USB interface device endpoint 2 double-ring write buffers is empty, read the large-capacity storage 64 bytes one by one, and call D12_WriteEndpoint to write the endpoint 2 output port (the same below ), until the contents of the rated number of logical areas are transferred to the computer. If necessary, D12_WriteEndpoint can be deformed to speed up the operation;

(3). SCSIOP_TEST_UNIT_READY, send 13 bytes of OK information. The 13 bytes are specifically: 0x55, 0x53, 0x42, 0x43, 4-byte signature, 0, 0, 0, 0, 0;

(4). SCSIOP_REQUEST_SENSE, first returns 14 bytes of illegal request information, and then sends 13 bytes of OK information. The 0th byte in the 14 bytes is 0xf0, 2 is 0x05, 7 is 0x0a, 12 is 0x20, and the rest are 0.

(5).SCSIOP_INQUIRY, first returns 36 bytes of device information, and then sends 13 bytes of OK information. The first byte in section 36 is 0x80, 3 is 0x01, 4 is 0x1f, and the rest are 0.

(6). SCSIOP_MEDIUM_REMOVAL, send 13 bytes of OK information.

(7). READ_FORMAT_CAPACITIES, first returns 12-byte formatted capacity information, and then sends 13-byte OK information. The third byte in the 12 bytes is 0x08, 4, 5, 6, and 7 are the total number of logical areas (high first), 8 is 0x02, 9, 10, and 11 are the number of logical area bytes (high first), and the rest is 0.

(8). SCSIOP_READ_CAPACITY, first returns 8-byte capacity information, and then sends 13-byte OK information. 0, 1, 2, and 3 in the 8 bytes are numbers starting from 0, and the number of the last logical area (high first), and 4, 5, 6, and 7 are the number of bytes in the logical area (high first).

(9).SCSIOP_VERIFY, send 13 bytes of OK information.

(10).SCSIOP_MODE_SENSE, first return 8-byte mode information, and then send 13-byte OK information. The 0th byte in section 8 is 0x1C, 1 is 0x06, 3 is 0x01, and the rest are 0.

According to content of the present invention, adopt single-chip microcomputer MDT10P22 as controller, download the software development tool of MDT10P22 from the Internet, according to the software process that the present invention provides, design control software, generate the binary programming file of MDT10P22. Use PROTEL circuit diagram design software to draw the schematic diagram as shown in the attached drawing. Plan the placement of components, use patch components, and draw a beautiful PCB diagram. Generate parts list from PCB drawing. Download Microsoft's DDK device driver development tool from the Internet, download the UMSS U disk driver package, modify and generate the U disk driver running on WIN98, and use the smart installation packaging program to package and generate the SETUP.EXE installation program.

Claims (5)

1, a kind of USB mass storage device, constitute by hardware and software two parts, it is characterized in that hardware is formed by connecting through circuit by USB interface and power source generator circuit, oscillatory circuit, usb communication circuit, single chip machine controlling circuit, mass memory interface circuit, wherein, USB interface and power source generator circuit provide the USB interface with the usb communication circuit, and supply remaining circuit work from the power supply of about 3.3 volts of USB power supply derivation; Oscillatory circuit drives the usb communication circuit working; The usb communication circuit is responsible for the transmitting-receiving of usb data bag; It is mass storage device by computer Recognition oneself that single chip machine controlling circuit is responsible for by the usb communication circuit, and controls the read-write of mass memory interface circuit intelligently; The mass memory interface circuit is preserved the blocks of data that computing machine transmits via the usb communication circuit, simultaneously also under the effect of single chip machine controlling circuit via the usb communication circuit to computing machine transmission block data.

2, USB mass storage device according to claim 1 is characterized in that described power supply generation circuit adopts 3 diodes to be composed in series, and obtains 3.4 volts power supply from the step-down of 5 volts of USB power supplys; Single-chip microcomputer adopts high speed PIC compatible type MCU single-chip microcomputer MDT10P20, and the USB interface device adopts the PDIUSB12D chip, and mass storage adopts the FLASH chip, and the three forms USB high capacity memory module.

3, USB mass storage device according to claim 1 is characterized in that described Control Software is made of 2 parts: USB device identification division and high capacity storage read-write part; Wherein, the USB device identification division is finished by 0 read-write of control end points, meets USB standard 1.1; High capacity storage read-write part is finished by end points 2 read-writes, meets USB MASS STORAGE CLASS BULK-ONLY TRANSPORT standard; In addition, the operating specification that also meets USB interface device and high capacity storage chip.

4, USB mass storage device according to claim 1 is characterized in that in the described high capacity storage read-write software,

(1) have one finish last time write operation and this operation between the PreRestore program of the write operation left over:

Flag set of the every block operations of if,

If meets another write order, and the logic area address drop on last logic area address and its piece upper bound it

Between,

From backup, recover the data in the middle unwritten zone of this piece;

else

From backup, recover the data of this piece afterbody unwritten areas, remove will of every block operations;

fi

fi

(2) there is a Backup_DirectWrite_Restore who is used for write operation back up _ directly to write _ recovery routine, supports multiple file layouts such as FAT, FAT32, NTFS:

If begins to write one page,

1. if every block operations once indicates removing,

Write down the relative address in of living in of current logic area address and the logic area;

The end addresses in the zone that if is to be written drops within of living in of the logic area,

Wipe backup block;

Backup does not desire to write the data of Background Region to backup block;

Relative address is not 0 in the else if logical blocks, wipes backup block;

fi

Relative address is not 0 in the if logical blocks,

Backup does not desire to write the data of front area to backup block;

Wipe the current piece write desired;

From backup, recover not desire the front area write;

fi

2., wipe current block if relative address is not 0 in the logical blocks;

fi

Call D12_ReadEndpoint and read end points 2 input ports 64 bytes, write mass storage; Finish 8 times

During operation, write a logic area, correspondingly the logic area address increases by 1;

If logic area address still same fast in,

The every block operations of set once indicates;

else

Removing every block operations once indicates;

fi

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