CN1581021B - Personal digital assistant capable of reducing cold start probability and method thereof - Google Patents

Abstract

A method for reducing the probability of cold boot in a computer system and a computer system thereof. The computer system has a CPU for controlling the computer system, a wake-up button for waking up the CPU from a sleep mode, and a battery for supplying power to the computer system. The CPU supports a software battery fault handling function. The method of the present invention includes, when the CPU is in sleep mode and the computer system is in a state where the battery power supply is uncertain, even if a wake-up event occurs, the CPU continues to remain in sleep mode; and when the CPU is in sleep mode and the period during which the wake-up button is pressed is less than a predetermined value, the CPU continues to remain in sleep mode.

Description

Personal digital assistant and method for reducing cold boot probability

(1) Technical field

The present invention relates to a method for reducing the probability of cold boot in a computer system and its computer system, and in particular to a Synchronous Dynamic Random Access (SDR) that can avoid battery faults (Battery Fault) in computer systems. Memory, SDRAM) data loss, to reduce the method and its computer system of the probability of cold boot.

(2) Background technology

For a computer system whose main power source is a battery, when a battery failure occurs and the battery cannot continue to supply power, the computer system must enter a sleep mode in real time to reduce power consumption. Among them, the battery failure refers to the situation that the battery power is exhausted, or the computer system is hit by an external force, so that the battery is separated from the computer system and cannot continue to supply power. The computer system is, for example, a Personal Digital Assistant (PDA).

The central processing unit (Central Processing Unit, CPU) used by general computer systems includes at least two modes: normal operation mode (Normal Operation Mode) and sleep mode (Sleep Mode). If the CPU is a CPU capable of handling battery failure, the CPU will directly enter sleep mode when the battery failure occurs. If the CPU used by the computer system is a CPU supporting a software battery fault (Software Battery fault) processing function, when a battery fault occurs, the CPU will receive a battery fault indication event. At this time, the CPU regards the battery failure indication event as an interrupt source (InterruptSource). This interrupt source must be processed by the software program code (Software Code) before the CPU can enter the sleep mode.

When a battery failure occurs and the CPU enters sleep mode, the remaining power on the main circuit board of the computer system, including the power stored in the equivalent capacitor on the main circuit board and the power of the backup power supply, will continue to be supplied to SDRAM to continue Save data on SDRAM. Like this, as long as the user replaces a new battery or reinstalls the dropped battery, the CPU can be woken up again, and the computer system will return to the state before entering the sleep mode for the user to continue using. When the CPU is woken up, the CPU will perform hardware initialization first, and then the CPU can start to execute the application program. Wherein, when the CPU is initializing the hardware, the CPU will perform a loading procedure of the software program code. The loading program of the software program code includes the loading program of the boot code (Boot Code).

However, when the above-mentioned CPU used is a CPU that supports the software battery failure processing function, the battery failure must occur after the CPU has successfully executed the hardware initialization action, and the software program code can handle the corresponding battery failure indication event Instead, put the CPU into sleep mode. If the battery failure occurs when the CPU is executing hardware initialization, the software program code will not be able to handle the battery failure indication event, and will not be able to make the CPU enter the sleep mode. In this way, since the CPU will remain in the normal operating mode that consumes a large amount of power, and the battery cannot supply power, the residual power on the main circuit board of the computer system will be rapidly consumed until all the power is consumed. At this time, the data on the SDRAM will be completely lost due to the exhaustion of the power on the main circuit board, and the main circuit board cannot continue to supply power. All user data and previously downloaded programs will be cleared. After the user replaces the battery or reinstalls the battery, the data in the SDRAM has disappeared, so the computer system can only be cold-booted (Cold Reset), returning to the initial state of the computer system when it leaves the factory.

For ease of description, the period during which the CPU executes hardware initialization after the CPU wakes up from sleep mode is defined as the first period T1, and after the CPU executes hardware initialization, the period during which the CPU can normally start executing the application program is defined as the second period. Period T2.

Please refer to FIG. 1 , which is a waveform diagram of related signals when the battery failure occurs in the first period T1 . The power enable signal PWR_EN is used to indicate whether to enter the sleep mode. When the power enable signal PWR_EN is enabled (eg high level), the CPU is in the normal working mode; and when the power enable signal PWR_EN is disabled (eg low level), the CPU is in the sleep mode. The CPU core power signal CPU_CR_PWR is used to indicate the power supply state of the CPU core power. When the CPU is in the normal working mode, the battery supplies power to the CPU normally, so the CPU core power signal CPU_CR_PWR is at a high level, and when the CPU is in the sleep mode, the battery does not supply power to the CPU, so the CPU core power signal CPU_CR_PWR is at a low level.

In addition, the CPU peripheral component power supply CPU_IO_PWR is used to indicate the power supply status of the CPU peripheral components. Regardless of whether the CPU is in the normal working mode or the sleep mode, the peripheral components of the CPU have power supply, so the CPU_IO_PWR of the CPU peripheral component power supply is at a high level. The battery fault signal BTRY_FLT is used to indicate whether there is a battery fault. When the battery fault signal BTRY_FLT is enabled, the battery fault signal BTRY_FLT turns to a low level.

Please refer to Figure 1. At the time point t1, the CPU wakes up from the sleep mode, the power enable signal PWR_EN turns to a high level, and the CPU enters the first period T1. If a battery failure occurs during the first period T1, a battery failure indication event 102 will be generated, and the battery failure signal BTRY_FLT will turn to a low level. At this time, the software program code will not be able to handle the battery fault, so the CPU will continue to maintain the normal working mode and consume a large amount of electric energy. After the time point t2, since the power on the main circuit board will be exhausted, the main circuit board will no longer be able to provide power to the SDRAM. Data on SDRAM will be completely gone.

Please refer to FIG. 2 , which is a waveform diagram of related signals when the battery failure occurs in the second period T2 . When the battery failure occurs at the time point t3 in the second period T2 and the battery failure indication event 202 is generated, since the software program code can successfully process the battery failure indication event 202, the CPU will successfully enter the sleep mode to reduce power consumption . At this time, the remaining power on the main circuit board can still be supplied to the SDRAM, so the data stored in the SDRAM can still be completely preserved.

Therefore, how to solve the problem that the battery failure occurs in the first period, so that the residual power of the main circuit board will be exhausted due to the CPU still maintaining the normal operating mode, and the main circuit board can no longer supply SDRAM power and the data stored in SDRAM will be lost. It is one of the directions of the industry's efforts to reduce the chance of cold booting of the computer system.

(3) Contents of the invention

In view of this, the object of the present invention is to provide a method for reducing the probability of cold boot in a computer system and the computer system thereof. The present invention can effectively avoid the problem of SDRAM data loss caused by battery failure occurring in the first period, and can reduce the probability of cold booting.

According to the object of the present invention, a method for reducing the probability of cold boot in a personal digital assistant having a central processing unit for controlling the personal digital assistant from a sleep mode to A wake-up button for mode wake-up, and a battery used to provide power for the personal digital assistant, the central processing unit supports a software battery fault handling function, the method includes: when the central processing unit is in the sleep mode, and the When the personal digital assistant is in a state of uncertain battery power supply, even if a wake-up event occurs, the CPU is still maintained in the sleep mode; and when the CPU is in the sleep mode, and the wake-up button is pressed When the period is less than a predetermined value, the central processing unit continues to be in the sleep mode.

The present invention also provides a personal digital assistant, including: a central processing unit, used to control the personal digital assistant, the central processing unit supports software battery failure processing function; a circuit unit, electrically connected with the central processing unit, The circuit unit is used to receive a wake-up event and selectively output the wake-up event to the central processing unit; a judgment circuit is used to control the circuit unit according to the state of the personal digital assistant; and a battery is used for The personal digital assistant provides power; wherein, when the central processing unit is in the sleep mode, when a wake-up event occurs, the judging circuit judges whether the personal digital assistant is in a battery failure state, the battery cover of the battery On state or battery low power state, if yes, then the circuit unit does not output the wake-up event to the CPU, so that the CPU remains in the sleep mode.

The present invention also provides a method of reducing the chance of cold boot in a personal digital assistant having a central processing unit for controlling the personal digital assistant for waking the central processing unit from a sleep mode A wake-up button, and a battery for supplying power to the personal digital assistant, the central processing unit supports a software battery fault handling function, the method includes: when the central processing unit is in the sleep mode, when a wake-up event occurs , judging whether the personal digital assistant is in the state of battery failure, the state of opening the battery cover of the battery or the state of low battery power, if so, the central processing unit is still maintained in the sleep mode.

In order to make the above-mentioned purposes, features and advantages of the present invention more comprehensible, a preferred embodiment is specifically cited below, and is described in detail in conjunction with the accompanying drawings as follows:

(4) Description of drawings

FIG. 1 is a waveform diagram of related signals when a battery failure occurs in a first period T1.

FIG. 2 is a waveform diagram of related signals when the battery failure occurs in the second period T2.

FIG. 3 is a block diagram of a computer system for executing the above-mentioned program (1) according to a preferred embodiment of the present invention.

FIG. 4A is a waveform diagram of the first signal S1 and the second signal S2 when the central processing unit (CPU) of FIG. 3 is in sleep mode and the judging circuit judges that the computer system is in an uncertain state of battery power supply.

FIG. 4B is a waveform diagram of the first signal S1 and the second signal S2 when the CPU of FIG. 3 is in the sleep mode and the judging circuit judges that the computer system is not in the state of uncertain battery power supply.

Fig. 5 is a block diagram of a computer system executing the above-mentioned program (2) according to a preferred embodiment of the present invention.

FIG. 6A is a waveform diagram of the third signal S3 and the fourth signal S4 when the CPU is in the sleep mode and the wake-up button is pressed for less than a predetermined value P in FIG. 5 .

FIG. 6B is a waveform diagram of the third signal S3 and the fourth signal S4 when the CPU is in the sleep mode and the wake-up button is pressed for a period greater than a predetermined value P in FIG. 5 .

(5) specific implementation

The present invention avoids the traditional problem of losing all SDRAM data due to power exhaustion by preventing battery failure from occurring during the first period T1. And the program that the present invention proposes to prevent battery failure from occurring in the first period T1 includes: (1) when the computer system is in sleep mode, and when the computer system is in a state where the power supply of the battery is uncertain, including battery failure state, battery When the cover is open or the battery is low, even if a wake-up event occurs, the generated wake-up event is not sent to the CPU, so that the CPU continues to stay in sleep mode. (2) When the computer system is in the sleep mode, the computer system judges whether the wake-up button is triggered by an external force by judging the length of time the wake-up button is pressed. When the period during which the wake-up button is pressed is less than a predetermined value, the CPU is also kept in the sleep mode. Procedure (1) and procedure (2) may be implemented simultaneously or individually.

Please refer to FIG. 3 , which is a block diagram of a computer system 300 for executing the above procedure (1) according to a preferred embodiment of the present invention. The computer system 300 includes a central processing unit (Central Processing Unit, CPU) 302, a circuit unit 304, a judgment circuit 306 and a battery 308. The CPU 302 is used to control the computer system 300. CPU 302 is to support software battery failure processing function. The circuit unit 304 is electrically connected with the CPU 302. The circuit unit 304 is used for receiving a first signal S1 and outputting a second signal S2. The judging circuit 306 is used for controlling the circuit unit 304 according to the state of the computer system 300 . The battery 308 is used to supply power to the computer system 300 .

Please refer to FIG. 4A, which is a waveform diagram of the first signal S1 and the second signal S2 when the CPU 302 of FIG. 3 is in sleep mode and the judging circuit 306 judges that the computer system 300 is in an uncertain state of battery power supply. Assume that when the first signal S1 is enabled, the first signal S1 is at a low level; similarly, when the second signal S2 is enabled, the second signal S2 is at a low level. When a wake-up event 410 is generated at the time point t4, the first signal S1 is turned to a low level. When the CPU 302 is in sleep mode, and the judging circuit 306 judges that the computer system 300 is in an uncertain state of battery power supply, the circuit unit 304 will not transmit the wake-up event 410 to the CPU 302, so the second signal S2 is maintained at this time at a high level. Even though the wake-up event 410 is input to the circuit unit 304, since the CPU 302 does not receive the wake-up event, the CPU 302 will still remain in the sleep mode.

Please refer to FIG. 4B, which is a waveform diagram of the first signal S1 and the second signal S2 when the CPU 302 of FIG. When a wake-up event 420 is generated at the time point t5, the first signal S1 is turned to a low level. When the CPU 302 is in sleep mode, and the judging circuit 306 judges that the computer system 300 is not in a state of uncertain battery power supply, the circuit unit 304 will send a wakeup event 422 to the CPU 302. CPU 302 will be woken up.

When the computer system is in an uncertain state of battery power supply, the present invention prevents the CPU 302 from being woken up by not allowing the wake-up event to be input to the CPU 302, so as to prevent the computer system from entering the above-mentioned first period T1 of executing hardware initialization. This is because, when the computer system 300 is in (1) the battery failure state that the battery has no power and the battery falls off, and the battery cannot supply power normally; (2) the user will open the battery cover for fixing the battery, and will take out the battery to replace the battery or (3) in a low battery state in which the power stored in the battery is too low, if the computer system 300 is woken up, the computer system 300 enters the normal working mode, and enters the first period T1 to perform hardware initialization. , the above three states may cause the battery to continue to supply power, the remaining power on the main circuit board will be exhausted rapidly, and all SDRAM data will be lost. Therefore, the present invention detects the state of the computer system 300, and when the computer system meets the above three states, the CPU 302 is kept in the sleep mode. In this way, the CPU 302 will not enter the above-mentioned first period T1, and there will be no problem that the software program code cannot handle the battery failure event as in the traditional method. The remaining power on the main circuit board can continue to supply power to the SDRAM to maintain its stored data. Therefore, the computer system 300 of the present invention can avoid SDRAM data loss and reduce the chance of cold boot.

Please refer to FIG. 5 , which is a block diagram of a computer system 500 for executing the above procedure (2) according to a preferred embodiment of the present invention. The computer system 500 includes a wake-up button 530, a CPU 502, a delay protection circuit 532 and a battery 508. The wake-up button 530 is configured on the casing of the computer system 500 for operation by the user. The CPU 502 is used to control the computer system 500, and the CPU 502 supports software battery failure handling functions. The delay protection circuit 532 is used to detect the state of the wake-up button 530 . The wake-up button 530 outputs a third signal S3 to the delay protection circuit 532, and the delay protection circuit 532 outputs a fourth signal S4 to the CPU 502. The battery 508 is used to provide power required by the computer system 500 .

The wake-up button 530 may be pressed by the user's finger, or may be pressed because the computer system 500 is dropped and hit. When the computer system 500 is dropped, the battery 508 is likely to fall off at the same time due to the impact. Generally speaking, the general value of the time length for the wake-up button 530 to be pressed due to collision or impact is about 1-2 milliseconds (millisecond), and the time length for the user to press the wake-up button 530 with a finger is usually longer, which is generally Values around 100 milliseconds or so. Therefore, in the present invention, by setting a predetermined value P, the predetermined value P is greater than 1-2 milliseconds and less than 100 milliseconds. As long as it is determined that the wake-up button 530 is pressed for less than the predetermined value P, it can be known that the wake-up button 530 is pressed due to a collision or impact.

Because when the computer system 500 is dropped or hit, the battery 508 is likely to be knocked off as well. If the battery 508 falls off, the battery 508 cannot normally supply power to the computer system 500 . At this time, if the CPU 502 is woken up from the sleep mode, the residual power on the main circuit board will be exhausted quickly, and the SDRAM data will be lost. Therefore, when the CPU 502 is in sleep mode, and the delay protection circuit 532 detects that the wake-up button 530 is pressed for less than the predetermined value P, it means that the computer system 500 may be bumped or impacted, and the battery 508 may have fallen off. At this time, the present invention avoids the situation of SDRAM data loss by keeping the CPU 502 in the sleep mode.

Please refer to FIG. 6A, which is a waveform diagram of the third signal S3 and the fourth signal S4 when the CPU 502 is in the sleep mode and the wake-up button 530 is pressed for less than a predetermined value P in FIG. Assume that when the third signal S3 is enabled, the third signal S3 is at a low level; similarly, when the fourth signal S4 is enabled, the fourth signal S4 is at a low level. When a wake-up event 610 is generated at the time point t6, the third signal S3 is turned to a low level. When CPU 502 is in sleep mode, and delay protection circuit 532 detects that the period during which wake-up button 530 is pressed is less than predetermined value P, although delay protection circuit 532 receives wake-up event 610, delay protection circuit 532 will not transmit any wake-up event Give CPU 502. Therefore, the fourth signal S4 output by the delay protection circuit 532 will remain at a high level at the time point t6, and the CPU 502 will continue to maintain the sleep mode.

Please refer to FIG. 6B , which is a waveform diagram of the third signal S3 and the fourth signal S4 when the CPU 502 is in sleep mode and the wake-up button 530 is pressed for a period greater than a predetermined value P in FIG. 5 . When a wake-up event 620 is generated at the time point t7, the third signal S3 is turned to a low level. When the CPU 502 is in the sleep mode, and the delay protection circuit 532 detects that the wake-up button 530 has been pressed for a period greater than the predetermined value P, it means that the user has pressed the wake-up button 530 and intends to wake up the computer system 500. Therefore, after the delay protection circuit 532 receives the wakeup event 620, the delay protection circuit 532 will output a wakeup event 622 to the CPU 502. At this time, the fourth signal S4 output by the delay protection circuit 532 turns to a low level at the time point t6, and the CPU 502 will be woken up.

Wherein, the delay protection circuit 532 is controlled by a control signal CTRL. When the computer system 500 is in the sleep mode, the control signal CTRL is enabled, and the delay protection circuit 532 is activated to perform the actions shown in FIG. 6A and FIG. 6B . And when the computer system 500 is in the normal working mode, the control signal CTRL is disabled, and the delay protection circuit 532 is not activated. At this time, the third signal S3 will be directly transmitted to the CPU 502. In this way, the operation speed of the computer system 500 in the normal working mode can be accelerated.

The method for reducing the probability of cold boot in the computer system and the computer system disclosed in the above-mentioned embodiments of the present invention can effectively avoid the problem that the battery failure occurs in the first period T1, resulting in the loss of SDRAM data, and can reduce the risk of cold boot probability. For computer systems, especially personal digital assistants, the present invention has the advantages of extending the time for SDRAM to store data and preserving data integrity.

In summary, although the present invention has been disclosed as above with a preferred embodiment, it is not intended to limit the present invention. Any person familiar with the art may make various modifications without departing from the spirit and scope of the present invention. Modifications and replacements, so the protection scope of the present invention shall prevail as defined by the appended claims.

Claims (5)

1. method that in personal digital assistant, reduces the probability of cold boot, this personal digital assistant have in order to a central processing unit of controlling this personal digital assistant, in order to this central processing unit from a sleep pattern wake up one wake button up, and with thinking that this personal digital assistant provides a battery of power supply, this central processing unit support software battery failures processing capacity, this method comprises:

Be at this central processing unit under the situation of this sleep pattern, and this personal digital assistant is when being in a battery electric quantity and supplying uncertain state, even a wake events produces, this central processing unit still continues to be maintained at this sleep pattern; And

When this central processing unit is in this sleep pattern, and this wake that button is pressed up during during less than a predetermined value, then this central processing unit continues to be maintained at this sleep pattern.

2. the method for claim 1 is characterized in that, this predetermined value is waken the general value of button because of collision or the time span that is pressed of bump up greater than this, and wakes the general value of the time span that button pressed by a user up less than this.

3. the method for claim 1 is characterized in that, this predetermined value is greater than 2 milliseconds, and less than 100 milliseconds.

4. personal digital assistant comprises:

One central processing unit is in order to control this personal digital assistant, this central processing unit support software battery failures processing capacity;

One circuit unit electrically connects with this central processing unit, and this circuit unit is in order to receiving a wake events, and optionally exports this wake events to this central processing unit;

One decision circuitry in order to the state according to this personal digital assistant, is controlled this circuit unit; And

One battery is with thinking that this personal digital assistant provides power supply;

Wherein, be at this central processing unit under the situation of this sleep pattern, in wake events generation, this decision circuitry is judged battery cover open mode or the low state of charge of battery whether this personal digital assistant is in battery fault condition, battery, if, then this circuit unit does not export this wake events to this central processing unit, makes this central processing unit still continue to be maintained at this sleep pattern.

5. method that in personal digital assistant, reduces the probability of cold boot, this personal digital assistant have in order to a central processing unit of controlling this personal digital assistant, in order to this central processing unit from a sleep pattern wake up one wake button up, and with thinking that this personal digital assistant provides a battery of power supply, this central processing unit support software battery failures processing capacity, this method comprises:

Be in this sleep pattern in this central processing unit, in wake events generation, judge whether this personal digital assistant is under the battery cover open mode or the low state of charge of battery of battery fault condition, battery, if then this central processing unit still continues to be maintained at this sleep pattern.

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