CN1567721A - PWM buffer circuit for adjusting the frequency and duty cycle of the PWM signal - Google Patents

Abstract

A PWM buffer circuit comprises a duty cycle conversion circuit and a fixed frequency PWM signal generation circuit. The duty cycle conversion circuit is used for receiving a first PWM signal and then generating a duty cycle reference voltage based on a first duty cycle of the first PWM signal. The duty cycle reference voltage is a one-to-one mapping function of the first duty cycle. The fixed frequency PWM signal generating circuit is used for receiving the work cycle reference voltage and then outputting a second PWM signal with a fixed frequency. A second duty cycle of the second PWM signal is determined based on the duty cycle reference voltage. In addition, the second duty cycle is a one-to-one mapping function of the duty cycle reference voltage.

Description

PWM buffer circuit for adjusting the frequency and duty cycle of the PWM signal

technical field

The present invention relates to a buffer circuit applied to pulse width modulation (Pulse Width Modulation, PWM) signals, in particular to a PWM buffer circuit for adjusting the frequency and duty cycle (Duty Cycle) of the PWM signal.

Background technique

In recent years, the speed control method of the cooling fan motor is mainly achieved by using a pulse width modulation (Pulse Width Modulation, PWM) signal. Figure 1 shows a circuit block diagram of a fan motor speed control circuit using the existing 'PWM control method. Referring to FIG. 1 , the PWM signal generating unit 10 outputs a PWM signal S1 to the driving circuit 11 . Based on the PWM signal S1 , the driving circuit 11 outputs a driving signal A to the fan motor 12 to control the speed of the fan motor 12 . Specifically, a signal characteristic of the PWM signal S1 is the so-called "duty cycle", that is, the ratio of the pulse width to the period of the PWM signal S1. It is assumed that the duty cycle of the PWM signal S1 is represented by the symbol D1 in FIG. 1 . In the aforementioned existing PWM control method, when the duty cycle D1 of the PWM signal S1 is relatively large, the drive signal A output from the drive circuit 11 can make the fan motor 12 run at a relatively high speed; The duty cycle D1 of S1 is relatively small, and the driving signal A output from the driving circuit 11 can make the fan motor 12 run at a relatively low speed.

Existing 'PWM control methods have at least two disadvantages. The first disadvantage is that the frequency of the PWM signal S1 used must be relatively high, for example higher than 10 kHz. When the frequency of the PWM signal S1 is lower than 10 kHz, the operation of the fan motor 12 will be adversely affected by switching noise. The second disadvantage is that the duty cycle D1 of the PWM signal S1 used must be limited within the range of 30% to 85% to ensure that the driving circuit 11 and the fan motor 12 can be properly controlled by the PWM signal S1.

Contents of the invention

In view of the aforementioned problems, an object of the present invention is to provide a PWM buffer circuit, which is provided in the speed control circuit of the fan motor, to expand the applicable frequency range of the PWM signal as the control signal.

An object of the present invention is to provide a PWM buffer circuit, which is installed in the speed control circuit of the fan motor, to expand the applicable duty cycle range of the PWM signal as the control signal.

According to one aspect of the present invention, a PWM buffer circuit is provided, which includes a duty cycle conversion circuit and a fixed frequency PWM signal generation circuit. The duty cycle converting circuit is used for receiving a first PWM signal, and then generating a duty cycle reference voltage based on a first duty cycle of the first PWM signal. The duty cycle reference voltage is a one-to-one mapping function of the first duty cycle. The fixed-frequency PWM signal generating circuit is used to receive the duty cycle reference voltage, and then output a second PWM signal with a fixed frequency. A second duty cycle of the second PWM signal is determined based on the duty cycle reference voltage, and the second duty cycle is a one-to-one mapping function of the duty cycle reference voltage.

According to another aspect of the present invention, a fan motor speed control circuit is provided, including a PWM signal generating unit, a PWM buffer circuit, a driving circuit, and a fan motor. The PWM signal generating unit is used for generating a first PWM signal with a first duty cycle. The PWM buffer circuit is connected to the PWM signal generating unit for converting the first PWM signal into a second PWM signal with a fixed frequency and a second duty cycle. The drive circuit is connected to the PWM buffer circuit for outputting a drive signal based on the second PWM signal. The fan motor is connected to the driving circuit, and its speed is controlled by the driving signal.

In a preferred embodiment of the present invention, the frequency of the first PWM signal can be greater than 30 Hz and the first duty cycle is within the range of 5% to 95%. Therefore, the PWM buffer circuit according to the present invention can be set in the speed control circuit of the fan motor to expand the applicable frequency range of the PWM signal of the control signal and expand the applicable duty cycle of the PWM signal of the control signal range.

Description of drawings

Figure 1 shows a circuit block diagram of a fan motor speed control circuit using the existing 'PWM control method.

FIG. 2 shows a circuit block diagram of a fan motor speed control circuit provided with a PWM buffer circuit according to the present invention.

FIG. 3 shows a detailed circuit block diagram of the PWM buffer circuit according to the present invention.

FIG. 4( a ) shows a one-to-one mapping function of the duty cycle reference voltage V1 to the duty cycle D1 of the PWM signal S1 .

FIG. 4( b ) shows that the duty cycle D2 of the PWM signal S2 is a one-to-one mapping function of the duty cycle reference voltage V1 .

FIG. 5 shows an example of a specific circuit configuration of the PWM buffer circuit according to the present invention.

Detailed ways

The foregoing and other objects, features, and advantages of the present invention will be more apparent from the following description and accompanying drawings. Preferred embodiments according to the present invention will now be described in detail with reference to the drawings.

FIG. 2 shows a circuit block diagram of a fan motor speed control circuit provided with a PWM buffer circuit 20 according to the present invention. Referring to Fig. 2, the present invention is different from the prior art shown in Fig. 1 in that the present invention arranges a PWM buffer circuit 20 between the PWM signal generation unit 10 and the drive circuit 11, so that the PWM output from the PWM signal generation unit 10 The signal S1 is converted into a PWM signal S2 by the PWM buffer circuit 20 before being input to the driving circuit 11 . Then, based on the PWM signal S2 , the driving circuit 11 outputs a driving signal B to the fan motor 12 .

Specifically, the PWM buffer circuit 20 converts the PWM signal S1 having a duty cycle D1 and a frequency F1 into a PWM signal S2 having a duty cycle D2 and a frequency F2. In the present invention, the duty cycle D2 and the frequency F2 of the PWM signal S2 are designed to be within a value range that can ensure that the speed of the fan motor is properly controlled without causing switching noise. Therefore, with this configuration, even if the duty cycle D1 and frequency F1 of the PWM signal S1 are not within the application range that allows the fan motor to perform proper operation, since the drive circuit 11 receives the PWM signal S2 converted by the PWM buffer circuit 20 , so the speed of the fan motor 12 can still be properly controlled without causing switching noise. In other words, the PWM buffer circuit 20 according to the present invention is arranged in the speed control circuit of the fan motor, so as to expand the applicable frequency range of the PWM signal of the control signal, and expand the applicable duty cycle range of the PWM signal of the control signal .

In the prior art PWM control method shown in FIG. 1 , the frequency of the PWM signal S1 must be higher than 10 kHz and the duty cycle D1 must be limited within the range of 30% to 85%. In an embodiment of the present invention, the PWM buffer circuit 20 can convert the PWM signal S1 having a frequency greater than 30 Hz and a duty cycle ranging from 5% to 95% into a PWM signal S2 having a frequency F2 greater than 10 kHz. Therefore, with the PWM buffer circuit 20 according to the present invention, the applicable frequency range of the PWM signal S1 is extended to be greater than 30 Hz and the applicable duty cycle range is extended to a range between 5% and 95%.

FIG. 3 shows a detailed circuit block diagram of the PWM buffer circuit 20 according to the present invention. Referring to FIG. 3 , the PWM buffer circuit 20 includes a duty cycle conversion circuit 21 and a fixed frequency PWM signal generation circuit 22 . Specifically, the duty cycle converting circuit 21 receives the PWM signal S1, and then generates a duty cycle reference voltage V1 based on the duty cycle D1 of the PWM signal S1. In other words, the duty cycle reference voltage V1 is a one-to-one mapping function of the duty cycle D1 of the PWM signal S1 , as shown in FIG. 4( a ). The fixed frequency PWM signal generating circuit 22 receives the duty cycle reference voltage V1, and then determines the duty cycle D2 of the PWM signal S2 based on the duty cycle reference voltage V1. In other words, the duty cycle D2 of the PWM signal S2 is a one-to-one mapping function of the duty cycle reference voltage V1 , as shown in FIG. 4( b ). To sum up, in order to convert the duty cycle D1 into the duty cycle D2, the PWM buffer circuit 20 first uses the duty cycle conversion circuit 21 to convert the duty cycle D1 into the duty cycle reference voltage V1 in the first stage, and then in the second stage The duty cycle reference voltage V1 is converted into a duty cycle D2 by the fixed frequency PWM signal generating circuit 22 .

In addition, regardless of the magnitude of the duty cycle reference voltage V1, the fixed frequency PWM signal generating circuit 22 only generates a PWM signal S2 with a fixed frequency. Therefore, the fixed-frequency PWM signal generating circuit 22 can be designed to output the PWM signal S2 with a frequency F2, wherein the frequency F2 is large enough to avoid the generation of switching noise.

In an embodiment of the present invention, the fixed-frequency PWM signal generating circuit 22 is implemented by a microchip control unit (Microchip Control Unit), wherein the microchip control unit executes the foregoing according to the present invention through the setting of a software program. function. In another embodiment of the present invention, the fixed-frequency PWM signal generating circuit 22 includes a frequency controller 23 and a PWM signal generator 24 , as shown in FIG. 3 . Specifically, the frequency controller 23 provides a frequency control signal FC for determining the frequency of the PWM signal S2 generated by the PWM signal generator 24 . Based on the duty cycle reference voltage V1 from the duty cycle conversion circuit 21 and the frequency control signal FC from the frequency controller 23 , the PWM signal generator 24 generates a PWM signal S2 having a duty cycle D2 and a frequency F2 .

FIG. 5 shows an example of a specific circuit configuration of the PWM buffer circuit 20 according to the present invention. Referring to FIG. 5 , the duty cycle conversion circuit 21 includes a transistor Q1 , a plurality of resistors R1 to R5 , a diode Dd1 , a capacitor C1 , and an operational amplifier OA1 . The frequency controller 23 includes a plurality of resistors R6 to R8, a capacitor C2, and an operational amplifier OA2. The PWM signal generator 24 includes an operational amplifier OA3 and a resistor R9.

Specifically, the gate of the transistor Q1 is used to receive the PWM signal S1 , the drain thereof is connected to a voltage source V _DD through the resistor R1 , and the source thereof is grounded. The P terminal of the diode Dd1 is electrically connected to the drain of the transistor Q1, and the N terminal thereof is electrically connected to the non-inverting input terminal of the operational amplifier OA1. Both the resistor R2 and the capacitor C1 are electrically connected between the N pole of the diode Dd1 and the ground. The resistor R3 is electrically connected between the inverting input terminal of the operational amplifier OA1 and the ground. The resistor R4 is electrically connected between the output terminal of the operational amplifier OA1 and the ground. The output terminal of the operational amplifier OA1 outputs the duty cycle reference voltage V1 to the non-inverting input terminal of the operational amplifier OA3 via the resistor R5.

The resistor R6 is electrically connected between the non-inverting input terminal of the operational amplifier OA2 and the ground. The resistor R7 is electrically connected between the non-inverting input terminal and the output terminal of the operational amplifier OA2. The capacitor C2 is electrically connected between the inverting input terminal of the operational amplifier OA2 and the ground. The resistor R8 is electrically connected between the inverting input terminal and the output terminal of the operational amplifier OA2. With this configuration, the output terminal of the operational amplifier OA2 outputs the frequency control signal FC to the inverting input terminal of the operational amplifier OA3 via the resistor R8. In the example shown in Figure 5, the frequency control signal FC is a triangular wave continuous signal with a frequency f, where:

$\mathrm{<span\; class="notranslate">\; f</span>}<span\; class="notranslate">\; =</span>\frac{\mathrm{<span\; class="notranslate">\; 1</span>}}{\mathrm{<span\; class="notranslate">\; 2</span>}{\mathrm{<span\; class="notranslate">\; R</span>}}_{\mathrm{<span\; class="notranslate">\; 8</span>}}{\mathrm{<span\; class="notranslate">\; <figure-callout\; id="2"\; label="C"\; filenames="A0313736000151.png"\; state="\{\{state\}\}">C</figure-callout></span>}}_{\mathrm{<span\; class="notranslate">\; 2</span>}}\mathrm{<span\; class="notranslate">\; ln</span>}<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 1</span>}<span\; class="notranslate">\; +</span>\mathrm{<span\; class="notranslate">\; 2</span>}\frac{{\mathrm{<span\; class="notranslate">\; R</span>}}_{\mathrm{<span\; class="notranslate">\; 6</span>}}}{{\mathrm{<span\; class="notranslate">\; R</span>}}_{\mathrm{<span\; class="notranslate">\; 7</span>}}}<span\; class="notranslate">\; )</span>}<span\; class="notranslate">\; .</span>$

In response to the duty cycle reference voltage V1 received at the non-inverting input terminal of the operational amplifier OA3 and the frequency control signal FC received at the inverting input terminal of the operational amplifier OA3, the output terminal of the operational amplifier OA3 outputs a PWM signal via a resistor R9 S2. Specifically, the operational amplifier OA3 acts as a voltage comparator, so that when the duty cycle reference voltage V1 is greater than the voltage level of the frequency control signal FC, the operational amplifier OA3 outputs the high level state of the PWM signal S2, and when the duty cycle reference voltage When V1 is lower than the voltage level of the frequency control signal FC, the operational amplifier OA3 outputs the low level state of the PWM signal S2. In this way, the PWM signal generator 24 converts the duty cycle reference voltage V1 into a duty cycle D2. In addition, the frequency F2 of the PWM signal S2 generated by the PWM signal generator 24 is equal to the frequency f of the frequency control signal FC.

Although the present invention has been described by way of illustration of preferred embodiments, it should be understood that the present invention is not limited to the disclosed embodiments. On the contrary, the invention is intended to cover various modifications and similar arrangements apparent to those skilled in the art. Accordingly, the scope of the claims of the application should be accorded the broadest interpretation to encompass all such modifications and similar arrangements.

Claims (12)

1. A pulse width modulation buffer circuit, characterized in that: the circuit comprises: A duty cycle conversion circuit for receiving a first pulse width modulation signal, and then generating a duty cycle reference voltage based on a first duty cycle of the first pulse width modulation signal, wherein the duty cycle reference voltage is the first a one-to-one mapping function of the duty cycle, and A fixed frequency pulse width modulation signal generation circuit, connected to the duty cycle conversion circuit, which is used to receive the duty cycle reference voltage, and then output a second pulse width modulation signal with a fixed frequency, wherein the second pulse width modulation signal A second duty cycle is determined based on the duty cycle reference voltage, and the second duty cycle is a one-to-one mapping function of the duty cycle reference voltage. 2. The pulse width modulation buffer circuit according to claim 1, characterized in that: the duty cycle conversion circuit comprises: a transistor, the gate of which is used to receive the first PWM signal and the source of which is grounded; a first resistor connected between the drain of the transistor and a voltage source VDD; a diode, the p-pole of which is electrically connected to the drain of the transistor; A second resistor connected between the N pole of the diode and the ground; A first capacitor connected between the N pole of the diode and the ground; a first operational amplifier, the non-inverting input terminal of which is connected to the N pole of the diode; a third resistor connected between the inverting input terminal of the first operational amplifier and the ground; an electric resistor connected between the inverting input terminal of the first operational amplifier and the output terminal of the first operational amplifier; and A fifth resistor is connected between the output end of the first operational amplifier and the fixed frequency pulse width modulation signal generating circuit. 3. The pulse width modulation buffer circuit as claimed in claim 1, wherein the fixed frequency pulse width modulation signal generating circuit is implemented by a microchip control unit through setting of a software program. 4. The pulse width modulation buffer circuit according to claim 1, wherein the fixed frequency pulse width modulation signal generating circuit comprises: a frequency controller, providing a frequency control signal for determining the fixed frequency of the second PWM signal, and A pulse width modulation signal generator, connected to the duty cycle conversion circuit and the frequency controller, generates the second pulse width modulation signal in response to the duty cycle reference voltage and the frequency control signal. 5. The pulse width modulation buffer circuit according to claim 4, characterized in that: the frequency controller comprises: A second operational amplifier having a non-inverting input terminal, an inverting input terminal, and an output terminal; a sixth resistor connected between the non-inverting input terminal of the second operational amplifier and ground; a seventh resistor connected between the non-inverting input terminal and the output terminal of the second operational amplifier; a second capacitor connected between the inverting input terminal of the second operational amplifier and ground; and An eighth resistor is connected between the non-inverting input terminal and the output terminal of the second operational amplifier. 6. The pulse width modulation buffer circuit according to claim 4, wherein the pulse width modulation signal generator comprises: a third operational amplifier, the non-inverting input of which is connected to the duty cycle switching circuit to receive the duty cycle reference voltage, and the inverting input of which is connected to the frequency controller to receive the frequency control signal, and A ninth resistor, one end of which is connected to the output end of the third operational amplifier so that the second PWM signal is output through the other end of the ninth resistor. 7. The PWM buffer circuit as claimed in claim 4, wherein the frequency control signal is a triangular wave continuous signal. 8. The PWM buffer circuit as claimed in claim 1, wherein the frequency of the first PWM signal is greater than 30 Hz and the first duty cycle is within a range of 5% to 95%. 9. The PWM buffer circuit as claimed in claim 1, wherein the fixed frequency of the second PWM signal is greater than 10 kHz. 10. A speed control circuit for a fan motor, characterized in that: the circuit includes: A pulse width modulation signal generation unit, used to generate a first pulse width modulation signal, the first pulse width modulation signal has a first duty cycle; a pulse width modulation buffer circuit connected to the pulse width modulation signal generating unit for converting the first pulse width modulation signal into a second pulse width modulation signal, the second pulse width modulation signal has a fixed frequency and a first two duty cycles; and A drive circuit, connected to the PWM buffer circuit, is used to output a drive signal to a fan motor based on the second PWM signal, so as to control the speed of the fan motor. 11. The speed control circuit of the fan motor according to claim 10, wherein the PWM buffer circuit comprises: a duty cycle conversion circuit for receiving the first pulse width modulation signal, and then generating a duty cycle reference voltage based on the first duty cycle of the first pulse width modulation signal, wherein the duty cycle reference voltage is the first a one-to-one mapping function of the duty cycle, and A fixed frequency pulse width modulation signal generation circuit, connected to the duty cycle conversion circuit, used to receive the duty cycle reference voltage, and then output the second pulse width modulation signal, wherein the second duty cycle of the second pulse width modulation signal is determined based on the duty cycle reference voltage, and the second duty cycle is a one-to-one mapping function of the duty cycle reference voltage. 12. The speed control circuit of the fan motor according to claim 10, wherein the fixed frequency PWM signal generation circuit comprises: a frequency controller, providing a frequency control signal for determining the fixed frequency of the second PWM signal, and A pulse width modulation signal generator, connected to the duty cycle conversion circuit and the frequency controller, generates the second pulse width modulation signal in response to the duty cycle reference voltage and the frequency control signal.

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