CN1567584A - Semiconductor package with conductive bumps implanted on chip and method for manufacturing same - Google Patents

Abstract

A semiconductor package with conductive lugs on chip is prepared as forming multiple conductive lugs on welding pad on active surface of chip, wrapping chip and conductive lugs by a package colloid and exposing end of conductive lugs out of package colloid. Then, a plurality of conductive traces are formed on the packaging colloid and are electrically connected to the exposed end parts of the conductive bumps. And laying a solder mask layer on the conductive trace, wherein the solder mask layer has multiple openings to expose the predetermined portion of the conductive trace, so as to be soldered with the solder balls. The semiconductor package utilizes the conductive bumps to highlight the positions of the pads on the chip, so that the conductive traces are electrically connected to the pads by the conductive bumps, thereby ensuring the good rate and reliability of the finished product.

Description

Semiconductor package with conductive bumps implanted on chip and method for manufacturing same

technical field

The present invention relates to a semiconductor package and its manufacturing method, in particular to a semiconductor package that does not require a chip carrier, and a method for manufacturing the semiconductor package.

Background technique

A semiconductor package is a structure carrying at least one integrated circuit component such as a semiconductor chip, and the chip is usually covered and protected with an encapsulation resin. The size of the semiconductor package is often relatively light, thin and short, so a chip scale package (chip scale package, CSP) has been developed, which is characterized in that the CSP structure only has a size equal to or slightly larger than the chip size.

U.S. Patent Nos. 5,892,179, 6,103,552, 6,287,893, 6,350,668, and 6,433,427 are traditional CSP structures that directly form build-uplayers on chips without using chip carriers such as substrates or lead frames, and Use redistribution layer (RDL, redistribution layer) technology to redistribute the pads on the chip to the required position. As shown in Figure 5, this CSP structure has a plurality of build-up layers formed on the active surface (active surface) 100 of the chip 10, including: a dielectric layer (dielectric layer) 11, laid on the active surface 100 of the chip 10 And set a plurality of through holes 110, so that the pads 101 on the chip 10 are exposed through the through holes 110; and a plurality of conductive traces 12, formed on the dielectric layer 11 and electrically connected to the exposed on the chip 10 pad 101 . A solder mask layer (solder mask layer) 13 can be laid on the conductive trace 12, and a predetermined portion of the conductive trace 12 is exposed and soldered to the solder ball 14 by a plurality of openings 130 penetrating through the solder mask layer 13, The solder ball 14 serves as an input/output (I/O) terminal electrically connected to an external device (not shown). Therefore, the solder pad 101 connected thereto is redistributed to a position in contact with the solder ball 14 by using the conductive trace 12 , so that the solder pad 101 is electrically connected to the solder ball 14 through the conductive trace 12 . In other words, when the pads on the chip are arranged at the peripheral or arranged at uneven pitches, redistribution technology can be used to redistribute the pads at the periphery or at uneven pitches by means of conductive traces. Arranged in an array to a predetermined position for placing solder balls, so that the solder balls (the so-called "ball grid array") that are subsequently formed on the predetermined position are arranged in an array by conductive traces and pads. electrical connection.

However, the disadvantage of the above-mentioned CSP structure is that the application of rewiring technology or the conductive traces laid on the chip is often limited by the size of the chip or the area of the active surface, especially when the integration level of the chip is increased and the chip size is shrinking day by day. In some cases, the chip cannot even provide enough or more surface area to place a larger or larger number of solder balls for effective electrical connection with the outside world.

In view of this, another package structure of US Pat. No. 6,271,469 forms a build-up layer on a chip, which can provide sufficient or more surface area to carry more or more input/output terminals or solder balls. As shown in FIG. 6 , this packaging structure utilizes an encapsulant 15 to cover the non-active surface 102 and the side surface 103 of the chip 10 , so that the active surface 100 of the chip 10 is exposed and flush with the surface 150 of the encapsulant 15 . Then, lay a first dielectric layer 16 on the active surface 100 of the chip 10 and the surface 150 of the encapsulant 15, and use laser drilling (laser drilling) technology to open a plurality of through holes penetrating the first dielectric layer 16 160 , so as to expose the pads 101 on the chip 10 . Next, a plurality of conductive traces 12 (hereinafter referred to as “first conductive traces”) are formed on the first dielectric layer 16 , and the first conductive traces 12 are electrically connected to the exposed pads 101 . Then, a second dielectric layer 17 is laid on the first conductive trace 12, and a plurality of through holes 170 penetrating through the second dielectric layer 17 are opened, so as to expose the predetermined portion of the first conductive trace 12 through the through holes. part, and then form a plurality of second conductive traces 18 on the second dielectric layer 17, so that the second conductive traces 18 are electrically connected to the exposed parts of the first conductive traces 12. Finally, the solder repellent layer 13 is laid on the second conductive trace 18 , so that a predetermined portion of the second conductive trace 18 is exposed through the opening 130 of the solder repellent layer 13 and soldered to the solder ball 14 . Therefore, the surface 150 of the encapsulant 15 covering the chip 10 can provide a larger surface area than the active surface 100 of the chip 10 , so that more solder balls 14 can be placed for effective electrical connection with the outside.

However, the disadvantage of the above packaging structure is that when using laser drilling technology to open through holes through the first dielectric layer to expose the pads on the chip, the pads on the chip are covered by the first dielectric layer, so that the laser It is usually difficult to accurately identify the position of the pad, so that the opened through hole cannot be accurately matched to the position of the pad; since the pad on the chip cannot be fully exposed, it is difficult to ensure the electrical properties between the conductive trace and the pad The quality of the connection will damage the quality and reliability of the finished product. At the same time, laying the first dielectric layer on the chip and the packaging colloid and using laser drilling technology to open through holes will increase the cost and complexity of the process, and the first dielectric layer and the chip and the packaging colloid have different coefficients of thermal expansion ( CTE, coefficient of thermal expansion), so in a high temperature environment or thermal cycle (thermal cycle), the first dielectric layer and the chip and packaging colloid will produce different thermal stress (thermal stress), so that the interface (interface) between them. layer (delamination), thereby reducing the quality and reliability of finished products.

Therefore, how to provide a semiconductor package that can ensure the quality of the electrical connection between the conductive trace and the pad and improve the yield and reliability of the finished product is an important issue.

Contents of the invention

In order to overcome the above-mentioned shortcoming of the prior art, the object of the present invention is to provide a semiconductor package with conductive bumps planted on the chip and a method for making the same. The method of manufacture is to form a plurality of conductive bumps ( conductive bump) to highlight the position of the pad, so as to ensure the electrical connection quality between the conductive trace and the pad, and improve the yield and reliability of the finished product.

Another object of the present invention is to provide a semiconductor package with conductive bumps planted on the chip and its manufacturing method. It does not need to lay a dielectric layer on the chip and use laser technology to open through holes through the dielectric layer. The pad on the chip is exposed through the through hole, so the cost can be reduced and the process can be simplified.

Another object of the present invention is to provide a semiconductor package with conductive bumps planted on the chip and its manufacturing method. Delamination occurs between the dielectric layer and the chip and encapsulant due to the difference in coefficient of thermal expansion (CTE, coefficient of thermal expansion).

In order to achieve the above and other objects, a semiconductor package for implanting conductive bumps on a chip of the present invention includes: at least one chip having an active surface and an opposite non-active surface, and formed on the active surface A plurality of pads, and the non-active surface exposes the encapsulation gel; a plurality of conductive bumps are respectively formed on the pads of the chip, and the conductive bumps are selected from solder bumps, high-lead content solder bumps, gold A group consisting of solder bumps and gold plugs; an encapsulation compound, used to cover the chip and the conductive bump, and make the end of the conductive bump exposed to the encapsulation compound and a surface of the encapsulation compound flush; a plurality of first conductive traces, formed on the surface of the encapsulant and electrically connected to the exposed end of the conductive bump; a solder repellent layer, laid on the first conductive traces and provided with A plurality of openings expose predetermined portions of the first conductive trace through the openings; and a plurality of solder balls are respectively formed on the exposed portions of the first conductive trace.

The above-mentioned semiconductor package further includes: at least one dielectric layer and a plurality of second conductive traces formed on the dielectric layer, the dielectric layer and the second conductive traces are sandwiched between the first conductive trace and the rejecting Between the solder layers, the dielectric layer is laid on the first conductive trace and a plurality of through holes are opened, so that the predetermined part of the first conductive trace is exposed through the through holes, so as to be connected with the second conductive trace Wires are electrically connected, and the solder repellent layer is laid on the second conductive trace, and a predetermined part of the second conductive trace is exposed through its opening, so that the plurality of solder balls are respectively formed on the second conductive trace. on exposed portions of conductive traces.

The manufacturing method of the above-mentioned semiconductor package includes the following steps: preparing a wafer, which is composed of a plurality of chips, each chip has an active surface and an opposite non-active surface, and a plurality of welding pads are formed on the active surface; forming a plurality of conductive bumps on the bonding pads of each of the chips; cutting the wafer to form a plurality of isolated chips, each of which has a plurality of conductive bumps, wherein the conductive bumps are selected from solder bumps , a group consisting of high lead content solder bumps, gold solder bumps, and gold plugs; a carrier is provided to carry the plurality of chips, and each of the chips is connected to the carrier by its conductive bumps On a surface of a tool, wherein, the carrier is a film; forming an encapsulant on the surface of the carrier to cover the plurality of chips and conductive bumps; performing a grinding step to grind the encapsulant and the conductive bump The end of the conductive bump is flush with the surface, and the part of the encapsulant that covers the non-active surface of the chip is ground away to expose the non-active surface of the chip. removing the carrier, exposing the end of the conductive bump to the encapsulant and being flush with a surface of the encapsulant; forming a plurality of conductive traces on the surface of the encapsulant, and making the conductive traces Electrically connected to the exposed end of the conductive bump; laying a solder repellant layer on the conductive trace, and opening a plurality of openings through the solder repellent layer, so that the predetermined part of the conductive trace passes through the opening exposing; respectively forming a plurality of solder balls on the exposed parts of the conductive traces; and cutting the encapsulant to form a plurality of semiconductor packages with isolated chips.

The manufacturing method of the semiconductor package of the present invention can also be completed by the following steps: prepare a wafer, which is composed of a plurality of chips, each of which has an active surface and an opposite non-active surface, and forms a wafer on the active surface. A plurality of bonding pads; respectively forming a plurality of conductive bumps on the bonding pads of each of the chips; cutting the wafer to form a plurality of isolated chips, each of which has a plurality of conductive bumps, wherein the conductive bumps are selected A group consisting of self-solder bumps, high-lead content solder bumps, gold solder bumps, and gold plugs; a carrier is provided to carry the plurality of chips, and each of the chips is connected by its conductive bumps placing on a surface of the carrier, wherein the carrier is a film; forming an encapsulant on the surface of the carrier to cover the plurality of chips and conductive bumps; performing a grinding step to grind The packaging colloid is flush with the surface of the end of the conductive bump; the carrier is removed so that the end of the conductive bump exposes the packaging colloid and is flush with a surface of the packaging colloid; forming a plurality of first conductive strips A trace is placed on the surface of the encapsulant, and the first conductive trace is electrically connected to the exposed end of the conductive bump; at least one dielectric layer is laid on the first conductive trace, and a plurality of penetrating the through hole of the dielectric layer, exposing a predetermined part of the first conductive trace through the through hole; forming a plurality of second conductive traces on the dielectric layer, and making the second conductive trace electrically Connecting to the exposed part of the first conductive trace; laying a solder repellant layer on the second conductive trace, and opening a plurality of openings through the solder repellent layer, so that the predetermined part of the second conductive trace can be borrowed The opening is exposed; forming a plurality of solder balls on the exposed portion of the second conductive trace; and cutting the encapsulant to form a plurality of semiconductor packages with separate chips.

The above-mentioned semiconductor package is first planted with a plurality of conductive bumps on the pads of the chip, and then wraps the chip with an encapsulant to expose the ends of the conductive bumps to the exposed encapsulant, so that subsequent build-up layers can be formed on the exposed on the end.

To sum up, the advantage of this structure is that the exposed end of the conductive bump can highlight the position of the pad on the chip, making it easy to identify, so that the conductive traces formed on the encapsulant subsequently can pass through the conductive bump. Good electrical connection to the pads, thereby improving the yield and reliability of finished products. In the prior art, it is necessary to form a dielectric layer on the chip and the encapsulant first, and then use laser drilling technology to open a plurality of through holes through the dielectric layer, so as to expose the pads on the chip through the through holes. Therefore, Compared with the prior art, the semiconductor package of the present invention does not need to use dielectric layer and laser drilling technology, so the cost can be reduced and the process can be simplified, and the pads on the chip will not be covered by the dielectric layer, which can avoid Because it is difficult for the laser to accurately identify the position of the solder pad, the solder pad cannot be exposed accurately or completely, which affects the quality of the electrical connection between the solder pad and the conductive trace, and there is no need to lay a dielectric layer on the chip and the packaging compound. It can also overcome the disadvantages in the prior art that delamination is easily caused at the interface between the dielectric layer and the chip and the encapsulation colloid due to the difference in thermal expansion coefficient and thermal stress generated therebetween.

Description of drawings

1 is a cross-sectional view of a semiconductor package according to Embodiment 1 of the present invention;

2A to 2H are schematic diagrams of manufacturing process steps of the semiconductor package of FIG. 1;

3 is a cross-sectional view of a semiconductor package according to Embodiment 2 of the present invention;

4 is a cross-sectional view of a semiconductor package according to Embodiment 3 of the present invention;

5 is a cross-sectional view of a conventional semiconductor package; and

FIG. 6 is a cross-sectional view of another conventional semiconductor package.

Detailed ways

Embodiments of the semiconductor package and its manufacturing method of the present invention will be described in detail below with reference to FIG. 1 , FIG. 2A to FIG. 2H , FIG. 3 and FIG. 4 .

Example 1

As shown in FIG. 1 , the semiconductor package of the present invention includes: at least one chip 20 having an active surface 200 and an opposite non-active surface 201, and a plurality of solder pads 202 are formed on the active surface 200; Conductive bumps 21 are respectively formed on the pads 202 of the chip 20; an encapsulant 22 is used to cover the chip 20 and the conductive bumps 21, and the end 210 of the conductive bump 21 is exposed to the encapsulant 22; A conductive trace 23 is formed on the encapsulant 22 and electrically connected to the exposed end 210 of the conductive bump 21; a solder repellent layer 24 is laid on the conductive trace 23 and has a plurality of openings 240, so that A predetermined portion of the conductive trace 23 is exposed through the opening 240 ; and a plurality of solder balls 25 are respectively formed on the exposed portion of the conductive trace 23 .

The above-mentioned semiconductor package can be manufactured according to the process steps shown in FIGS. 2A-2H .

First, as shown in Figure 2A, a wafer 2 is prepared, which is composed of a plurality of chips 20, each chip 20 has an active surface 200 and a relative non-active surface 201, and is formed on the active surface 200 of each chip 20. There are a plurality of pads 202 . Next, a bumping or stud bumping step is carried out to form a conductive bump 21 on each pad 202 of the chip 20, the conductive bump 21 can be a solder bump (solder bump), High lead solder bump, gold bump, or gold stud bump, etc.

Next, as shown in FIG. 2B , a singulation operation is performed, and the wafer 2 is diced to form a plurality of isolated chips 20 , and each chip 20 has a plurality of conductive bumps 21 .

As shown in FIG. 2C, a carrier 26, such as a film (tape), is provided to carry the plurality of chips 20. A plurality of packaging units 261 can be defined on a surface 260 of the carrier 26, so that at least one The chip 20 is connected to each package unit 261 by its conductive bump 21 .

Then, perform a molding (molding) process, utilize an existing resin material (such as epoxy resin etc.) 20 and conductive bumps 21.

As shown in FIG. 2D , the carrier 26 is removed or peeled off from the encapsulant 22 , so that the end portion 210 of the conductive bump 21 contacting the carrier 26 exposes the encapsulant 22 and is roughly in line with the encapsulant 22 . One surface 220 is flush.

At the same time, as shown in FIG. 2E , a grinding (grinding, such as mechanical grinding) step can be optionally performed to grind the surface 220 of the encapsulant 22 that is substantially flush with the end 210 of the conductive bump 21, so that the conductive bump can be exposed. The end 210 of the block 21, and ensure that the end 210 is indeed flush with the surface 220 of the encapsulant 22 and the planarity of the surface 220, so that subsequent processes can be carried out so that the end 210 of the exposed conductive bump 21 The surface 220 of the encapsulant 22 also provides more surface area (compared with the active surface 200 of the chip 20) for subsequent formation of a build-up layer and a greater number of I/Os ( input/output, I/O) terminal (not shown).

Next, as shown in FIG. 2F , a plurality of conductive traces 23 are formed on the surface 220 of the encapsulant 22 by using existing technologies such as photolithography, and each conductive trace 23 is connected to at least one conductive bump 21. Therefore, the pads 202 on the chip 20 can use the conductive bumps 21 and the conductive traces 23 to redistribute (redistribution) to desired positions, for example, to be connected to subsequent input/output terminals (not shown in the figure). ) position for electrical connection; the conductive trace 23 is made of a conductive material such as copper, aluminum, or an alloy thereof.

As shown in FIG. 2G, after forming the conductive trace 23 on the encapsulant 22, lay a solder repellant layer 24 on the conductive trace 23, and open a plurality of openings 240 through the solder repellent layer 24, so that the conductive trace A predetermined portion of the wire 23 is exposed through the opening 240 , and the exposed portion of the conductive trace 23 may be a terminal.

Then, a conventional screen printing (screen printing) operation is performed to form a solder ball 25 on the exposed portion (terminal) of each conductive trace 23, and this solder ball 25 serves as the input/output terminal of the semiconductor package, so that The chip 20 is electrically connected with an external device (not shown in the figure, such as a printed circuit board, etc.).

Finally, as shown in FIG. 2H , a cutting operation is performed to cut the encapsulant 22 to form a plurality of semiconductor packages with separate chips 20 .

The above-mentioned semiconductor package is first planted with a plurality of conductive bumps on the pads of the chip, and then uses an encapsulant to cover the chip, and the end of the conductive bump is exposed to the encapsulant, so that the subsequent build-up layer can be formed on the on the exposed end. The advantage of this structure is that the exposed end of the conductive bump can highlight the position of the solder pad on the chip, making it easy to identify, so that the conductive traces formed on the encapsulant later can be electrically connected well by the conductive bump to the pad, thereby improving the yield and reliability of the finished product. In the prior art, it is necessary to first form a dielectric layer on the chip and the encapsulation compound, and then use laser drilling technology to open a plurality of through holes through the dielectric layer, so as to expose the pads on the chip through the through holes. Compared with the prior art, the semiconductor package of the present invention does not need to use dielectric layer and laser drilling technology, so the cost can be reduced and the process can be simplified, and the welding pad on the chip will not be covered by the dielectric layer, thus avoiding the It is difficult for the laser to accurately identify the position of the solder pad, so that the solder pad cannot be exposed accurately or completely, which affects the quality of the electrical connection between the solder pad and the conductive trace, and there is no need to lay a dielectric layer on the chip and the packaging compound. It can overcome the disadvantages in the prior art that delamination is easily caused at the interface between the dielectric layer and the chip and the encapsulation compound due to the difference in coefficient of thermal expansion (CTE, coefficient of thermal expansion) and thermal stress generated.

Example 2

FIG. 3 shows a semiconductor package of Embodiment 2 of the present invention. As shown in the figure, the structure of the semiconductor package is roughly the same as that of the semiconductor package described in Embodiment 1 above, the difference is that when performing the grinding step shown in FIG. The portion covering the non-active surface 201 of the chip 20 exposes the non-active surface 201 of the chip 20 . In addition to the functions achieved by the semiconductor package of the first embodiment, the exposed inactive surface 201 helps to dissipate the heat generated by the chip 20 during operation to the outside or the atmosphere, thereby improving the heat dissipation efficiency of the package.

Example 3

FIG. 4 shows a semiconductor package of Embodiment 3 of the present invention. As shown in the figure, the structure of the semiconductor package is roughly the same as that of the semiconductor package described in Embodiment 1 above, the difference is that conductive traces 23 (hereinafter referred to as "first conductive traces") are formed on the encapsulant 22 Afterwards, at least one dielectric layer 27 is first laid on the first conductive trace 23, and a plurality of through holes (via) 270 penetrating the dielectric layer 27 are opened, so that a predetermined part of the first conductive trace 23 can pass through the first conductive trace 23. Holes 270 are exposed. Next, a plurality of second conductive traces 28 are formed on the dielectric layer 27, the dielectric layer and the second conductive traces are sandwiched between the first conductive traces and the solder repellent layer, and each second The conductive trace 28 is electrically connected to the exposed portion of the at least one first conductive trace 23 .

Then, a solder repellent layer 24 is laid on the second conductive trace 28, and a plurality of openings 240 penetrating through the solder repellent layer 24 are opened, so that a predetermined part of the second conductive trace 28 is exposed through the opening 240. The exposed portion of the second conductive trace 28 may be a terminal. Then, carry out existing screen printing operation, so that form a solder ball 25 on the exposed part (terminus) of each second conductive trace 28, this solder ball 25 is used as the input/output terminal of semiconductor package and external device (not marked in the figure) form an electrical connection relationship.

In addition to the effects achieved by the semiconductor package of Embodiment 1 above, the arrangement of the dielectric layer 27 and the second conductive trace 28 can increase the number of build-up layers on the chip 20, thereby improving the flexibility of the layout of the conductive trace in the package. , so that the chip 20 can be more effectively electrically connected to the solder balls 25 and external devices for operation.

Claims (10)

1. a semiconductor package part that plants conductive projection on chip is characterized in that, this semiconductor package part comprises:

At least one chip has an action face and a relative non-action face, and forms a plurality of weld pads on this action face;

A plurality of conductive projections are formed at respectively on the weld pad of this chip;

One packing colloid, in order to coating this chip and conductive projection, and make the end of this conductive projection expose outside this packing colloid and with a flush of this packing colloid;

Many first conductive traces are formed at the surface of this packing colloid, and are electrically connected to the end of exposing of this conductive projection;

One refuses welding flux layer, is laid on this first conductive trace and offers a plurality of perforates, makes the predetermined portions of this first conductive trace borrow this perforate to expose; And

A plurality of soldered balls are formed at respectively on the exposed parts of this first conductive trace.

2. semiconductor package part as claimed in claim 1, it is characterized in that, this semiconductor package part also comprises: at least one dielectric layer and many second conductive traces that are formed on this dielectric layer, this dielectric layer and second conductive trace are folded in this first conductive trace and refuse between the welding flux layer, make this dielectric layer be laid on this first conductive trace and offer many perforations, make the predetermined portions of this first conductive trace borrow this perforation to expose, thereby electrically connect with this second conductive trace, and make this refuse welding flux layer to be laid on this second conductive trace, and borrow its perforate to expose outside the predetermined portions of this second conductive trace, these a plurality of soldered balls are formed at respectively on the exposed parts of this second conductive trace.

3. semiconductor package part as claimed in claim 1 or 2 is characterized in that, the non-action face of this chip exposes outside this packing colloid.

4. semiconductor package part as claimed in claim 1 or 2 is characterized in that, this conductive projection is selected from solder bump, high lead content solder bump, golden welding block, reaches the cohort that golden bolt piece is formed.

5. a method for making that plants the semiconductor package part of conductive projection on chip is characterized in that, this method for making comprises the following steps:

Prepare a wafer, be made of a plurality of chips, respectively this chip has an action face and a relative non-action face, and is formed with a plurality of weld pads on this action face;

Form a plurality of conductive projections respectively on the weld pad of this chip respectively;

Cut this wafer with form a plurality of lists from chip, respectively this chip has a plurality of conductive projections;

One carrier is provided,, and this chip is connect by means of its conductive projection put on a surface of this carrier in order to carrying this a plurality of chips;

Form a packing colloid on the surface of this carrier, in order to coat this a plurality of chips and conductive projection;

Remove this carrier, make the end of this conductive projection expose outside this packing colloid and with a flush of this packing colloid;

Form many conductive traces on the surface of this packing colloid, and make this conductive trace be electrically connected to the end of exposing of this conductive projection;

Lay one and refuse welding flux layer on this conductive trace, and offer a plurality of perforates that this refuses welding flux layer that run through, make the predetermined portions of this conductive trace borrow this perforate to expose;

Form a plurality of soldered balls respectively on the exposed parts of this conductive trace; And

Cut this packing colloid, with form many have single from the semiconductor package part of chip.

6. a method for making that plants the semiconductor package part of conductive projection on chip is characterized in that, this method for making comprises the following steps:

Prepare a wafer, be made of a plurality of chips, respectively this chip has an action face and a relative non-action face, and is formed with a plurality of weld pads on this action face;

Form a plurality of conductive projections respectively on the weld pad of this chip respectively;

Cut this wafer with form a plurality of lists from chip, respectively this chip has a plurality of conductive projections;

One carrier is provided,, and this chip is connect by means of its conductive projection put on a surface of this carrier in order to carrying this a plurality of chips;

Form a packing colloid on the surface of this carrier, in order to coat this a plurality of chips and conductive projection;

Remove this carrier, make the end of this conductive projection expose outside this packing colloid and with a flush of this packing colloid;

Form many first conductive traces on the surface of this packing colloid, and make this first conductive trace be electrically connected to the end of exposing of this conductive projection;

Lay at least one dielectric layer on this first conductive trace, and offer a plurality of perforations that run through this dielectric layer, make the predetermined portions of this first conductive trace borrow this perforation to expose;

Form many second conductive traces on this dielectric layer, and make this second conductive trace be electrically connected to the exposed parts of this first conductive trace;

Lay one and refuse welding flux layer on this second conductive trace, and offer a plurality of perforates that this refuses welding flux layer that run through, make the predetermined portions of this second conductive trace borrow this perforate to expose;

Form a plurality of soldered balls respectively on the exposed parts of this second conductive trace; And

Cut this packing colloid, form many have single from the semiconductor package part of chip.

7. as claim 5 or 6 described method for makings, it is characterized in that this method for making also comprises: carry out a grinding steps to grind the surface that this packing colloid flushes with the conductive projection end.

8. as claim 5 or 6 described method for makings, it is characterized in that, this method for making also comprises: carry out a grinding steps to grind the surface that this packing colloid flushes with the conductive projection end, and the worn packing colloid part that covers the non-action face of this chip, to expose outside the non-action face of this chip.

9. as claim 5 or 6 described method for makings, it is characterized in that before forming this first conductive trace, this conductive projection is to be selected from solder bump, high lead content solder bump, golden welding block, and the cohort formed of golden bolt piece.

10. as claim 5 or 6 described method for makings, it is characterized in that this carrier is a film.

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