CN1564125A - Array type reconstructural DSP engine chip structure based on CORDIC unit - Google Patents

Abstract

Interconnection bus including longitudinal interconnection bus and transverse interconnection bus interconnected through reconfigurable switch network are setup between reconfigurable processing units arranged in array. Reconfigurable processing units are connected to each other longitudinally through basic unit data lines, which are connected to transverse interconnection bus through reconfigurable switch network. In transverse adjacent reconfigurable processing units at same stage of pipeline, their adders, shifters, accumulators, and register are connected through interconnection lines containing control switch. Reconfigurable processing unit itself of using COROIC algorithm possesses high reconfigurability, providing features of realizing wide used DSP algorithms, simple structure and rules, easy of modularized. Thus, the reconfigurable processing unit is suitable for being as core unit in reconfigurable chip.

Description

An array reconfigurable DSP engine chip structure based on CORDIC unit

Technical field:

The invention relates to a reconfigurable (hardware programmable) array chip internal structure composed of coarse-grained basic units with a CORDIC algorithm as the core, and the structure is mainly used in the DSP field. Through the configuration of the hardware reconfigurable resources in the chip, it can efficiently execute the core links in most DSP algorithms, and can be used as the acceleration engine in the DSP system.

Background technique:

CORDIC (COordinate Rotation DIgital Computing), also known as coordinate rotation digital calculation method, is an iterative method for calculating generalized vector rotation. By setting the few parameters in the CORDIC unit, it can implement a variety of basic functions and operations with simple "shift-add" iterations, such as: trigonometric functions, inverse trigonometric functions, hyperbolic functions, inverse hyperbolic functions Functions, logarithmic operations, exponential operations, square root operations, multiplication operations, and division operations, these characteristics indicate that the CORDIC algorithm itself has good reconfigurability (hardware programmability). Many of these functions and operations are not easily realized by other methods, and are often encountered in some DSP algorithms. Previous reconfigurable devices are divided into two categories: fine-grained and coarse-grained. Our summary of the existing coarse-grained array chips found that their data word width is fixed, and they can only adapt to a class of applications with the same data word width. We believe that if the chip can have the function of reconfigurable data word width, the adaptability of the chip will be greatly enhanced, the waste of chip resources will be less, the performance of the functional modules will be higher, the power consumption will be lower, and the configuration data will be relatively low. Much less, in favor of dynamic applications.

Invention content:

In order to solve the problem of fixed data word width of existing coarse-grained DSP array chips, an array type reconfigurable DSP chip which can change the data word width by reconfiguring the basic operation components of adjacent units is provided. The technical scheme of the present invention is as follows: an array type reconfigurable DSP engine chip structure based on CORDIC unit, interconnection bus 2 is arranged between several reconfigurable processing units 1 arranged in an array, vertical interconnection bus 2 -1 and the horizontal interconnection bus 2-2 are connected to each other through the reconfigurable switch network 3, and each adjacent reconfigurable processing unit 1 in the same longitudinal arrangement direction is vertically connected through the basic unit data line 4, basically The unit data line 4 is connected to the horizontal interconnection bus 2-2 through the reconfigurable switch network 3. The reconfigurable processing unit 1 is a several-stage pipeline structure of the cordic algorithm, and the horizontally adjacent reconfigurable processing unit 1 is the same The adder and the adder at the corresponding position, the shifter and the shifter at the corresponding position, the accumulator and the accumulator at the corresponding position, and the register and the register at the corresponding position in the pipeline are respectively controlled by The interconnection lines 7 of the switches 5 are connected. The DSP engine chip of the present invention, in order to realize the reconfigurability between adjacent units, mainly establishes reconfigurable components between two arithmetic components such as shifters, adders, accumulators, and registers that are at the same pipeline level in adjacent units. Reconstructing the path, when the path is connected, two shifters, adders, accumulators, and registers can form a functional module with twice the original data word width. We have added reconfigurable functions to the shifters, adders, accumulators, and registers in the unit, so that the shifters, adders, and registers of the same level of pipeline between two horizontally adjacent units can be connected through configuration. Become the corresponding functional unit whose word width is 2 times of the original. This reconfigurable function allows us to combine 4/9/16 8-bit CORDIC units adjacent to each other in the layout to form a 16/24/32-bit CORDIC unit. Since the data word width of the shifter, adder, register and accumulator of the DSP engine chip of the present invention can be changed through reconfiguration, the versatility and adaptability of the chip are greatly enhanced, the waste of chip resources is small, and the function The high performance and low power consumption of the module facilitates dynamic applications. The reconfigurable processing unit 1 using the COROIC algorithm itself has strong reconfigurability, can efficiently implement a wide range of DSP algorithms, and has a simple and regular structure, easy to achieve modularization, and is very suitable as the core of reconfigurable chips unit. The invention is novel in design, reliable in operation and has great popularization value.

Description of drawings:

Fig. 1 is a schematic structural diagram of the present invention, Fig. 2 is a schematic structural diagram of a reconfigurable switch network 3 in Embodiment 2 of the present invention, Fig. 3 is a schematic structural diagram of a reconfigurable processing unit 1 in Embodiment 1, and Fig. 4 is an embodiment A schematic diagram of the reconfiguration of the shifter, FIG. 5 is a schematic diagram of the reconfiguration of the adder, and FIG. 6 is a schematic diagram of the connection structure of the first-stage pipeline in the adjacent reconfigurable processing unit 1 .

Detailed ways:

Specific Embodiment 1: The present embodiment will be specifically described below with reference to FIG. 1 , FIG. 3 to FIG. 6 . An interconnection bus 2 is arranged between several reconfigurable processing units 1 arranged in an array, and the vertical interconnection bus 2-1 and the horizontal interconnection bus 2-2 are connected to each other through a reconfigurable switch network 3. Each adjacent reconfigurable processing unit 1 in the vertical arrangement direction is vertically connected through the basic unit data line 4, and the basic unit data line 4 is connected with the horizontal interconnection bus 2-2 through the reconfigurable switch network 3, The reconfigurable processing unit 1 is a several-stage pipeline structure of the cordic algorithm, the adder and the adder in the corresponding position in the same pipeline of the horizontally adjacent reconfigurable processing unit 1, the shifter and the shifter in the corresponding position The bit register, the accumulator and the accumulator at the corresponding position, and the register and the register at the corresponding position are respectively connected through the interconnection line 7 including the control switch 5 .

As shown in FIG. 4 , the shifters 1-1-1 and 1-1-2 belonging to two adjacent reconfigurable processing units 1 are both right-shifted three-bit shifters. When a longer data word width is desired, the control switch 5 is turned on through an instruction, and the interconnection line 7 becomes a path, so that the shifter 1-1-1 and the shifter 1-1-2 are synthesized into a data word width For the original 2x shifter. The adder can also be reconfigured in the same way to increase the data word width. As shown in FIG. 5 , the carry-ahead adder 1-2-1 and the carry-ahead adder 1-2-2 belonging to the same position in two adjacent reconfigurable processing units 1 are connected by a control switch 5 Through the pass, you can get a look-ahead carry adder whose data word width is twice the original, so as to realize the reconstruction function. Accumulators and registers can also be reconstructed in the same way. The control switch 5 is realized by using a field effect transistor. Figure 6 shows a schematic diagram of the connection structure of shifters, adders, registers and accumulators at the same position in the first-stage pipeline in two horizontally adjacent reconfigurable processing units 1, adders 1-2-1 and Between Adder 1-2-2, Between Adder 1-3-1 and Adder 1-3-2, Between Adder 1-4-1 and Adder 1-4-2, Register 1-5 Between -1 and register 1-5-2, between register 1-6-1 and register 1-6-2, between register 1-7-1 and register 1-7-2, shifter 1-8 Between -1 and shifter 1-8-2, between shifter 1-9-1 and shifter 1-9-2, between flag register 1-10-1 and flag register 1-10-2 All of them are connected through the interconnection line 7 including the switch 5 .

As shown in Figure 3 and Figure 6, the working process of the chip is mainly divided into two stages: the reconstruction stage and the working stage. In the reconfiguration phase, the part with reconfigurable functions in the above structure, that is, the preconfigurable storage unit represented by the circle in the figure, is written with preset configuration data. At this time, the function of the chip has been fixed, which is equivalent to a hardware circuit that can only complete a certain function, and can load the processed data at any time to start working. After entering the working stage, a set of data enters the processing engine from the top of the unit at each clock beat, and runs down step by step in a pipelined manner. After reaching the end of the algorithm, it is connected to a certain chip port through the interconnection bus.

The following takes the calculation of the sine and cosine of a certain angle α as an example to illustrate the internal working process of the 8-bit CORDIC unit. The unit entrance has three data inputs (X ₀ , Y ₀ , Z ₀ ), the initial value is (1, 0, α), and the shift sequence of the first ten stages is (0, 0, 1, 2, 3, 4, 5, 6, 7, 8), the shift sequence (2, 5, 8) of the 3-stage modulo correction pipeline. After X ₀ enters the first-level pipeline, it is divided into two paths, one path is directly used as the addend of the first adder, and the other path is used as the addend of the second adder after being "shifted right by 0 bits"; Y ₀ enters After the first level of pipeline, it is divided into three ways, one way is directly used as the addend of the second adder, the second way is used as the addend of the first adder after "shifting right by 0", and the third way is sent into Symbol judging module; Z ₀ is divided into two paths after entering the first stage, one path is sent to the adder and ±arctan(2 ^-0 ) for summing, and the other path enters the symbol judging module. The sign judging module generates a sign bit according to the positive or negative of Z _i and sends it to the three-way adder to control them to make sum or difference. The results generated by the three adders are stored in the registers of the pipeline when the next clock arrives, for use in the second pipeline operation. By analogy, up to the tenth stage, the difference in operation between stages is the number of shifts (as described by the shift sequence). The pipeline from the eleventh level to the thirteenth level is a modulo correction operation. In this operation, X ₀ is divided into two ways, one way is directly used as the summand of the first adder, and the other way is used as the addend of the adder after being shifted to the right. Addend; the modulo correction operation of Y ₀ and X ₀ is the same; Z ₀ has no operation, only three-level register. The shift sequence of the three-level modulo correction operation is (2, 5, 8), and the addition and subtraction operations of the adders at each level are controlled by a preset storage bit. Finally, the data in the thirteenth-stage pipeline register is the result of this calculation: X ₁₃ =Cosα, Y ₁₃ =Sinα, Z ₁₃ =0. The two sine and cosine values can be output through the interconnection bus or passed to other functional modules for use.

Specific Embodiment 2: The present embodiment will be specifically described below with reference to FIG. 1 and FIG. 2 . The difference between this embodiment and Embodiment 1 is: the interconnection bus 2 is a 64-bit interconnection bus, the reconfigurable switch network 3 is composed of several switch tubes 3-1, and the switch tubes 3-1 are arranged vertically At the intersection of the 64 interconnection buses 2-1 and the 64 horizontal interconnection buses 2-2, the two main working poles of the switch tube 3-1 are connected to the longitudinal interconnection bus 2-1 and the horizontal interconnection bus 2-1 respectively. Connected to the bus 2-2, the control pole of the switch tube 3-1 is connected to the preset memory 3-2 for controlling the switch tube. When this embodiment is working, the configuration of the chip is determined by setting whether the switch tube 3-1 is connected or turned off in the preset memory 3-2 through programming. The switching tube 3-1 can be either a CMOS tube or an NMOS tube.

Claims (2)

1. An array-type reconfigurable DSP engine chip structure based on CORDIC units, an interconnection bus (2) is arranged between several reconfigurable processing units (1) arranged in an array, and the longitudinal interconnection bus (2 -1) The horizontal interconnection bus (2-2) is connected to each other through a reconfigurable switch network (3), and each adjacent reconfigurable processing unit (1) in the same longitudinal arrangement direction is connected through a basic unit data line (4) vertically connected, the basic unit data line (4) is connected with the horizontal interconnection bus (2-2) through a reconfigurable switch network (3), which is characterized in that the reconfigurable processing unit (1) is a cordic The pipeline structure of several stages of the algorithm, the adder and the adder in the corresponding position, the shifter and the shifter in the corresponding position, the accumulator and the The accumulator at the corresponding position, the register and the register at the corresponding position are respectively connected through an interconnection line (7) including a control switch (5). 2, a kind of array type reconfigurable DSP engine chip structure based on CORDIC unit according to claim 1, it is characterized in that described interconnection bus (2) is a 64-bit interconnection bus, reconfigurable switch network ( 3) It is composed of several switching tubes (3-1), and the switching tubes (3-1) are arranged at the intersection of 64 interconnecting buses (2-1) in the vertical direction and 64 interconnecting buses (2-2) in the horizontal direction point, the two main working poles of the switch tube (3-1) are respectively connected to the longitudinal interconnection bus (2-1) and the horizontal interconnection bus (2-2), and the control pole of the switch tube (3-1) Connect the preset memory (3-2) of the control switch tube.

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