CN1558320A - Multifunctional input and output system - Google Patents

Abstract

The present invention relates to an input/output system, and more particularly, to a multi-functional input/output system, which comprises a plurality of input/output devices, each of the input/output devices having a plurality of data pins and address pins; a control chip, which comprises a plurality of controllers corresponding to the input and output devices, a multiplexer and an arbiter, and is provided with a plurality of address data pins; and an address data bus including a plurality of signal lines, each signal line corresponding to and connected to each address data pin of the control chip; the data pins and address pins of each I/O chip can be connected to appropriate signal lines in the address data bus respectively, and can be used for data transmission with an application system through the matching selection of the multiplexer and a signal corresponding device.

Description

Multifunctional input and output system

technical field

The invention relates to an input and output system, in particular to a multifunctional input and output system.

Background technique

With the high development of information technology, the functions of information products are becoming more and more powerful, their operation is more and more convenient, and the application level is also becoming wider and wider. As a result, many audio-visual equipment, communication equipment, and even household appliances have more or less added some interfaces for information processing or information exchange. In order to facilitate information transfer and processing between various devices and equipment, each device or equipment is often equipped with various input and output devices for data transfer or transmission.

At present, the most commonly used method in the industry is to use the memory card to store data. The memory card can be taken out at any time and used for information exchange with other devices or information equipment, or the data in the memory card can be stored in the computer for further processing. calculation or processing.

Due to the wide variety of memory cards, the specifications and transmission interfaces of various memory cards are also different. In order to enable different memory cards to be used on the same information device, an appropriate read-write device must be installed on the information device to link and coexist. Retrieve data from various memory cards. Some manufacturers integrate the control chips of different memory cards on a circuit board to make it a multi-function card reader. The circuit structure is shown in Figure 1.

Its main structure is to include: a first slot 151, for inserting a first memory card 141; a second slot 153, for inserting a second memory card 143; a third slot 155, It is used to insert a third memory card 145; and a control chip 12, which can be connected to each memory card through each slot; and the computer 13 can use the control chip to access each memory card.

Wherein, the first slot 151 is provided with a data contact D[i:0] and an address contact A[p:0] in accordance with the specifications of the first memory card 141, which can be connected to the data pin dat of the first memory card 141 respectively. [i:0] and address pin add[p:0] are correspondingly connected, each data contact and address contact are respectively connected by the first data bus 161 composed of i+1 signal lines and p+1 signal lines The first address bus 181 composed of wires is connected to the first controller 121 in the control chip 12; the second slot 153 is provided with a data contact D[j:0] and an address contact A[q:0], The second data bus 163 comprising j+1 signal lines and the second address bus 183 comprising p+1 signal lines are respectively connected to the second controller 123 in the control chip 12, each data contact and address The contacts can be respectively connected to the data pin dat[j:0] and the address pin add[q:0] of the second memory card 143 correspondingly; and the third slot 155 is provided with a data contact D[k:0] and the address contact A[r:0] are respectively connected to the third data bus 165 including k+1 signal lines and the third address bus 185 including r+1 signal lines to the first in the control chip 12 For the three controllers 125, each data contact and address contact can be respectively connected to the data pin dat[j:0] and the address pin add[q:0] of the third memory card 143 correspondingly.

An arbiter 129 is further provided in the control chip 12 and connected to the first controller 121 , the second controller 123 and the third controller 125 respectively. In addition, each memory card is provided with corresponding enabling pins CE1, CE2 and CE3, which are respectively connected to the control chip 12 through the first enabling signal line 191, the second enabling signal line 193 and the third enabling signal line 195. Arbitrator 129. The arbiter 129 can enable (enable) the memory card it wants to access and its corresponding controller through the corresponding enable signal line according to the command of the computer 13, and simultaneously disable other memory cards and other controllers ( disable). In this way, the computer 13 can access memory cards of various specifications through the control chip 12 in the card reader.

Using the above technology, although the computer can achieve the purpose of accessing memory cards of various specifications, however, in order to connect with various memory cards correspondingly, the control chip 12 must be provided with a lot of pins to achieve the purpose. The more pins, the higher the manufacturing cost, and the control chip needs a larger area to accommodate so many pins. Moreover, a large number of signal lines connecting the pins of the control chip 12 and the contacts of the slots not only occupy a large amount of area on the circuit board, but also the arrangement and design of its wiring (layout) is also a major problem for practitioners.

Contents of the invention

In view of this, the main purpose of the present invention is to provide a multi-functional input and output system that can reduce the number of pins of the control chip, reduce the manufacturing cost and reduce the required area of the circuit.

The above object of the present invention is achieved by the following technical solutions.

Option One

A multifunctional input and output system is characterized in that it includes:

A plurality of input and output devices, each input and output device is respectively provided with a plurality of data pins and a plurality of address pins;

A control chip, including a plurality of controllers corresponding to each input and output device, a multiplexer and an arbiter, and having a plurality of address data pins; and

An address data bus, including a plurality of signal lines, respectively corresponding to and connected to each address data pin of the control chip;

Wherein, the data pins and address pins of each input and output device are respectively connected to appropriate signal lines in the address data bus, so as to achieve electrical connection with the control chip.

The feature of the multifunctional input and output system is that the multiplexer is also provided with a signal corresponding device.

The feature of the multifunctional input and output system is that the signal corresponding device is implemented in the form of a circuit.

The feature of the multifunctional input and output system is that the signal corresponding device is a memory storing a signal corresponding table.

Said multi-function input and output system is characterized in that: the memory is selected from one of flash memory, electronically erasable read-only memory and non-volatile memory.

Described multifunctional input-output system is characterized in that: each input-output device is selected as CF memory card, SM memory card, MS memory card, SD memory card, MMC memory card, NAND flash memory card, NOR flash memory respectively One of a card, a USB device, a parallel IDE device, a serial IDE device, a ROM, an erasable ROM, and a general-purpose input/output chip.

Option II

A multifunctional input and output system is characterized in that it includes:

A plurality of input and output devices, each input and output device is respectively provided with a plurality of data pins, a plurality of address pins and at least one control pin;

A control chip, including a plurality of controllers respectively corresponding to each input and output device, a multiplexer and an arbitrator, and having a plurality of address data control pins; and

An address data control bus, including a plurality of signal lines, respectively corresponding to and connected to each address data control pin of the control chip;

Wherein, the data pins, address pins and control pins of each input and output device are respectively connected to appropriate signal lines in the address data control bus, so as to achieve electrical connection with the control chip.

The feature of the multifunctional input and output system is that the multiplexer is also provided with a signal corresponding device.

The feature of the multifunctional input and output system is that the signal corresponding device is implemented in the form of a circuit.

Said multi-functional input and output system is characterized in that: the signal corresponding device is a memory storing a signal corresponding table.

Said multi-functional input and output system is characterized in that: the memory is selected from one of flash memory, electronically erasable read-only memory and non-volatile memory.

Described multifunctional input-output system is characterized in that: each input-output device is selected as CF memory card, SM memory card, MS memory card, SD memory card, MMC memory card, NAND flash memory card, NOR flash memory respectively One of a card, a USB device, a parallel IDE device, a serial IDE device, a ROM, an erasable ROM, and a general-purpose input/output chip.

The present invention provides a multi-functional input and output system, which mainly includes: a plurality of input and output devices, each input and output device is respectively provided with a plurality of data pins and a plurality of address pins; a control chip, including a plurality of A controller corresponding to each input and output device, a multiplexer and an arbitrator, and having a plurality of address data pins; and an address data bus, including a plurality of signal lines, respectively corresponding and connected Each address and data pin of the control chip; among them, the data pin and address pin of each input and output device are respectively connected to the appropriate signal line in the address data bus, so as to achieve electrical connection with the control chip, which can not only facilitate Provider wiring, and effectively reduce the area required for wiring.

In addition, a multifunctional input and output system provided by the present invention mainly includes: multiple input and output devices, each input and output device is respectively provided with multiple data pins, multiple address pins and at least one control pin Pin; a control chip, including a plurality of controllers corresponding to each input and output device, a multiplexer and an arbiter, and is provided with a plurality of address data control pins; and an address data control bus, Contains a plurality of signal lines, corresponding to and connected to each address data control pin of the control chip; wherein, the data pins, address pins and control pins of each input and output capacity are respectively connected to the address data control bus Appropriate signal lines are used to achieve electrical connection with the control chip, which not only facilitates the wiring of the industry, but also effectively reduces the area required for wiring.

The advantages of the present invention are:

1. By setting a multiplexer in the control chip, various input and output devices can be connected to the same group of pins of the control chip, which can reduce the number of pins of the control chip and reduce the production cost.

2. There is a signal corresponding device in the multiplexer, so that the pins of each input and output device can be connected to the pins of the control chip in the most suitable order, which can further reduce the area required by the circuit.

In order to have a further understanding and understanding of the features, structure and achieved effects of the present invention, a preferred embodiment and accompanying drawings will be described in detail below.

Description of drawings

FIG. 1 is a circuit block diagram of a conventional multi-function card reader.

FIG. 2 is a schematic block diagram of a preferred embodiment of the present invention.

FIG. 3 is a schematic block diagram of another embodiment of the present invention.

Detailed ways

First, please refer to FIG. 2 , which is a schematic block diagram of a preferred embodiment of the present invention. As shown in the figure, the multifunctional I/O system of the present invention mainly includes a plurality of I/O devices, a control chip 22 and an address data bus 26 . Taking the system of three input and output devices as an example, the multiple input and output devices include a first input and output device 241, a second input and output device 243 and a third input and output device 245, and each input and output device is respectively provided with a plurality of Data pins and multiple address pins. The first I/O device 241 is provided with a data pin dat[i:0] and an address pin add[p:0]; the second I/O device is provided with a data pin dat[j:0] and a bit The address pin add[q:0]; the third I/O device is provided with a data pin dat[k:0] and an address pin add[r:0].

The control chip 22 is provided with a first controller 221, a second controller 223 and a third controller 225 respectively corresponding to the first I/O device 241, the second I/O device 243 and the third I/O device 245, each controlling The device is connected to the address data pin ad[m:0] of the control chip 22 through a multiplexer 227, and the address data pin ad[m:0] is connected to the address data pin ad[m:0] through a m +1 address data bus 26 corresponding to the signal lines of each address data pin connects the data pins and address pins of each input and output device.

When the system operates, it uses an arbitrator 229 respectively connected to the multiplexer 227 and each controller to arbitrate, so as to determine whether the first controller 221, the second controller 223 or the third controller 225 passes through multiplexers in a time interval. The worker 227 obtains the right to use the address data pin ad[m:0] of the control chip 22. The arbiter 229 can also be connected to the first input and output via the enable pins CE1, CE2 and CE3 of the control chip 22 and the first enable signal line 291, the second enable signal line 293 and the third enable signal line 295 respectively. The device 241, the second input and output device 243 and the third input and output device 245 can enable (enable) the corresponding input and output devices at the same time when each controller obtains the right to use the address data pin, while the other input and output devices The device is disabled. In this way, the application system 23, such as a computer or other information devices, can access the specified input and output devices through the control chip 22. The control chip 22 only needs to set the maximum number of possible address data pins of an input and output device, which can greatly reduce the number of pins required by the control chip 22, reduce the area of the control chip 22 and save its manufacturing cost.

In the above-mentioned multi-functional input and output system, a signal corresponding device 28 can also be provided in the multiplexer 227 . The signal corresponding device 28 can pre-set each data pin and each address pin of each input and output device and the corresponding mode of each address data pin of the control chip 22, and each input and output device is then set in the signal corresponding device 28 Each data pin and each address pin are connected to corresponding signal lines in the address data bus 26 in a predetermined corresponding manner. That is to say, we can sequentially connect the data pin dat[i:0] and the address pin add[p:0] to the signal line AD[i in the address data bus 26, as shown in the first input and output device 241 +p+1:0]; or as the second input and output device 243, connect the data pin dat[j:0] and the address pin add[q:0] to the signal in the address data bus 26 in reverse order line AD[j+p+1:0]; or as the third input and output device 245, the address pin add[q:0] is sequentially connected to the address data pin AAD[r:0], and the data pin dat[k:0] is sequentially connected to the address data pin AD[r+k+1:0] and so on. The system can arrange the correspondence of its signals according to the spatial arrangement of each device or other requirements. In this way, not only the layout of the system can be simplified, but also the area required for wiring can be greatly reduced, which is in line with people's requirements for information products. Thin and short requirements.

The above-mentioned signal corresponding device 28 can be implemented in a circuit mode, and the corresponding mode of each signal is directly implemented in a multiplexer in a circuit switching mode. The signal corresponding device 28 can also be selected as flash memory (flash memory), electronically erasable read-only memory (electrically erasableprogrammable read-only memory; EEPROM) or non-volatile memory (non-volatile random access memory; NVRAM) and A signal correspondence table is stored in the memory, and the correspondence relationship between each address data pin and each pin of each input and output device can be obtained by using the signal correspondence table. In this embodiment, the signal correspondence table in the memory can be added, deleted or modified according to the requirements of the system, so that the system design has greater flexibility.

Finally, please refer to FIG. 3 , which is a schematic block diagram of another embodiment of the present invention. As shown in the figure, its main structure is roughly the same as that of the embodiment shown in FIG. [x:0], the control pin com[y:0] of the second I/O device 343 and the control pin com[z:0] of the third I/O device 345 . The control chip 32 is provided with a plurality of address data control pins add[m:0], and is connected to various input and output devices by an address data control bus 36 including a plurality of signal lines ADC[m:0].

In this embodiment, the signal corresponding device 38 can also include the corresponding relationship between the control pins of each input and output device and the address data control pins of the control chip 32, so that the overall wiring design of the system will have greater flexibility. .

The multi-functional input and output system of the present invention, no matter it is applied to the structure of the card reader or integrated into the computer motherboard, can exert its advantages of high wiring flexibility and system area saving. The system is applicable to various input and output devices, such as CF (Compact Flash) memory card, SM (Smart Media) memory card, MS (Memory Stick) memory card, SD (Secured Digital) memory card, MMC (MultiMedia Card) storage card, NAND flash memory card, NOR flash memory card, USB device, parallel (parallel) IDE device, serial (serial) IDE device, read-only memory (ROM), erasable read-only memory (EEPROM) and General-Purpose I/O and so on.

In summary, it should be known that the present invention relates to an input and output system, especially a multifunctional input and output system, which mainly uses a multiplexer to cooperate with a signal corresponding device, so that the input and output device and the control chip The connected lines can be freely allocated, effectively reducing the area required for wiring. Therefore, the present invention is full of novelty, progress, and can be used by industry, and it meets the requirements of the patent application. I submit an application for a patent for invention according to law, and I sincerely hope that the patent for this invention will be granted as soon as possible.

The above is only a preferred embodiment of the present invention, and is not used to limit the scope of the present invention, that is, all the shapes, structures, characteristics, spirits and methods described in the patent scope of the present invention are equal. Changes and modifications should be included in the scope of the patent application of the present invention.

Claims (12)

1. A multifunctional input and output system, characterized in that it includes: A plurality of input and output devices, each input and output device is respectively provided with a plurality of data pins and a plurality of address pins; A control chip, including a plurality of controllers corresponding to each input and output device, a multiplexer and an arbiter, and having a plurality of address data pins; and An address data bus, including a plurality of signal lines, respectively corresponding to and connected to each address data pin of the control chip; Wherein, the data pins and address pins of each input and output device are respectively connected to appropriate signal lines in the address data bus, so as to achieve electrical connection with the control chip. 2. The multifunctional input and output system according to claim 1, wherein the multiplexer is further provided with a signal corresponding device. 3. The multifunctional input and output system according to claim 2, wherein the signal corresponding device is implemented in the form of a circuit. 4. The multifunctional input and output system according to claim 2, wherein the signal corresponding device is a memory storing a signal corresponding table. 5. The multi-function input and output system according to claim 4, wherein the memory is one of a flash memory, an electronically erasable read-only memory, and a non-volatile memory. 6. The multifunctional input and output system according to claim 1, characterized in that: each input and output device is selected as CF memory card, SM memory card, MS memory card, SD memory card, MMC memory card, NAND flash memory card, NOR flash memory card, USB device, parallel IDE device, serial IDE device, read only memory, erasable read only memory and general input and output chip. 7. A multifunctional input and output system, characterized by comprising: A plurality of input and output devices, each input and output device is respectively provided with a plurality of data pins, a plurality of address pins and at least one control pin; A control chip, including a plurality of controllers respectively corresponding to each input and output device, a multiplexer and an arbitrator, and having a plurality of address data control pins; and An address data control bus, including a plurality of signal lines, respectively corresponding to and connected to each address data control pin of the control chip; Wherein, the data pins, address pins and control pins of each input and output device are respectively connected to appropriate signal lines in the address data control bus, so as to achieve electrical connection with the control chip. 8. The multifunctional input and output system according to claim 7, wherein the multiplexer is further provided with a signal corresponding device. 9. The multifunctional input and output system according to claim 8, wherein the signal corresponding device is implemented in the form of a circuit. 10. The multifunctional input and output system according to claim 8, wherein the signal corresponding device is a memory storing a signal corresponding table. 11. The multifunctional input and output system according to claim 10, wherein the memory is selected from one of flash memory, electronically erasable read-only memory and non-volatile memory. 12. The multifunctional input and output system according to claim 7, characterized in that: each input and output device is selected as CF memory card, SM memory card, MS memory card, SD memory card, MMC memory card, NAND flash memory card, NOR flash memory card, USB device, parallel IDE device, serial IDE device, read only memory, erasable read only memory and general input and output chip.

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