CN1549272A - Power-saving static memory control circuit - Google Patents

Abstract

The invention relates to a power-saving static memory control circuit, wherein an address comparator is used for comparing a current address signal and previous address data when a static memory is read, and if addresses represented by the address signal are the same, the buffered data are directly output from a buffer without enabling a memory unit, so that the purpose of saving power is achieved.

Description

Power saving static memory control circuit

technical field

The invention relates to a static memory control circuit, in particular to a power-saving static memory control circuit.

Background technique

Generally speaking, memory is mainly divided into two categories: static memory (SRAM) and dynamic memory (DRAM). Among them, under the same chip area, the capacity of the dynamic memory is more than four times that of the static memory, but in terms of speed, the static memory is more than four times faster than the dynamic memory. In addition, the price of static memory is much higher than that of dynamic memory, and its power consumption is also greater than that of dynamic memory. Therefore, in order to compromise the price and performance, in the design of the computer, a part of the static memory is often added between the central processing unit (CPU) and the dynamic memory as a cache memory (Cache) to provide a cache function.

FIG. 1 is a structural diagram of an existing static memory. Wherein, the address decoder 10 is used to read the data of the address line and perform address decoding, so as to output an address signal to select a specific memory segment of the memory unit 14 . The chip enable signal (-CS) is used to enable the memory unit 14, so that it can perform memory read and write actions on the selected specific memory segment. When the chip enable signal (-CS) is applied and the operation enable signal ( -OE) is also effected, then the memory unit 14 can be read, and the data stored in the specific memory segment is buffered by the buffer 18 and then output to the external circuit; and when the chip enable signal (-CS) is activated and the write enable signal (-WE) is also activated, the memory unit 14 can be written, so that the data input to the buffer 18 by the external circuit can be written into a specific memory segment. The aforementioned wafer enable signal, operation enable signal and write enable signal all use a low level trigger mode, that is, the low level is an active state, and the high level is an inactive state.

However, with the increasing popularity of portable devices recently, not only fast speed is required, but also power saving is required. Taking the operation of a general static memory as an example, in the standby state, the entire static memory only needs 2 microamperes, but in the operating state (when reading data or writing data, that is, the chip enable signal is low), the entire Static memory may require 20 milliamps, a ten thousand-fold difference in power consumption. In addition, the power consumption of the static memory is relatively large, so it is known that the power consumption of the static memory has a lot of room for improvement.

Contents of the invention

The object of the present invention is to provide a power-saving static memory control circuit, so as to reduce the power consumption when the static memory is read.

In order to achieve the above object, the present invention discloses a power-saving static memory control circuit, which controls the reading and writing of the memory by a chip enable signal, an operation enable signal and a write enable signal, wherein, when the chip enable signal and the operation enable signal are activated, the control circuit performs a read operation, when both the chip enable signal and the write enable signal are activated, the control circuit performs a write operation, and the control circuit includes: a memory unit for storing data ; The address decoder is used to decode the data of the address line to output the address signal to select a specific memory of the memory unit; the buffer is used to buffer the data to be accessed, so that the selected memory data will be read during the read operation Buffering and outputting, and when performing a write operation, buffering the input data and writing it into the selected memory; the address temporary register is used to store the current address signal generated by the address decoder and output the previous address signal; The address comparator is used to compare the current address signal and the previous address signal generated by the address decoder; and the blocking logic is used to switch the chip to the current address when the memory address to be read is the same as the address of the previous memory access The energy signal is blocked, and the buffer directly outputs the buffered data. When the address signals are the same in continuous time, the buffer outputs the buffered data instead of enabling the memory unit, so the power consumption of the static memory is reduced, and the object of the present invention can be achieved.

Wherein, the chip enable signal, the operation enable signal and the write enable signal are active at a low level, and inactive at a high level.

Wherein, when the current address signal is the same as the previous address signal, the address comparator outputs a low-level signal; otherwise, it outputs a high-level signal.

Wherein, the blocking logic is composed of an XOR gate and an OR gate, and the XOR gate inputs the output of the address comparator and the operation enable signal, and the OR gate performs a logic operation between the output of the XOR gate and the chip enable signal or process.

Description of drawings

In order to allow the examiner to better understand the technical content of the present invention, a preferred specific embodiment is given and illustrated as follows, wherein:

Fig. 1 is a structural diagram of a known static memory; and

Fig. 2 is a structural diagram of the static memory of the present invention.

Detailed ways

In the present invention, all the control signals are triggered by the low level as in the prior art, that is, the low level is the enabled state, and the high level is the disabled state. As shown in Figure 2, when both the chip enable signal (-CS) and the operation enable signal (-OE) are applied (logic 0), the read operation is performed, and when the chip enable signal (-CS) and the write If the input enable signal (-WE) is applied (logic 0), the write operation is performed.

As shown in Figure 2, the power-saving static memory control circuit structure of the present invention mainly includes an address decoder 10, an address temporary register 20, an address comparator 22, a memory unit 14, a buffer 18, and a blocking logic 24, etc., wherein The address decoder 10 is used to read the data of the address lines and perform address decoding to output address signals to select a specific memory segment of the memory unit 14 .

The address register 20 is used to store the current address signal and output the previous address signal. Wherein, the previous address signal is an earlier address signal in time, that is, the previous address signal is an address signal of a previous memory access.

The address comparator 22 is used to input and compare the current address signal and the previous address signal. If the current address signal and the previous address signal are the same, it means that the data of the same address is accessed in continuous time, and the output indicates that the address is the same. The address comparison signal (low level -CMP signal), otherwise the address comparison signal (high level -CMP signal) indicating that the address is not the same is output.

The blocking logic 24 is composed of an exclusive OR gate 241 and an OR gate 242 . The exclusive OR gate 241 is used to input the address comparison signal (-CMP) and the operation enable signal (-OE), and output to the OR gate 242 after logic inversion (NOR) processing, and the OR gate 242 outputs the output of the exclusive OR gate 241 Perform logical OR (OR) processing with the chip enable signal (-CS) to be an internal chip enable signal (-CS').

The internal chip enable signal (-CS') is used to enable the memory unit 14, so that it can perform memory reading and writing to the selected memory. When the internal chip enable signal (-CS') is applied and the operation enable signal ( -OE) is also used, then the memory unit 14 can be read, and the data stored in the specific memory segment is buffered and output to the external circuit through the buffer 18; and when the internal chip enable signal (-CS') is activated, and the write enable signal (-WE) is also activated, the memory 14 can be written, so that the data input to the buffer 18 by the external circuit can be written into a specific memory segment.

And through the processing of blocking logic 24, when the memory address to be read at present is the same as the address of the previous memory access, the output address comparison signal (-CMP) is a low level (logic 0), and the operation enabling signal (-OE) is also acted (logic 0), so the output of the exclusive OR gate 241 is a high level (logic 1), therefore, the active chip enable signal (-CS) and the output of the exclusive OR gate 241 pass through the OR gate The internal chip enabling signal (-CS') generated by the processing of 242 will become inactive (logic 1), that is, the blocking logic 24 will block (Mask) the chip enabling signal (-CS) without disabling memory unit 14, and because the memory address to be read at present is the same as the address of the previous memory access, and the buffer 18 still temporarily stores the data of the previous memory access, therefore, the data to be read at present can be directly It is only necessary to output from the buffer 18 .

And when data is written or the memory address to be read at present is different from the address of the previous memory access, the blocking logic 24 will not block the chip enable signal (-CS). Therefore, the data reading and writing mode of the memory is the same as The prior art is the same.

As can be seen from the above description, the present invention compares the current address signal and the previous address signal to block the chip enable signal (-CS) when the memory address to be read at present is the same as the address of the previous memory access. The required data still temporarily stored in the buffer is directly read from the buffer by disabling the memory unit. Since the power consumption of reading the buffer is much smaller than the power consumption of reading the memory unit, it has the advantage of reducing power consumption compared with the conventional memory control circuit.

The above-mentioned embodiments are only examples for convenience of description, and the scope of rights claimed by the present invention should be based on the scope of the patent application, rather than limited to the above-mentioned embodiments.

Claims (4)

1. the static memory control circuit of a power saving, it is by the wafer enable signal, operates enable signal and write the read-write that enable signal comes control store, wherein, when the wafer enable signal and the operation enable signal all be applied, this control circuit carries out read operation, and when the wafer enable signal and write enable signal and all be applied, this control circuit carries out write operation, it is characterized in that this control circuit comprises:

One memory cell is in order to store data;

One address decoder in order to the data of decode address line, is selected a specific memory of this memory cell to export an address signal;

One impact damper, in order to the data of the buffering access of wanting, with when carrying out read operation, with memory data buffering and the output of selecting, and when carrying out write operation, with data buffering of importing and the storer that writes to selection;

One address register is in order to store a present address signal that is produced by this address decoder and to export an address signal last time;

One address comparator is last time address signal of this present address signal of producing in order to this address decoder relatively and this; And

One blocking logic, it is when the storage address that will read at present is identical with the address of preceding primary memory access, with this wafer enable signal blocking, and this impact damper is directly with the data output that is cushioned.

2. the static memory control circuit of power saving as claimed in claim 1 is characterized in that, wherein, this wafer enable signal, to operate enable signal and write enable signal be to be active state with the low level, and high levle is active state not.

3. the static memory control circuit of power saving as claimed in claim 1 is characterized in that, wherein, when the present address signal when last time address signal was identical, the signal of this address comparator output low level, otherwise the signal of output high levle.

4. the static memory control circuit of power saving as claimed in claim 1, it is characterized in that, wherein, this blocking logic by an XOR gate and one or door institute formed, the output of this XOR gate Input Address comparer and this operation enable signal are somebody's turn to do or the output and the wafer enable signal of goalkeeper's XOR gate carry out the logical OR processing.

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