CN1436354A - Integrated dual frequency noise attenuator and transient suppressor - Google Patents

Abstract

An integral dual frequency by-pass and transient suppressor device has at least two ceramic semiconductor layers, the upper surfaces of which are formed with electrodes of generally U-shaped configuration. The base portions of the electrodes are exposed at opposite surfaces of the semiconductor layers, the leg portions of the U-shaped electrodes extending toward the base portions of electrodes of opposite polarity. The overlap or registration area of one pair of legs differs from the overlap area of the other leg pair with the result that two capacitors of different values are formed, the capacitors being in parallel and accordingly defining a low impedance path at two discrete frequencies. By varying the conductive paths as a function of the length of the electrode and/or the base of the U, a desired internal inductance is developed. Use of a semiconductor material in place of a dielectric provides transient energy suppression by shunting to ground any signal introduced to the device at a level at or above the breakdown voltage of the semiconductor.

Description

Integrated Dual-Band Noise Attenuator and Transient Suppressor

technical field

The present invention relates to a shunt or attenuation device having the properties of a varistor, and more particularly, the present invention relates to a miniaturized ceramic device for attenuating noise at multiple (at least two) discrete frequencies and capable of Transient suppression of voltage spikes and current spikes. A particular application of the device is, but not exclusively, as a noise attenuator and varistor in so-called dual-mode cellular phones having both digital and analog outputs. In this type of setup, the signal is transmitted simultaneously at two discrete frequencies, and it is desirable to attenuate to a minimum the "noise" produced by each of the two frequencies, while at the same time protecting the circuit from voltage The impact of spikes and current spikes, spikes are caused by external signal sources such as electrostatic discharge or internal signal sources such as battery peaks.

Background technique

For recent dual-mode cellular phones, the usual design is to set up separate LC (inductor-capacitor) networks, which are specially designed to attenuate (bypass ground) the noise generated by the digital transmit circuit and the analog transmit circuit separately. The current trend is miniaturization, and the need to utilize multiple scattered devices connected to the motherboard is not popular because multiple devices will occupy precious "geographical space".

Perhaps even more important, for the very high frequencies used in cellular phone technology (for example, 900MHz for analog transmission and 1.9GHz for digital transmission), since the lead circuits connected to the individual components themselves act as inductors , so the inclusion of the lead circuit will cause a large change in inductance.

Various forms of circuitry are known in the art, some examples from the US patent literature are listed below.

US Patent No. 5,430,601 discloses a multi-layer capacitor (MLC), which includes connection resistors.

US 5170317 discloses an MLC that, in addition to the main electrode, also includes a "correction" electrode that is narrower than the main electrode so that the capacitor has a precise capacitance.

US Patent US 4758922 discloses a U-shaped stripline that acts as a resonant element (capacitor) and has a ground plane and a dielectric layer interposed.

US patent US 4479100 relates to an impedance matching network comprising a plurality of electrodes with different cross-sectional areas. These electrodes can be connected in parallel with the main electrodes to provide a selected desired capacitance.

US Patent No. 4,074,340 discloses an MLC comprising regulating electrodes extending laterally to the whole. Capacitance adjustment is performed by connecting or disconnecting the external adjustment electrode to the main electrode.

US 4048593 and US 2758256 disclose the principle of arranging multiple discrete capacitors on a single substrate.

U.S. Patent No. 5,898,562, which has a common applicant with the present application, discloses the principle of making two discrete capacitors with different capacitance values in one device by setting two different overlapping regions using U-shaped electrodes.

The entire disclosures of the aforementioned US patents are hereby incorporated by reference.

Contents of the invention

The present invention relates to an integrated ceramic dual frequency noise attenuation device which provides transient energy protection. More particularly, the present invention relates to an attenuation device adapted to provide a low impedance ground circuit at a plurality of discrete frequencies and additionally adapted to provide protection from voltage spikes and current spikes that may pass through the device. protection of.

More specifically, the present invention relates to a dual-frequency shunt device having rheostat characteristics, which is characterized in that it is very simple to manufacture and provides a precise and accurately controlled dual LC circuit.

More specifically, the present invention relates to a single or multilayer shunt device having varistor characteristics, which is particularly suitable for filtering noise and providing transient energy protection, an embodiment of which includes a pair of U-shaped electrodes in ceramic semiconductor structures. Each electrode includes a base and a pair of branch portions extending from the base. In the ceramic structure, each base is arranged at the edge of a respective layer, the branches of each U-shaped electrode point towards the base of the opposite U-shaped electrode, and the electrodes are arranged on the upper surface of each layer in the ceramic semiconductor.

Other objects and advantages of the present invention are set forth in the following detailed description, from which those of ordinary skill in the art will understand these objects and advantages. In addition, those of ordinary skill in the art can also understand that, using the reference materials listed herein, without departing from the concept and protection scope of the present invention, the various embodiments and applications of the present invention can be used to refer to the Features and steps specifically shown, referenced, and discussed are subject to modification and modification. Such modifications may include, but are not limited to, substitutions of equivalent means and features, materials or steps shown, referenced or discussed; changes in function, operation or position of individual components, features, steps and the like.

Furthermore, it is to be understood that different embodiments of the present invention, and presently preferred different embodiments of the present invention, include various combinations or configurations of the presently disclosed features, steps, elements, or equivalents thereof (included in the accompanying drawings). combination of features or steps not explicitly stated in or not mentioned in the detailed description, or its structure).

It is characteristic of this exemplary device that the overlapping region defined by one pair of branches is different than the overlapping region defined by the second pair of branches, thereby forming two discrete capacitance values. The difference can be obtained by designing the length of one pair of branches to be greater than the length of the other pair, or by designing the width of one pair of overlapping branches to be greater than the width of the other pair of branches, or a combination of the two. the overlapping area.

Another feature that reflects the characteristics of the exemplary embodiments of the present invention is that the composition formed by connecting the branches of the U-shaped electrode with the base of the U-shaped electrode acts as an inductor, thereby, by arranging the above-mentioned U-shaped electrode Assemblies, such a circuit is naturally formed: two capacitors with different capacitance values are connected in parallel and connected in series with a pair of inductors, wherein the inductors are defined by electrodes that are also connected to the base of the U-shaped structure. together form a capacitor. The differential capacitance is achieved by making the overlapping branches on one side of the U-shaped electrode longer than the overlapping branches on the opposite side, in which case the longer branch has a longer conductive path, so it is naturally proportional to this ground has a large inductance.

Another feature of the present invention is that due to the U-shaped structure of the electrodes, in order to increase the inductance by extending the base of the U-shaped electrodes, the inductance alone is effectively increased without considerably increasing the capacitance.

Another feature that characterizes the exemplary embodiments of the device of the present invention is that instead of the dielectric, which was previously used to construct the capacitor, a semiconductor material having dielectric properties enables the device to operate at a voltage lower than the breakdown voltage of the semiconductor material. The level acts as a capacitor, and the semiconductor material has the property of conducting electricity at voltage levels at or above its breakdown voltage, allowing the device to act as a varistor.

The device of the present invention provides a compact and easy-to-manufacture device with ideal shunting and noise attenuation and varistor characteristics in a single chip with only two leads (surface mount or wire mount) Connect to the motherboard. By minimizing the external conductive paths, a great degree of control over the characteristics of the shunt device can be exercised. This is contrary to the shunt technology using discrete capacitors and inductors. In the case of using discrete devices, it is necessary to set an extended conductive path on the PC motherboard. Therefore, it is more or less necessary to set a controllable inductance.

According to the present invention, it is an object to provide an easily manufacturable integrated chip device which is particularly suitable as a shunt device or noise attenuator at multiple discrete frequencies, while also acting as a varistor to protect the circuit from voltage spikes and current The impact of sharp pulses.

Another object of the present invention is to provide a device of the above-mentioned kind, wherein the capacitance and inductance values of the device can be precisely determined, and the device complies with the requirements of efficient use of the geographical space of the connected motherboard.

Another aspect of the invention addresses the integration of a dual frequency noise attenuation device with the transient energy characteristics of a varistor. The protective properties of a varistor are achieved by replacing the dielectric with a semiconducting material such as zinc oxide (ZnO), which would otherwise be used to construct the capacitor.

Other embodiments of the invention, not necessarily presented in this summary section, may include and incorporate the aspects mentioned in the above summarized object of the invention, and/or additional features discussed in this application various mixes and combinations.

The features and aspects of these and other embodiments, including methods of manufacture, will be better understood by those of ordinary skill in the art after reading the following portions of the specification.

Description of drawings

In the following detailed description, for those of ordinary skill in the art, the present invention has been completely and effectively disclosed with reference to the accompanying drawings. This disclosure includes preferred embodiments of the present invention. In the accompanying drawings:

Figure 1 is an exploded perspective view showing an exemplary device of the present invention;

Fig. 2 and Fig. 3 are top views, respectively showing the upper electrode and the lower electrode in the exemplary device according to the present invention;

Fig. 4 is the schematic circuit diagram of the exemplary device of the present invention shown in Fig. 1;

Figures 5 and 6 are top views showing, respectively, the upper and lower electrodes of an exemplary device of the present invention to be discussed in detail below;

Fig. 7 and Fig. 8 are top views, respectively showing the upper electrode and the lower electrode arranged in the exemplary device, and the specific dimensions on the specific positions of the two electrodes are shown in the figure, wherein, according to the exemplary device of the present invention It is discussed in conjunction with Figure 5 and Figure 6;

Figure 9 is a schematic exploded perspective view showing the exemplary device of the present invention discussed in connection with Figures 5 to 8;

Figure 10 is a schematic circuit diagram of the exemplary apparatus of the present invention discussed in connection with Figures 5 to 9;

FIG. 11 is a graph showing the attenuation versus frequency for the exemplary apparatus of the present invention described in connection with FIGS. 5 through 10 .

Reference numerals will be used repeatedly hereinafter to refer to the same or analogous features or elements of the invention. The drawing scale of the drawings is not strict, and in some cases, in order to make the present invention more clearly presented and easier to understand, the relevant components are shown enlarged to show the detailed structures.

Detailed ways

Referring to the accompanying drawings, FIG. 1 is an exploded perspective view of the device according to the present invention, the size and thickness of each element are significantly enlarged, so as to clearly present and understand the structure.

The shunt varistor device 10 generally consists of at least two semiconductor layers 11, 31, the upper surfaces of which are provided with a U-shaped upper electrode 12 and a lower electrode 13 formed thereon. Electrode 12 includes a base 14 having branches 15 and 16 projecting from opposite ends. The electrode 13 includes a base portion 14a from which branch portions 15a and 16a protrude from opposite ends thereof.

It can be clearly seen from FIG. 1 that the electrodes 12 and 13 are respectively arranged above the semiconductor layers 11 and 31 in such a way that the bases 14 and 14a are respectively exposed at opposite edges of the semiconductor layers. It can be seen from Figure 1 that a single unit is represented by a solid line, which includes an upper electrode, a lower electrode, and an intervening semiconductor layer, and any number of layers can be set in a multilayer device to obtain the required capacitance. value and inductance value.

Terminals 17, 18 are formed on the end edges of the semiconductor layer, the terminal 17 is electrically connected to the base 14a of the electrode 13, and the terminal 18 is electrically connected to the base of the electrode 12 or other parts.

As can be clearly seen from Figures 1 to 3, due to the smaller width and length L2 of the branches 15 and 15a, the alignment or overlap region 19 defined by the branches 15 and 15a will be smaller than that defined by the longer, wider branch 16. , 16a defines the overlapping region 20, wherein the length of the branch 16, 16a is represented by the symbol L1.

Since the capacitance value is directly proportional to the overlap area, the capacitance value defined in the overlap region 19 will be smaller than the capacitance value defined in the overlap region 20 . Thus, it will be appreciated that by varying the widths of the respective overlapping branch features, or by varying the length of the overlapping features, or both, it is possible to obtain a capacitor C1 defined by the overlapping region 19 as compared to a capacitor C1 defined by the overlapping region 20. The capacitance difference required between bulk capacitor C2.

Since the inductance is set as a function of the total length of the conductive path, using branches of different lengths naturally provides a larger inductance with longer branch lengths, whereby the inductance automatically becomes larger to interact with the larger capacitance value , so it is preferable to adjust the capacitance value according to the length of the overlapping branches.

When integrated into the dual-frequency noise attenuator described above, the semiconductor 11 interposed between the upper electrode 12 and the lower electrode 13 has all the electrical insulating properties necessary for the dielectric used to make a capacitor. However, substituting semiconductors for the commonly used dielectrics also brings additional useful properties to integrated devices.

Replacing the dielectric with a semiconductor allows the device to also function as a varistor. As is understood, a semiconductor material becomes a conductor at a certain breakdown voltage. If a voltage level that reaches or exceeds the semiconductor's breakdown voltage is introduced into the dual frequency resonant capacitor arrangement, the semiconductor becomes conductive, effectively shunting unwanted signals to ground. In this way, the device protects the circuit from voltage spikes and current spikes that typically occur due to conditions such as electrostatic discharge (ESD) or battery spikes. In the electronics industry, since the trend is towards ever-increasing miniaturization, it is highly desirable to integrate these functions into one device.

Manufacturing method

The method of fabricating a shunt device with varistor properties is largely the same as the traditional method of fabricating ceramic capacitors. Since this method is well known to those skilled in the art, it is only briefly described below. Those skilled in the art will also appreciate that the described method is only one of many known methods for making ceramic capacitors.

Semiconductor devices are formed by casting a thin layer of a slurry of a semiconductor-forming material, such as fine-grained zinc oxide, suspended in a liquid base containing a binder. The "green" porcelain is screen-printed with electrode-forming inks to form the desired U-shaped pattern. Typically, the ink contains a metal, such as platinum. The patterned green ceramics are stacked to provide the desired number of layers, aligning the patterns of adjacent layers to achieve the desired overlapping state. Individual units are obtained by dicing the stacked semiconductor layers in such a way that the bases 14, 14a are exposed at opposite ends of the burn-in chip. Thereafter, the cut-out units are subjected to binder burn-out treatment at a first temperature, and then sintered at a higher temperature to form the structure.

Terminals 17, 18 are respectively attached to the bare base 14 at one end and the base 14a at the other end. The terminals can be made by any of a number of known methods, including vapor deposition methods to provide electrical and mechanical bonding to the base of the exposed electrode at the opposite end of the semiconductor layer, followed by coating on the sputtered layer. One or more layers of metal so that it can be soldered to the motherboard. Where face mounting is desired, the terminals can extend beyond the edge of the end. As an alternative termination method, a layer of carbon may be applied first, followed by an outer layer of silver, with or without a metal layer between the carbon and silver layers.

Example

Consistent with the requirement of "preferred embodiment" in the US patent law, specific examples of components according to the present invention are given below with reference to FIGS. 5 to 10, but are not limited thereto. Those skilled in the art can understand that in other exemplary embodiments of the present invention, there may be different device values and dimensions.

The multilayer device is fabricated from 8 active layers of zinc oxide ceramic, each approximately 0.002268 inches thick. In this embodiment, eight active electrodes are used. In the example shown, branches 115 and 116 have widths Z1 and Z3, respectively, which are the same at 0.004860 inches. Branches 115a and 116a have widths Z5 and Z7, respectively, which are the same and are both 0.007290 inches. The length Z2 of the base 114 is 0.01620 inches. The length Z4 of the base 114a is 0.019440 inches. The length Y1 of the branch 115 is 0.029970 inches. The length Y2 of the branch 116 is 0.01701 inches. The lengths Y3 and Y4 of branches 115a and 116a are equal, both 0.050220 inches. The widths X1 and X2 of the legs 114, 114a are equal at 0.006480 inches. The distance R1 between branches 115 and 116 is 0.006480 inches. The distance R2 between branches 115a and 116a is 0.004860 inches. The total length S1 of each layer is 0.059940 inches. The overall width T1 of each layer is 0.03240 inches. The distance Q1 between the ends of branches 115a and 116a and the outer edge of the layer is 0.009720 inches. As can be clearly seen from FIG. 9, the electrodes are stacked such that the overlapping or alignment area 119 of the branches 115 and 115a is approximately three times the size of the overlapping area 200 of the branches 116 and 116a.

It is measured that the capacitance of the capacitor C11 defined by the overlapping region 200 is about 16 picofarads, and the capacitance of the capacitor C21 defined by the region 119 is about 46 picofarads. It can be calculated that the values of the inductances La1 and Lb1 are about 0.6 nanohenries.

Obviously, by tailoring the overlapping regions, many different capacitance values can be obtained. Similarly, by changing the length and width of the electrode branches and the base, the desired inductance can be tailored to a specific application. Representative resistor values R11 and R21 associated with these devices are nominal values and will of course depend on the physical structure of the device, and the specific example of resistance is not important to the discussion of the exemplary embodiments herein. The values of the illustrated example have been found to be very effective as a splitter for a dual-mode cellular telephone operating at analog and digital frequencies of 900 MHz and 1.9 GHz, respectively. It is particularly advantageous that the properties of the inductance are predictable, as opposed to the large variation in inductance associated with variations in the lead circuit length between the capacitors due to the use of split capacitors.

Obviously, after being familiar with the disclosure of the present invention, those skilled in the art can easily make various changes to the details of the structure without departing from the idea of the present invention. Accordingly, the present invention can be interpreted broadly.

Claims (24)

1. A multi-frequency noise attenuating device having varistor characteristics, the device having a first side and a second side, said device comprising a plurality of three-layer LC circuit stacks with the same number of secondary The semiconductor layers are arranged across. 2. The multi-frequency noise attenuation device with varistor characteristics according to claim 1, wherein the three-layer LC circuit stack further comprises: a first U-shaped ceramic electrode plate having a first base and a first branch portion of variable length and width, the first base being disposed along a first side of the device; Primary semiconductor layer; a second U-shaped ceramic electrode plate having a second base and a second branch portion of variable length and width, the second base being disposed along a second side of the device; Wherein, the first side and the second side are opposite to each other. 3. The multi-frequency noise attenuation device with varistor characteristics according to claim 2, wherein said device further comprises: a first terminal electrically connected to the first base of the first U-shaped ceramic electrode plate; A second terminal, which is electrically connected to the second base of the second U-shaped ceramic electrode plate. 4. The multi-frequency noise attenuation device with varistor characteristics according to claim 2, wherein the first branch part and the second branch part in each three-layer LC circuit stack have a predetermined amount along the length direction overlap. 5. The multi-frequency noise attenuation device with varistor characteristics according to claim 4, wherein the overlapping regions of the first and second branch portions in each three-layer LC circuit stack are preset to The resulting paired capacitance values are precisely defined. 6. The multi-frequency noise attenuating device having varistor characteristics according to claim 2, wherein said primary and secondary semiconductor layers comprise a zinc oxide material. 7. A multi-frequency noise attenuating device having varistor characteristics, the device having a first side and a second side, said device comprising a plurality of four-layer LC circuit stacks. 8. The multi-frequency noise attenuation device with varistor characteristics according to claim 7, wherein the four-layer LC circuit stack further comprises: a first U-shaped ceramic electrode plate having a first base and a first branch portion of variable length and width, the first base being disposed along a first side of the device; a first semiconductor layer; a second U-shaped ceramic electrode plate having a second base and a second branch portion of variable length and width, the second base being disposed along a second side of the device; a second semiconductor layer; Wherein, the first side and the second side are opposite to each other. 9. The multi-frequency noise attenuation device with varistor characteristics according to claim 8, wherein said device comprises: a first terminal electrically connected to the first base of the first U-shaped ceramic electrode plate; A second terminal, which is electrically connected to the second base of the second U-shaped ceramic electrode plate. 10. The multi-frequency noise attenuation device with varistor characteristics according to claim 2, wherein the first branch part and the second branch part in each three-layer LC circuit stack have a predetermined amount along the length direction overlap. 11. The multi-frequency noise attenuation device with varistor characteristics according to claim 10, wherein the overlapping area of the first and second branch parts in each three-layer LC circuit stack is preset, so as to The resulting paired capacitance values are precisely defined. 12. The multi-frequency noise attenuating device having varistor characteristics according to claim 8, wherein the first and second semiconductor layers comprise a zinc oxide material. 13. A multi-frequency noise attenuating device having rheostat characteristics, the device having a first side and a second side, the device comprising: The first U-shaped electrode plate; a second U-shaped ceramic electrode plate; and multiple semiconductor layers. 14. The multi-frequency noise attenuation device with varistor characteristics according to claim 13, wherein the plurality of semiconductor layers are arranged crosswise with the first and second U-shaped electrode plates. 15. The multi-frequency noise attenuation device with varistor characteristics according to claim 14, wherein the first U-shaped electrode plate further comprises: a first base disposed along a first side of the device; first branch part; the second branch part; Wherein, the first and second branch parts have preset and variable length and width characteristics with each other. 16. The multi-frequency noise attenuation device with varistor characteristics according to claim 15, wherein the second U-shaped electrode plate further comprises: a second base disposed along a second side of the device; the third subdivision; The fourth branch part; Wherein, the third and fourth branch portions have preset and variable length and width characteristics with respect to each other. 17. The multi-frequency noise attenuating device having varistor characteristics according to claim 16, wherein said first and third branch portions define a first overlapping region, said second and fourth branch portions define a second overlapping area. 18. The multi-frequency noise attenuating device having varistor characteristics according to claim 19, wherein the first and second overlapping regions have different characteristic values. 19. The multi-frequency noise attenuation device with varistor characteristics according to claim 16, wherein said device further comprises: a first terminal electrically connected to the first base of the first U-shaped ceramic electrode plate; a second terminal electrically connected to the second base of the second U-shaped ceramic electrode plate; Wherein, the first side and the second side are opposite to each other. 20. The multi-frequency noise attenuating device having varistor characteristics according to claim 13, wherein the plurality of semiconductor layers comprise a zinc oxide material. 21. The multi-frequency noise attenuating device having varistor characteristics according to claim 13, wherein said first and second U-shaped electrode plates are ceramic. 22. A method for manufacturing a multi-frequency noise attenuating device having varistor characteristics, said method comprising the steps of: (a) providing a plurality of primary semiconductor layers; (b) providing a plurality of secondary semiconductor layers; (c) performing screen printing on each of the plurality of primary semiconductor layers to produce the first U-shaped ceramic electrode plate; (d) performing screen printing on each of the plurality of secondary semiconductor layers to produce a second U-shaped ceramic electrode plate; (e) intersecting said primary and secondary semiconductor layers with said first and second U-shaped electrode plates thereon; and (f) setting terminals of opposite polarity on the device, thereby forming a first terminal and a second terminal, the first terminal is electrically connected to the first U-shaped ceramic electrode plate, and the second terminal opposite thereto The two terminals are electrically connected to the second U-shaped ceramic electrode plate. 23. The method for manufacturing a multi-frequency noise attenuating device having varistor characteristics according to claim 22, wherein said device has a first side and a second side opposite to each other, and wherein said first U-shaped The electrode plate has a base arranged along the first side communicating with the first terminal, the second U-shaped electrode plate has a second base arranged along the second terminal The communicating second side is arranged. 24. The method for manufacturing a multi-frequency noise attenuating device having varistor characteristics according to claim 23, wherein the first U-shaped electrode plate has two branch portions, and the second U-shaped electrode plate has two branch portions. and wherein the two branch portions of the first electrode plate overlap with the two branch portions of the second electrode plate, thereby forming a capacitor element in the LC circuit.

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