CN1420542A - Manufacturing method of semiconductor device applied to system chip - Google Patents

Abstract

A method for manufacturing semiconductor device used in system chip includes forming multiple bit lines and the first dielectric layer on memory unit of substrate and forming the second dielectric layer on peripheral circuit region, forming the first dielectric layer on the second dielectric layer and forming the second dielectric layer on the first dielectric layer and the second dielectric layer on the second dielectric layer. Then, after forming plural grids in the memory unit area and the peripheral circuit area, ion implantation of lightly doped source/drain area of the P-type MOS transistor is carried out by energy which can only penetrate the substrate surface of the peripheral circuit area but can not penetrate the substrate surface of the memory unit area. Then, a plurality of spacers are formed on sidewalls of the gate, wherein the spacers formed on sidewalls of adjacent gates in the memory cell region are connected to each other. Then, forming multiple P-type source/drain regions on the substrate at two sides of the grid of the P-type MOS transistor device region in the peripheral circuit region.

Description

Manufacturing method of semiconductor device applied to system chip

technical field

The invention relates to a manufacturing method of a semiconductor device, and in particular to a manufacturing method of a semiconductor device applied to a system chip.

Background technique

With the competition in the market, the current production of integrated circuits has moved towards making read-only memory, static random access memory, flash memory or dynamic random access memory, logic circuit, digital circuit, etc. on the same chip, which is the so-called system chip (System On a Chip, SOC), in order to meet the requirements of light, thin, short, small and high function.

However, the DRAM, flash memory, logic circuits, and radiofrequency (RF) devices are manufactured on the same chip, and the circuit connection between them is relatively complicated in the design of the circuit layout. In addition, since the manufacturing methods of devices with different functions are quite different, how to integrate and manufacture devices with different functions on the same chip is very important in the manufacture of the system chip.

Please refer to FIG. 1 which is a top view of a memory cell area of a known system chip. FIG. 2 is a cross-sectional view of a known system chip. In FIG. 2 , it can be divided into a memory cell area 200 and a peripheral circuit area 202 . Wherein, the memory cell region 200a is a cross-sectional view along line I-I' in FIG. 1 . The memory cell region 200b is a cross-sectional view along line II-II' in FIG. 1 .

Please refer to FIG. 1 and FIG. 2 at the same time, the system chip is divided into a memory cell area 200 and a peripheral circuit area 202 . A plurality of bit lines 102, a composite dielectric layer 104 composed of silicon oxide/silicon nitride/silicon oxide, a plurality of gates 108, an anti-breakdown ion implantation region 114 and an The spacer 116 on the sidewall of the gate 108 . On the substrate 100 of the P-type metal oxide semiconductor transistor (PMOS) device region of the peripheral circuit region 202, a dielectric layer 106, a plurality of gates 110, and a P-type lightly doped source/drain region 112 (LightDoped Drain) have been formed. , LDD), the source/drain region 120 and the spacer 118 located on the sidewall of the gate 110 .

In the manufacturing process of the above-mentioned system chip, a part of the dielectric layer (not shown) is removed by anisotropic etching to form spacers 116 and 118 on the sidewalls of the gate 108 and gate 110. The surface of the substrate 100 in the cell region 200 is prone to form silicon recesses 122 (Si Recess) due to over-etching (Over Ething). Since the surface of the substrate 100 has a higher ion concentration, when silicon recesses are formed on the surface of the substrate 100 in the memory cell region 200 , the ion concentration of the substrate 100 will be insufficient and a punchthrough phenomenon (PunchThrough) will easily occur. Therefore, it is necessary to implant P ^- type ions into the substrate 100 on both sides of the gate 110 of the P-type metal oxide semiconductor transistor (PMOS) device region of the peripheral circuit region 202 . In the step of forming the P-type lightly doped source/drain region 112, ion implantation is performed with higher ion implantation energy, so as to implant P ^- type ions between the gates 108 of the memory cell region 200 at the same time, An anti-puncture ion implantation region 114 (Anti-Punch Through Region) is formed. However, the formation of the anti-breakdown ion implantation region in the memory cell region 200 will cause the initial voltage (Vt) of the device to rise due to the diffusion of P-type ions, and will generate Problems such as Junction Breakdown.

Contents of the invention

Therefore, the present invention is to provide a method for manufacturing a semiconductor device applied to a system chip, so that no silicon recess occurs in the memory cell area, so that the memory cell area does not need to be implanted for anti-breakdown, and the device performance can be improved.

The present invention provides a manufacturing method of a semiconductor device applied to a system chip. The method includes providing a substrate having a memory cell region and a peripheral circuit region. After forming a plurality of bit lines in the memory cell region of the substrate, the substrate is A first dielectric layer and a second dielectric layer are respectively formed in the memory cell area and the peripheral circuit area. Next, a plurality of gates are formed in the memory cell area and the peripheral circuit area of the substrate. And carry out a comprehensive ion implantation step, the ion implantation energy of this ion implantation step is to make the implanted ions enough in the substrate on both sides of the gate of a P-type metal oxide semiconductor transistor device area in the peripheral circuit area A plurality of P-type lightly doped source/drain regions are formed, but an anti-breakdown ion implantation region cannot be formed in the substrate of the memory cell region. Then, a plurality of spacers are formed on the sidewalls of the gate, wherein the spacers formed by the sidewalls of adjacent gates in the memory cell area are connected to each other. An ion implantation step is then performed to form a plurality of P-type source/drain regions in the substrate on both sides of the gate of the P-type MOS transistor device region in the peripheral circuit region.

According to a preferred embodiment of the present invention, since the gap between the gates of the memory cell region becomes smaller as the integration of semiconductor devices increases, the spacers subsequently formed on the side walls of the gates will be connected to each other Therefore, through the blocking of the connecting spacer, the substrate between the gates of the memory cell area will not be over-etched, and of course the phenomenon of silicon recess will not be caused, and there is no need to recess the silicon in the memory cell area. Perform breakdown-resistant ion implantation. Moreover, in the step of ion implantation of the P-type slightly doped source/drain region of the P-type metal oxide semiconductor transistor device region in the peripheral circuit region, the present invention can only penetrate the P-type metal oxide semiconductor region of the peripheral circuit region. The base surface of the metal oxide semiconductor transistor, and the energy that cannot penetrate the base surface of the memory cell region will only form a P-type lightly doped source/drain region in the peripheral circuit region, but will not form an anti-breakdown region in the memory cell region ion implantation area. Of course, the initial voltage (Vt) increase due to the diffusion of P-type ions and the junction breakdown (Junction Breakdown) at the source/drain junction will not be caused.

Therefore, the manufacturing method of a semiconductor device applied to a system chip disclosed by the present invention can prevent silicon depressions in the storage unit area, and at the same time do not need to perform anti-breakdown implantation on the storage unit area, and can improve device performance.

Description of drawings

In order to make the purpose, features and advantages of the present invention more obvious and understandable, the following is described in detail in conjunction with the accompanying drawings:

Fig. 1 is the top view of the storage cell area of a known system chip;

Fig. 2 is a sectional view of a known system chip;

Fig. 3 is the top view of the storage unit area of a kind of system chip of the preferred embodiment of the present invention:

4A to 4C are sectional views of a manufacturing process of a system chip according to a preferred embodiment of the present invention.

The marks in the figure are:

100, 300: base

102, 302: bit line

104, 106, 304, 306: dielectric layer

108, 110, 308, 310: grid

112, 312: Lightly doped source/drain regions

114: Anti-breakdown ion implantation area

116, 118, 314, 316: gap wall

120, 318: source/drain regions

122: Silicon depression

200, 200a, 200b, 400, 400a, 400b: memory cell area

202, 402: peripheral circuit area

Detailed ways

The method for manufacturing a semiconductor device applied to a system chip according to a preferred embodiment of the present invention will be described in detail below with reference to the accompanying drawings. FIG. 3 is a top view of a storage unit area of a system chip according to a preferred embodiment of the present invention. 4A to 4C are cross-sectional views of a manufacturing process of a system chip according to a preferred embodiment of the present invention. In FIG. 4A and FIG. 4C , it can be divided into a memory cell area 400 and a peripheral circuit area 402 . Wherein, the memory cell region 400a is a cross-sectional view along line III-III' in FIG. 3 . The memory cell region 400b is a cross-sectional view along line IV-IV' in FIG. 3 .

First, please refer to FIG. 3 and FIG. 4A , a substrate 300 is provided, and a plurality of bit lines 302 are formed on the substrate 300 . The method for forming the bit line 302 is, for example, to first form a patterned photoresist layer (not shown) on the substrate 300, and then perform an ion implantation process to implant N in the substrate 300 exposed by the patterned photoresist layer. ⁺ -type ions, and then remove the patterned photoresist layer to form the bit line 302 .

Next, a composite dielectric layer 304 is formed in the memory cell area 400 and a dielectric layer 306 is formed in the peripheral circuit area 402. The composite dielectric layer 304 is composed of silicon oxide/silicon nitride/silicon oxide, for example, to form The method of the composite dielectric layer 304 is, for example, chemical vapor deposition (Chemical Vapor Deposition, CVD). The material of the dielectric layer 306 is, for example, silicon oxide, and the method of forming the dielectric layer 306 is, for example, thermal oxidation. Wherein, the steps of forming a layer of composite dielectric layer 304 in the memory cell area 400 and forming a dielectric layer 306 in the peripheral circuit area 402 are, for example, first forming a layer of photoresist layer (not shown) to cover the memory cell area 400 and expose In the peripheral circuit area 402 , after forming the dielectric layer 306 on the substrate 300 of the peripheral circuit area 402 , the photoresist layer covering the memory cell area 400 is removed. Then, another layer of photoresist layer (not shown) is formed to cover the peripheral circuit area 402 and expose the memory cell area 400, and then form a layer of composite dielectric layer 304 on the substrate 300 of the memory cell area 400, and then remove the cover The photoresist layer of the peripheral circuit area 402. Of course, a layer of photoresist layer (not shown) can be formed to cover the peripheral circuit area 402 and expose the memory cell area 400, and then form a layer of composite dielectric layer 304 on the substrate 300 of the memory cell area 400, and then remove the cover. The photoresist layer of the peripheral circuit area 402. Then, another layer of photoresist layer (not shown) is formed to cover the memory cell area 400 and expose the peripheral circuit area 402, and then after forming the dielectric layer 306 on the substrate 300 of the peripheral circuit area 402, remove the covering memory cell region 400 of the photoresist layer.

Next, referring to FIG. 3 and FIG. 4B , a conductive layer (not shown) is formed on the substrate 300. The material of the conductive layer is, for example, doped polysilicon. The method of forming the conductive layer is, for example, In-Situ ) by doping ions, a doped polysilicon layer is formed on the substrate 300 by chemical vapor deposition. Then, the conductor layer is patterned by using a lithographic etching process to form a plurality of gates 308 in the memory cell area 400 and a plurality of gates 310 in the peripheral circuit area 402 .

Then, carry out a comprehensive ion implantation step, using the gate 310 of the P-type metal oxide semiconductor transistor device region in the peripheral circuit region 402 as a mask, implanting ^P- ions in the substrate 300 on both sides of the gate 310, to form a P-type lightly doped source/drain region 312 . Wherein, the energy control of the ion implantation step enables the implanted ions to form a P-type lightly doped source/drain in the substrate 300 on both sides of the gate 310 of the P-type metal oxide semiconductor transistor device region in the peripheral circuit region 402 pole region 312 , but cannot form an anti-puncture ion implantation region in the substrate 300 of the memory cell region 400 .

Next, referring to FIG. 4C, a dielectric layer (not shown) is formed on the entire substrate 300. The material of the dielectric layer is, for example, silicon oxide or silicon nitride. The method of forming the dielectric layer is, for example, chemical vapor deposition. . Then, part of the dielectric layer is removed to form a spacer 314 on the sidewall of the gate 308 in the memory cell region 400 and a spacer 316 on the sidewall of the gate 310 in the peripheral circuit region 402 . A method for removing part of the dielectric layer is, for example, anisotropic etching. Since the gap between the gates 308 of the memory cell region 400 becomes smaller as the integration of semiconductor devices increases, the deposited dielectric layer will fill up the gaps between the gates 308 of the memory cell region 400, so that subsequent During the process of forming the spacers 314 on the sidewalls of the gates 108, the dielectric layer between the gates 308 will not be completely removed, that is, the spacers 314 between the gates 308 will be connected to each other, so The substrate 300 between the gates 308 will not be over-etched, and of course there will be no silicon recess, and there is no need to perform anti-breakdown ion implantation on the silicon recess of the memory cell region 400 .

Then, using the spacer 316 and the gate 310 in the peripheral circuit area 402 as a mask, an ion implantation step is carried out, in the substrate 300 on both sides of the gate 310 of the P-type metal oxide semiconductor transistor device area in the peripheral circuit area 402 P ⁺ -type ions are implanted to form source/drain regions 318 .

Afterwards, the process of completing the SoC can be easily realized by those skilled in the art, so details are not repeated here.

According to the above-mentioned preferred embodiment of the present invention, since the spacers between the gates of the memory cell regions are connected to each other, the barrier between the gates of the memory cell regions will not be blocked by the connected spacers. In the case of over-etching, of course, the phenomenon of silicon recess will not be caused, and there is no need to perform anti-breakdown ion implantation on the silicon recess in the memory cell region. Moreover, in the ion implantation step of the P-type lightly doped source/drain region of the P-type metal oxide semiconductor transistor device region in the peripheral circuit region, the present invention can only penetrate the P-type gold in the peripheral circuit region The base surface of the oxygen semiconductor transistor device region, and the energy that cannot penetrate the base surface of the memory cell region will only form a P-type lightly doped source/drain region in the P-type metal oxide semiconductor transistor device region of the peripheral circuit region, The anti-breakdown ion implantation region will not be formed in the memory cell region. Of course, the initial voltage (Vt) increase due to the diffusion of P-type ions, and the junction breakdown (Junction Breakdown) at the source/drain junction (Junction) will not be caused.

Therefore, the manufacturing method of a semiconductor device applied to a system chip disclosed by the present invention can prevent silicon depressions in the storage unit area, and at the same time do not need to perform anti-breakdown implantation on the storage unit area, and can improve device performance.

Although the present invention has been disclosed as above with a preferred embodiment, it is not intended to limit the present invention. Any changes and modifications made by those skilled in the art without departing from the spirit and scope of the present invention belong to this invention. protection scope of the invention.

Claims (13)

1. manufacture method that is applied to the semiconductor device of System on Chip/SoC, it is characterized in that: this method comprises:

One substrate is provided, and this substrate comprises a memory cell areas and a peripheral circuit region;

This memory cell areas in this substrate forms plurality of bit lines;

This memory cell areas and this peripheral circuit region in this substrate form one first dielectric layer and one second dielectric layer respectively;

This memory cell areas and this peripheral circuit region in this substrate form a plurality of grids;

Carry out a comprehensive ion implantation step, the ion of this ion implantation step is implanted energy makes the ion of being implanted be enough to form the light doped source/drain regions of a plurality of P types in this substrate of those grid both sides of a P type MOS (metal-oxide-semiconductor) transistor device region of this peripheral circuit region, wears ion implantation region but can't form a resistance in this substrate of this memory cell areas;

Sidewall at those grids forms a plurality of clearance walls, and wherein adjacent formed those clearance walls of those gate lateral walls are connected with each other among this memory cell areas;

Carry out an ion implantation step, in this substrate of those grid both sides of this P type MOS (metal-oxide-semiconductor) transistor device region of this peripheral circuit region, to form a plurality of P type source/drain regions.

2. the manufacture method that is applied to the semiconductor device of System on Chip/SoC according to claim 1 is characterized in that: the material of this first dielectric layer comprises the silicon oxide/silicon nitride/silicon oxide layer.

3. the manufacture method that is applied to the semiconductor device of System on Chip/SoC according to claim 2 is characterized in that: the method that forms this first dielectric layer comprises chemical vapour deposition technique.

4. the manufacture method that is applied to the semiconductor device of System on Chip/SoC according to claim 1 is characterized in that: the material of this second dielectric layer comprises silica.

5. the manufacture method that is applied to the semiconductor device of System on Chip/SoC according to claim 4 is characterized in that: the method that forms this second dielectric layer comprises thermal oxidation method.

6. the manufacture method that is applied to the semiconductor device of System on Chip/SoC according to claim 1 is characterized in that: the step that forms those bit lines in this memory cell areas of this substrate comprises:

Form a patterning photoresist layer at this periphery circuit region;

Carry out an ion implantation step, in this substrate that this patterning photoresist layer is exposed, implant N ⁺The type ion.

7. the manufacture method that is applied to the semiconductor device of System on Chip/SoC according to claim 1 is characterized in that: the step that forms those clearance walls at the sidewall of those grids comprises:

On this memory cell areas of this substrate and this peripheral circuit region, form a dielectric layer, and carry out an anisotropic etch process, remove this dielectric layer of part.

8. the manufacture method that is applied to the semiconductor device of System on Chip/SoC according to claim 1 is characterized in that: the step that forms this first dielectric layer and this second dielectric layer respectively at this memory cell areas and this peripheral circuit region of this substrate comprises:

In this substrate, form one first photoresist layer and cover this memory cell areas and exposed this peripheral circuit region;

In this substrate of this peripheral circuit region, form this second dielectric layer;

Remove this first photoresist layer;

In this substrate, form one second photoresist layer and cover this peripheral circuit region and exposed this memory cell areas;

In this substrate of this memory cell areas, form one first dielectric layer;

Remove this second photoresist layer.

9. manufacture method that is applied to the semiconductor device of System on Chip/SoC, it is characterized in that: this method comprises:

One substrate is provided, and this substrate comprises a memory cell areas and a peripheral circuit region, and this memory cell areas formed plurality of bit lines and one first dielectric layer, and this peripheral circuit region has formed one second dielectric layer;

This memory cell areas and this peripheral circuit region in this substrate form a plurality of grids;

In this substrate of those grid both sides of a P type MOS (metal-oxide-semiconductor) transistor device region of this peripheral circuit region, form the light doped source/drain regions of a plurality of P types, in this substrate of this memory cell areas, do not form one and resist and wear ion implantation region;

This memory cell areas and this peripheral circuit region in this substrate form one the 3rd dielectric layer, and the 3rd dielectric layer fills up the gap between those adjacent among this memory cell areas grids;

Carry out an anisotropic etching process, remove part the 3rd dielectric layer, form a plurality of clearance walls with the sidewall at those grids, wherein the 3rd dielectric layer in the gap between adjacent those grids is not removed among this memory cell areas;

Carry out an ion implantation step, in this substrate of those grid both sides of this P type MOS (metal-oxide-semiconductor) transistor device region of this peripheral circuit region, to form a plurality of P type source/drain regions.

10. the manufacture method that is applied to the semiconductor device of System on Chip/SoC according to claim 9 is characterized in that: the material of this first dielectric layer comprises the silicon oxide/silicon nitride/silicon oxide layer.

11. the manufacture method that is applied to the semiconductor device of System on Chip/SoC according to claim 10 is characterized in that: the method that forms this first dielectric layer comprises chemical vapour deposition technique.

12. the manufacture method that is applied to the semiconductor device of System on Chip/SoC according to claim 9 is characterized in that: the material of this second dielectric layer comprises silica.

13. the manufacture method that is applied to the semiconductor device of System on Chip/SoC according to claim 12 is characterized in that: the method that forms this second dielectric layer comprises thermal oxidation method.

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