CN1404118A - Method for locally forming silicide metal layer - Google Patents

Abstract

The present invention provides a method for forming a silicide layer on an integrated circuit. The method can avoid forming metal silicide on the surface of elements with high resistance value, so that the efficiency of the elements is not reduced. The method can also avoid the leakage current phenomenon caused by the formation of silicide between the memories on the same word line. The method of the present invention is mainly to form a mask on the device without forming silicide on the surface. In the space between the memories, the dielectric material is deposited to a greater thickness by design so that it is not completely removed in the subsequent etch-back step. Then, a metal layer is deposited and a heating step is performed to form silicide. Thus, the above object can be achieved.

Description

Method for locally forming metal silicide layer

field of invention

The present invention relates to a method for locally forming a metal silicide layer, in particular to a method for locally forming a metal silicide layer for avoiding the formation of a metal silicide layer on the surface of an element requiring high resistance and avoiding leakage current between memories.

Background of the invention

Generally, in order to reduce the resistance value and improve the efficiency of integrated circuits, a metal silicide layer, such as silicon titanium oxide, is often deposited on the surface of circuits and components. It is necessary to avoid the formation of metal silicide on the surface of areas that are not suitable for reducing the resistance value, such as the space between memories on the same word line, and components that require high resistance values, such as load transistors (load transistor) and electrostatic discharge (electrostatic discharge) discharge, ESD) protection device. The traditional forming method is shown in FIG. 1 : firstly, a silicon substrate 100 is provided, on which there are at least two regions: one is the array region 101 , and the other is the peripheral region 102 . In the array region 101 , there is a dielectric layer 105 , such as a silicon oxide-silicon nitride-oxide (ONO) layer, on top of the substrate 100 . On the dielectric layer 105 is a memory array composed of a plurality of memories 110 , wherein there is a first spacing region 106 between two adjacent memories 110 on the same word line. In the peripheral region 102 , there are at least a plurality of transistors 120 , and there is a second spacer region 107 between two adjacent transistors 120 . After the step of forming metal silicide, metal silicide ( 150 , 160 , 170 ) is formed on the top surface of the gate of the memory 110 , the top surface of the gate of the transistor 120 , and the surface of the silicon substrate 100 .

However, in the conventional method, in the step of forming the sidewall 130 of the memory 110 , it is often difficult to control, resulting in over-etching to expose the silicon substrate inside the first spacer region 206 , as shown in FIG. 2A . So that when the step of forming metal silicide is performed, a metal silicide layer 240 is also formed on the surface of the silicon substrate 100 in the first spacer region 206 , as shown in FIG. 2B . This will result in leakage current, which affects the performance of the memory. In addition, if there are other components on the substrate, such as load transistors or ESD protection devices, metal silicide will also be formed on the surface at the same time, which will cause problems. We have found that these undesired problems are caused by the lack of selectivity for the formation of metal silicides by conventional methods.

Contents of the invention

It is an object of the present invention to provide a method for locally forming a metal silicide layer on an integrated circuit.

Another object of the present invention is to provide a method to avoid leakage current caused by metal silicide formed between memory devices on the same word line.

Yet another object of the present invention is to provide a method for avoiding the formation of silicide on the surface of components requiring high resistance.

According to the above purpose, the method of the present invention mainly includes the following steps: first, a silicon substrate is provided, which can be divided into an array area and a peripheral area on this silicon substrate, wherein the array area includes A first dielectric layer is on the substrate and a plurality of first transistors, such as memory arrays, are on the first dielectric layer. There is a first interval region between two adjacent transistors among the plurality of first transistors. In the peripheral region, a plurality of second transistors and a plurality of semiconductor elements are located on the substrate, wherein the plurality of semiconductor elements are devices with a relatively high resistance value, and any two of the plurality of second transistors are adjacent to each other There is a second spacer region between the second transistors, and the width of the second spacer region is larger than that of the first spacer region. Then, a second dielectric layer is conformally deposited to cover the substrate, the array region, the plurality of first transistors, the peripheral region, the plurality of second transistors, and the surfaces of the plurality of semiconductor elements. Then, an etching step is performed to remove most of the second dielectric layer, and the remaining second dielectric layer only exists in the first spacer region. Then, a third dielectric layer is deposited to cover the substrate, the array region, the peripheral region, the plurality of first transistors, the plurality of second transistors, the plurality of semiconductor elements, and the second dielectric layer. layer. Afterwards, a photoresist layer is deposited to cover the third dielectric layer. Then, the photoresist layer is removed on areas where metal silicide is not to be formed, such as the plurality of semiconductor elements. Then use the remaining photoresist layer as a mask to perform another etching step to remove part of the third dielectric layer, and then the remaining third dielectric layer only exists in the first spacer region and the plurality of semiconductor elements on the surface. Afterwards, the remaining photoresist layer is removed. Then, a metal layer is deposited to cover the surface of the entire structure. A heating step is performed to form metal silicide. Finally, the metal layer and the remaining third dielectric layer are removed.

Description of drawings

1 is a schematic cross-sectional view of partially forming a metal silicide layer on an integrated circuit by a conventional method;

2A to FIG. 2B are cross-sectional schematic diagrams at various stages of an embodiment of an over-etching problem caused by a conventional method;

3A to 3L are schematic cross-sectional views at various stages of an embodiment of partially forming a metal silicide layer on an integrated circuit according to the inventive method.

Detailed ways

The present invention provides a method to form a metal silicide on a local area of an integrated circuit, which includes the following steps: first, as shown in FIG. One is the peripheral area 102 . A first dielectric layer, such as a silicon oxide-silicon nitride-silicon oxide (ONO) layer 105 is deposited on the array area 101, and a memory array is deposited on the ONO layer 105, wherein the same word line There is a first space area 306 between two adjacent memories 110 . And at least two types of components are included on the peripheral region 102: one type must reduce its surface resistance, such as a plurality of transistors 120; the other type does not need to reduce its surface resistance, such as a load transistor 302 in this embodiment and an electrostatic discharge protection (ESD) device 304 . Wherein, there is a second spacer region 307 between two adjacent transistors 120 , and the width of the second spacer region 307 is larger than that of the first spacer region 306 . In this embodiment, the distance between the gates of two adjacent memories 110 is about 0.32 microns, and the distance between the gates of two adjacent transistors 120 is about 0.40 microns. The width of the first spacing region 306 is about 0.30 microns, and the width of the second spacing region 307 is about 0.38 microns.

Afterwards, a second dielectric layer 310 such as a silicon oxide layer is conformally deposited to cover the entire surface of the array area 101 and the peripheral area 102 , as shown in FIG. 3B . The thickness of the second dielectric layer 310 is about 350 to 500 angstroms. However, the thickness of the second dielectric layer 310 in the first spacer region 306 will be thicker in other parts, because the width of the first spacer region 306 is narrower, so the speed at which the second dielectric layer 310 is deposited there will be faster. This design rule is just the difference between the present invention and traditional methods. Then, an etching step is performed to remove most of the second dielectric layer 310, leaving only the remaining second dielectric layer 310 in the first spacer region 306, as shown in FIG. 3C. Afterwards, a third dielectric layer 320 such as a silicon oxide layer is conformally deposited to cover the entire array area 101 and the surface of the peripheral area 102 , as shown in FIG. 3D . Afterwards, a photoresist layer 330 is deposited to cover the third dielectric layer 320, as shown in FIG. 3E. Then, perform pattern transfer and remove part of the photoresist layer 330 , leaving only the photoresist layer 330 above the load transistor 302 and the ESD protection device 304 , as shown in FIG. 3F . Then, using the remaining photoresist layer 330 as a mask, an etching step is performed to remove most of the third dielectric layer 320, leaving only the part of the third dielectric layer 320 covered by the photoresist layer 330, as shown in FIG. 3G is shown. Part of the third photoresist layer 320 located in the first spacer region 306 and above the second dielectric layer 310 will also partially remain due to the same effect as the aforementioned second dielectric layer 310 , as shown in FIG. 3G . Afterwards, the photoresist layer 330 is removed, as shown in FIG. 3H.

Then, deposit a metal layer 340, such as metal titanium, to cover the entire integrated circuit, as shown in FIG. 3I. A heating step is then performed to react the metal with the polysilicon to form silicide metals (342, 344, 346), which are respectively located on the gate surface of the memory 110, the gate surface of the transistor 120, and the surface of the substrate 100, as shown in FIG. 3J . However, the first spacer region 306, the load transistor 302 and the ESD protection device 304 do not form a silicide metal layer because there are dielectric layers (310, 320) thereon.

Afterwards, the metal layer 340 is removed, as shown in FIG. 3K. Finally, the second dielectric layer 320 is removed to expose the surface of the load transistor 302 and the ESD protection device 304 , as shown in FIG. 3L . The second dielectric layer 310 and the third dielectric layer 320 located in the first spacer region 306 may remain or be removed, which is not a necessary step of the present invention. In this way, the method for partially forming the metal silicide layer of the present invention is completed.

The above descriptions are only preferred embodiments of the present invention, and are not intended to limit the patent scope of the present invention; all other equivalent changes or modifications that do not deviate from the spirit disclosed in the present invention should be included in the following within the scope of the claims.

Claims (9)

1. local method that forms metal silicide layer, this method comprises the following step at least:

One silicon base material is provided, on this silicon base material, can divides into an an array zone and a neighboring area at least;

Form on the silicon base material of one first dielectric layer in this array region, and a plurality of the first transistor wherein has one first interval region between adjacent two the first transistors in these a plurality of the first transistors on this first dielectric layer;

Form on a plurality of transistor secondses this ground in this neighboring area, wherein between adjacent two transistor secondses one second interval region is arranged in these a plurality of transistor secondses, and this second interval region is greater than this first interval region;

Form on a plurality of semiconductor elements this ground in this neighboring area;

Conformally deposit one second dielectric layer to cover this ground, this array region, this neighboring area, these a plurality of the first transistors, these a plurality of transistor secondses and this a plurality of semiconductor elements;

Carry out one first etching step to remove most of this second dielectric layer, remaining this second dielectric layer is present in this first interval region;

Conformally deposit one the 3rd dielectric layer covering this ground, this array region, this neighboring area, these a plurality of the first transistors, these a plurality of transistor secondses, these a plurality of semiconductor elements, and this second dielectric layer;

Deposit a photoresist layer to cover the 3rd dielectric layer;

Remove this photoresist layer that is positioned at this a plurality of semiconductor elements top;

With this photoresist layer is a mask, carries out one second etching step to remove part the 3rd dielectric layer, and remaining the 3rd dielectric layer is positioned on this second dielectric layer and these a plurality of semiconductor elements;

Remove this photoresist layer;

Deposit a metal level to cover this silicon base material, this array region, this neighboring area, these a plurality of the first transistors, these a plurality of transistor secondses and the 3rd dielectric layer;

Carry out a heating steps to form metal silicide;

Remove this metal level, and

Remove the 3rd dielectric layer.

2. method according to claim 1, wherein said first dielectric are monoxide-nitride-oxide (ONO) layer.

3. method according to claim 1 more comprises a gate pole oxidation layer between the gate and this ground of these a plurality of transistor secondses.

4. method according to claim 1, wherein said second dielectric layer is an one silica layer.

5. method according to claim 1, wherein said the 3rd dielectric layer is an one silica layer.

6. method according to claim 1, wherein said a plurality of semiconductor elements are load transistor.

7. method according to claim 1, wherein said a plurality of semiconductor elements are electrostatic protection device.

8. method according to claim 1, wherein said a plurality of semiconductor elements comprise a load transistor and an electrostatic protection device at least.

9. method according to claim 1, wherein said metal level are layer of titanium metal.

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