CN1402330A - Generating Standard Logical Unit Database by Merging Power Lines Method - Google Patents

Abstract

The first logic unit comprises a PMOS and an NMOS, wherein a source electrode area of the PMOS is connected with a power line through a first lead wire, a source electrode area of the NMOS is connected with a ground wire through a second lead wire, a drain electrode area of the PMOS is connected with a drain electrode area of the NMOS through a third lead wire, and a grid electrode of the PMOS is connected with a grid electrode of the NMOS through a polysilicon wire. And the first logic unit is partially overlapped with the second logic unit, wherein the first lead and the second lead of the first logic unit are overlapped and correspondingly connected with the first lead and the second lead of the second logic unit.

Description

Generating a Standard Logical Cell Database Using the Combined Power Line Method

Technical field

The invention relates to a manufacturing method and design of a semiconductor element, and in particular to a method of merging power lines to generate a standard logic unit database.

Background technique

Known methods of designing integrated circuits in semiconductor design require a computer-stored database and behavioral circuit modules that scan the availability of integrated circuits. Traditional logic cells include basic logic gates such as OR, NAND, NOR, AND, XOR, converters, and also logic cells with the size of a logic gate array. These logic cells also include sequential circuit elements such as latches and flip-flops necessary for memory. The interconnections of the selected logic cells are then defined, and the selected logic cells are placed and routed to form the integrated circuit. For example, groups of logic units can be interconnected into a block as flip-flops or shift registers. Traditionally, the manufacturing process has expanded from the manufacture of one logic device to the assembly and wiring of multiple logic devices.

In terms of current manufacturing process and design technology development, the VLSI represented by the microprocessor has a trend of accelerated improvement in both efficiency and integration. Recently, the object geometry size of the device is about 0.5 micron. However, it is foreseeable that within a few years, the component size will shrink to 0.1 micron. Such tiny object sizes could allow 4.5 million transistors or 1 million logic gates to be fabricated on a 25mm-square chip. This trend will aspire to continue, to form smaller object geometries and fabricate more circuit elements on a chip, and towards wafers of increasingly larger sizes to accommodate greater quantities of circuit elements.

Because the manufacturing process requires a large number of components and actual detailed manufacturing steps, the actual design must rely on the support of computers to complete. Therefore, most stages of actual design are completed by computer-aided tools, and many stages have been partially or fully automated. The automation of the actual design process can improve integration, reduce waiting cycles and improve chip performance.

In order to operate ultra-large-scale integrated circuits with high performance and high integration, high-precision circuit design must be performed, so computer-aided design tools have played an important role in high-precision circuit design.

Afterwards, check the wiring diagram to make sure that the design meets the design requirements. Until now, design files have been nothing more than explicit specifications, known as intermediate forms, to describe wiring diagrams. The design files are then converted into pattern generator files for mask patterns generated by optical or e-beam pattern generators.

During fabrication, silicon wafers are patterned using masks and a series of lithographic processes. The formation of components requires very precise and detailed steps, including the separation between geometric figures and figures. The process of converting circuit details into wiring diagrams is called actual design. It is an extremely tedious and error-prone process due to its extremely small error tolerance requirements and extremely small individual components.

The purpose of actual design is to determine the optimal arrangement of components on the layout or in three-dimensional space, and to determine the effective interconnection or wiring diagram between components to obtain the desired effect. Since the space on the chip is very precious, designers must effectively use the space to achieve the purpose of reducing cost and increasing production capacity.

Practical design automation systems in use today are limited to placing and routing (routing) only about 20,000 components or logic cells. In order to complete the placement of a large number of logic cells, the logic cells are divided into blocks of 20,000 or less, and then the blocks are placed or routed. Since integrated circuits contain a large number of logic units, these logic units can be tens of thousands or hundreds of thousands or even millions of small logic units, and the results of the above-mentioned method and placement solution are not optimal, so this method cannot satisfy required. Each logic cell represents a single logic element, such as one or more logic elements interconnected within a standard to perform a specific function. A logic cell consisting of two or more interconnected gates or logic elements can be used as a standard module in circuit resources.

The logic unit or other above-mentioned circuit elements are interconnected or wired according to the circuit logic design to provide the required functions. The various circuit elements are interconnected via vertical and horizontal channels of the logic cells via wires or wiring coils.

In terms of actual design, the input is a circuit diagram and the output is a wiring diagram. This I/O process is accomplished through a series of stages including partitioning, layering planning, placement, routing and compression.

Separation—A chip contains millions of transistors. Wiring diagrams of the entire circuit cannot be fully implemented due to storage space limitations and limitations of the available electrical power supply. Therefore, generally, components or logic units are grouped into sub-circuits and modular blocks. The interconnection between logic cells is accomplished by complex and time-consuming and physically placed interconnection coils. The actual partitioning process takes into account many factors such as block size, number of blocks, and number of interconnects between blocks.

Delimited output is a group of blocks separated by the required interconnection between blocks. The desired interconnection group is then like a grid column. In large circuits, the separation process is usually a staged process, although a non-staged process can be utilized, and at the highest level, a circuit can have 5 to 25 blocks. However, a larger number of blocks has more potential and is also the focus of research and development. Each block is cyclically divided into smaller blocks.

Layer Planning and Placement—This step considers selecting a good layout to replace each block of the entire chip, as between blocks and to the boundaries. Hierarchical planning is a critical step as the basis for building a good wiring diagram. However, the calculation of this step is very difficult. Usually, this layered plan wiring diagram is mostly completed by design engineers with computer-aided design tools. It is usually necessary to specially design and place the main components of the integrated circuit at special positions on the chip.

Only in simple wiring diagrams, existing wiring diagram tools can provide a method that does not require human engineering direction and coordination. An aspect of the present invention may allow review issues including completion of process plan wiring diagrams without following human controls.

During placement, as shown in FIG. 1 , groups of logic cells 66 are placed and interconnected into blocks 60 , and several blocks are located on a chip (not shown). The purpose of the placement is to seek the minimum block arrangement area to allow the completion of the interconnection between the blocks. Typical placement is done in two phases. In the first phase, a starting placement is established. In the second phase, the starting placement is evaluated and iterative improvements are made until the wiring diagram has a minimum area and meets design specifications.

In order to limit the number of repetitions of the placement operation, the required routing space is evaluated concurrently with the placement phase. A good layout and circuit efficiency mainly depends on good placement calculations. Once the location of each block is fixed, only very small-scale wiring and overall circuit efficiency improvements can be made.

Routing—The purpose of the routing phase is to complete the interconnection between blocks according to a specific mesh column. First, the space not occupied by tiles, that is, the wiring space, is divided into square areas called aisles and switch boxes. The purpose of the wiring is to test the length of the coil with a short circuit and to make all the electrical connections with the channels and switch boxes.

Routing is usually done in two phases, overall wiring and detailed wiring. In global routing, the connections are made between blocks of appropriate circuits regardless of the geometric details and connections of each individual coil. For each coil, the overall wiring is done as one of the channels of the coils. That is, the overall wiring details inaccurate coil wiring through regions of different wiring spaces.

After the overall routing is detailed routing, which can complete the point-to-point connections between the connectors on the block. Inexact routing can be converted to exact routing through detailed geometric information such as line width and its layer assignment. Detailed wiring includes channel wiring as well as switch box wiring.

Due to the nature of the routing design, in many cases it is not guaranteed that a complete link routing can be achieved. Therefore, a technique called "strip and rewind" is used to remove the problematic links and reroute them into a different order.

Compression - Compression is a process that compresses the wiring pattern from all directions, so the total area will be reduced. Through the miniaturization of the chip, the line length is shortened, so that the signal delay between circuit elements can be reduced. At the same time, due to the smaller area, the number of chips that can be produced on the same wafer will be increased, thereby reducing the manufacturing cost. However, it must be ensured that there are no design criteria and violations of the manufacturing process before compression can be performed.

The actual design of VLSI is inherently iterative, and many steps, such as global routing and channel routing, are repeated many times to obtain a better layout pattern. Furthermore, the quality of the results obtained in one stage depends on the quality of the results obtained in the previous stage. For example, higher quality routing does not compensate for poor placement quality. Therefore, which step is performed first has a greater influence on the quality of the overall result.

It can be seen that layer planning and placement issues play a more important role than routing and compression in determining area and chip performance. Since placement may result in an unroutable pattern, the overall chip may need to be reset or repartitioned by removing defective blocks or replacing them with new blocks before other routing attempts are attempted. The overall design cycle is traditionally repeated a number of times to accomplish the design goals. The complexity of each step varies with design constraints and the type of design used.

How to improve the existing design, so that the semiconductor circuit design can be more accurate and the design and wiring can be completed in a relatively short period of time, so as to improve the yield and output, has become the most worthy of research.

Contents of the invention

The main purpose of the present invention is to provide an actual logic unit placement method, and effectively reduce the total area of the wiring diagram by this method.

Another object of the present invention is to provide an accurate and effective IC wiring diagram design, thereby effectively improving product yield and yield.

Yet another object of the present invention is to provide a method for generating a logic cell database by merging a logic cell power supply line having power lines with adjacent logic cells, so that coil contacts between logic cells can be eliminated, thereby effectively eliminating The complexity of forming coil contacts between logic cells.

Another object of the present invention is to provide another integrated circuit wiring diagram, so that the overall design and wiring time can be effectively shortened, the yield can be greatly increased, and the integrated circuit manufacturing cost can be greatly reduced.

In order to achieve the above object, the present invention provides a logic unit arrangement diagram, the first logic unit includes a PMOS and an NMOS, wherein the source of the PMOS is connected to the power line V _DD via a first wire, and the source of the NMOS is connected to the ground line GND The drains of the PMOS and NMOS are connected through a third wire, and the gates of the PMOS and NMOS are connected through a polysilicon wire. The first and second wires of the first logic unit and the first and second wires of the second logic unit overlap each other and are connected to each other. The configuration of these logic cells can reduce the block size, so the total area of the wiring pattern can be reduced.

Since the logic cells partially overlap, the total area of the wiring diagram can be greatly reduced.

Since the coil contacts between the logic units are removed, the complexity of forming the coil contacts between the logic units can be eliminated.

Since the complexity of forming the coil contact between the logic units is eliminated, the risk of wrong connection between the logic units can be eliminated, and thus the yield rate can be greatly improved.

Since the coil contact between the logic units is eliminated, the time delay and the total length of the coil can be greatly reduced, so the yield of the overall integrated circuit can be greatly increased, and the manufacturing cost of the integrated circuit can be significantly reduced.

Description of drawings

Fig. 1 shows a schematic arrangement diagram of a known logic unit;

Figure 2 shows a schematic diagram of a typical logic unit according to a preferred embodiment of the present invention;

Figure 3 shows a schematic diagram of a typical logic unit according to a preferred embodiment of the present invention; and

FIG. 4 shows a connection between two adjacent logic units formed by merging power lines according to a preferred embodiment of the present invention.

Detailed ways

In order to make the above and other objects, features, and advantages of the present invention more comprehensible, preferred embodiments are described in detail below in conjunction with the accompanying drawings.

Fig. 2 shows a simplified diagram of a typical logic unit according to the preferred embodiment of the present invention.

Referring to FIG. 2 , a first converter logic unit 200 includes a PMOS structure, for example, the PMOS structure has a gate, and the gate is surrounded by an N well. A contact window 202 is connected to a source region of the PMOS, and a contact window 204 is connected to a drain region of the PMOS. An NMOS structure, for example, the NMOS structure has a gate, wherein the gate is surrounded by a P-well. A contact 206 is connected to a source region of the NMOS, and a contact 208 is connected to a drain region of the NMOS. The gate of the PMOS and the gate of the NMOS are connected by a polysilicon line 210 via a plug 212 . The source region of the PMOS is connected to the power line V _DD via the wire 214 , and the source area of the NMOS is connected to the ground line GND via the wire 216 . The drain regions of the NMOS and PMOS are connected via a wire 218 . The connection port 220 is connected to the power line V _DD , and the connection port 230 is connected to the ground line GND.

Referring to FIG. 3 , a second converter logic unit 300 includes a PMOS structure, for example, the PMOS structure has a gate, and the gate is surrounded by an N well. A contact window 302 is connected to a drain region of the PMOS, and a contact window 304 is connected to a source region of the PMOS. An NMOS structure, for example, the NMOS structure has a gate, wherein the gate is surrounded by a P-well. A contact 306 is connected to a drain region of the NMOS, and a contact 308 is connected to a source region of the NOS. The gate of the PMOS is connected to the gate of the NMOS by a polysilicon line 310 via a plug 312 . The source region of the PMOS is connected to the power line V _DD through the wire 314 , and the source region of the NMOS is connected to the ground line GND through the wire 316 . The drain regions of the NMOS and PMOS are connected via a wire 318 . The connection port 320 is connected to the power line V _DD , and the connection port 330 is connected to the ground line GND.

Referring to FIG. 4 , the first converter logic unit 200 and the second converter logic unit 300 are connected by overlapping the wires 214 and 216 of the first converter logic unit and the wires 314 and 316 of the second converter logic unit, so as to A partial overlap is formed, as shown in 402 and 404 in FIG. 4 . Although the preferred embodiment uses two converter logic units to display the interconnection between the two converter logic units, in practical applications, the present invention can also be applied to making other logic units such as OR, NAND, NOR, AND , XOR, etc. The interconnection of logic cells with logic gate arrays. The placement of logic cells can reduce the block size, so the total area of the wiring diagram can be reduced.

Please refer to FIG. 1. FIG. 1 shows a schematic diagram of a known logic cell array. form. The space between the power supply line V _DD of the first logic unit and the second logic unit adjacent to the first logic unit is called "line-line spacing". For example, in a schematic diagram of a known logic cell array, the line-to-line spacing along the X direction is about 0.8 microns. Therefore, in the combined power scheme of the present invention, at least 0.8 microns of layout space can be utilized between two adjacent logic cells.

After layer planning and placement according to the invention, wiring and fabrication of integrated circuits can be performed according to known schematics.

One aspect of the present invention is that the arrangement of the logic units can be performed relatively easily and at a relatively low cost since the interconnections between the logic units are removed by merging the power supply lines V _DD and the ground lines GND between the logic units. less time. Defective logic cells can be easily removed because the placement step results in a simpler wiring diagram. Therefore, the entire chip does not need to be replaced or repartitioned to remove defective logic cells or replace with new blocks before performing other steps. Therefore, the output can be effectively increased, and the cost can be greatly reduced.

Another aspect of the present invention is that since the interconnection between the logic units is removed by merging the power line V _DD and the ground line GND, the known time-consuming design and manufacture of the interconnection can be avoided. Therefore, the output can be effectively increased, and the cost can be greatly reduced.

Since the logic cells partially overlap, the total area of the wiring diagram can be greatly reduced.

Since the coil contacts between the logic units are removed, the complexity of forming the coil contacts between the logic units can be eliminated.

Since the complexity of forming the coil contact between the logic units is eliminated, the risk of wrong connection between the logic units can be eliminated, and thus the yield rate can be greatly improved.

Since the coil contact between the logic units is eliminated, the time delay and the total length of the coil can be greatly reduced, so the yield of the overall integrated circuit can be greatly increased, and the manufacturing cost of the integrated circuit can be significantly reduced.

In a preferred embodiment of the present invention, two converter logic units are used to display the interconnection between the two converter logic units. However, in practical applications, the present invention can also be applied to manufacture more than two converter logic units.

The preferred embodiment of the present invention uses the converter logic unit to display the interconnection between logic units, but in practical applications, the present invention can also be applied to other logic units such as OR, NAND, NOR, AND, XOR, etc. The interconnection of the logic cells of the logic gate array.

Although the present invention has been disclosed as above with a preferred embodiment, it is not intended to limit the present invention, and any person skilled in the art can make various modifications and modifications without departing from the spirit and scope of the present invention. , so the scope of protection of the present invention depends on the appended claims.

Claims (6)

1. the one kind high actual laying method that meticulous logical block is placed is used for a design of integrated circuit, and it comprises:

One first logical block is provided, this first logical block comprises a PMOS and a NMOS, wherein the one source pole district of this PMOS is connected via one first lead with a power line, the one source pole district of this NMOS is connected via one second lead with a ground wire, the drain region of this PMOS is connected via a privates with the drain region of this NMOS, and the grid of this PMOS is connected via a polysilicon lines with the grid of this NMOS;

One second logical block is provided, this second logical block comprises a PMOS and a NMOS, wherein the one source pole district of this PMOS is connected via one first lead with a power line, the one source pole district of this NMOS is connected via one second lead with a ground wire, the drain region of this PMOS is connected via a privates with the drain region of this NMOS, and the grid of this PMOS is connected via a polysilicon lines with the grid of this NMOS;

This first logical block of overlapping and this second logical block, wherein this of this first logical block first first is connected with this second lead is overlapping and corresponding with this of this second lead and this second logical block; And

Separate and wiring.

2. the actual laying method that the meticulous logical block of height as claimed in claim 1 is placed, wherein this first logical block and this second logical block comprise a transducer.

3. the actual laying method that the meticulous logical block of height as claimed in claim 1 is placed, wherein this first logical block and this second logical block comprise OR, NAND, NOR, one of them main gate of AND and XOR.

4. the one kind high actual displacement structure that meticulous logical block is placed is used for a design of integrated circuit, and it comprises:

One first logical block, this first logical block comprises a PMOS and a NMOS, wherein the one source pole district of this PMOS is connected via one first lead with a power line, the one source pole district of this NMOS is connected via one second lead with a ground wire, the drain region of this PMOS is connected via a privates with the drain region of this NMOS, and the grid of this PMOS is connected via a polysilicon lines with the grid of this NMOS; And

One second logical block, this second logical block comprises a PMOS and a NMOS, wherein the one source pole district of this PMOS is connected via one first lead with a power line, the one source pole district of this NMOS is connected via one second lead with a ground wire, the drain region of this PMOS is connected via a privates with the drain region of this NMOS, the grid of this PMOS is connected via a polysilicon lines with the grid of this NMOS, this first logical block and this second logical block are overlapped, and wherein this of this first logical block first first is connected with this second lead is overlapping and corresponding with this of this second lead and this second logical block.

5. the actual displacement structure that the meticulous logical block of height as claimed in claim 4 is placed, wherein this first logical block and this second logical block comprise a transducer.

6. the actual displacement structure that the meticulous logical block of height as claimed in claim 4 is placed, wherein this first logical block and this second logical block comprise OR, NAND, NOR, one of them main gate of AND and XOR.

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