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CN1402140A - Device for switching from non-software drive memory interface to software drive interface - Google Patents

Device for switching from non-software drive memory interface to software drive interface Download PDF

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Publication number
CN1402140A
CN1402140A CN 02115102 CN02115102A CN1402140A CN 1402140 A CN1402140 A CN 1402140A CN 02115102 CN02115102 CN 02115102 CN 02115102 A CN02115102 A CN 02115102A CN 1402140 A CN1402140 A CN 1402140A
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Prior art keywords
interface
floppy drive
data
sl11h
processor
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CN 02115102
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Chinese (zh)
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CN1151443C (en
Inventor
李晋宁
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Shenzhen enrich Technology Co. Ltd.
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SHENZHEN YINGNING CO Ltd
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Publication of CN1402140A publication Critical patent/CN1402140A/en
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Publication of CN1151443C publication Critical patent/CN1151443C/en
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Abstract

A device for converting the non-diskette drive interface to diskette drive interface is composed of a memory with different interface for outputting data signals, a SL11H interface connected to said memory for providing the entry addresses of program register and daa register for data conversion and transmission, a processor containing a memory and connected to said SL11H interface for receiving its data, processing it and storing it in memory, and a diskette drive. Its advantages are simple structure, and low cost.

Description

Non-floppy drive memory interface is converted to the device of floppy drive interface
Technical field the present invention relates to the data conversion technique between a kind of different pieces of information interface, relates in particular to a kind of technology that various storage medium interfaces is converted to floppy drive interface.
3.5 inches floppy disks that background technology is generally used in the market are capacity or speed all finalizes the design almost before the more than ten years, from then on not development again, it exists that consume system resources is excessive, limited storage space, speed wait shortcoming too slowly, and in recent years, hard disk is obtained high capacity, high-speed fast-developing, and USB (universal serial bus) (USB) is a kind of simple computer external interface standard.It has advantages such as plug and play, expansion be convenient, and computer peripheral equipment is placed on the cabinet outside, and the trouble that saved in the computing machine draw-in groove and be installed, reconfigure system, restarts has become an interface of computing machine indispensability.But in a lot of fields, especially come the opertaing device major part of parts such as each Industrial Control Computer, Medical Devices, teaching equipment, the military equipment industry mechanism of Data transmission to have floppy drive by floppy disk or floppy disk is used in requirement, this part industrial control equipment still is necessary to the demand of floppy drive, but will be under the trend that general-purpose computer and other field are eliminated at floppy drive, will have floppy drive or requirement and use the opertaing device of the industry mechanism of floppy disk and upgrade again and will bring tremendous loss to society.
Summary of the invention the purpose of this invention is to provide a kind of simple in structure, device that various storage medium interfaces that cost is low, easy to operate are converted to floppy drive interface.
The present invention is achieved in that the present invention includes one can be the storer of distinct interface, be used to export various data-signal, the SL11H interface that is connected with storer provides the entry address of program register and data register, is used for data-switching and transmission; The processor that comprises an internal memory that is connected with the SL11H interface, the data that receive the SL11H interface are handled and are stored in the internal memory; Processor connects a floppy drive interface.
The data transmission of SL11H interface is by the realization that is connected with memory interface of two difference mode signal lines of D+ and D-.
The present invention also comprises a crystal oscillator clock, the time of control data transmission.
The present invention also comprises a transceiver/impact damper, be used to guarantee processor and floppy drive interface between the driving force of data transfer.
Processor connected with being connected by data line, address wire, look-at-me line of SL11H interface.
Be connected a floppy drive with floppy drive interface.
After adopting technique scheme, solve the difficulty on traditional floppy disk and the mobile memory exchanges data now, both satisfied the transmission of mass data, needn't do very big change to the existing product structure again, simple in structure, cost is low, easy to operate.Needn't the equipment that 3.5 cun floppy disks of any needs such as Weaving device, IT product, monitoring device carry out the data I/O be improved, can use various hard disks to carry out data transmission.
The invention will be further described below in conjunction with accompanying drawing and concrete embodiment for description of drawings.
Fig. 1 is a structured flowchart of the present invention;
Fig. 2 is a SL11H interface structure block diagram of the present invention;
Fig. 3 is usb data transfer process figure;
Fig. 4 is a processor software process flow diagram of the present invention.
Embodiment as shown in Figure 1, the present invention includes one can be the storer of distinct interface, is used to export various data-signal, and a SL11H interface is connected with storer, the entry address of program register and data register is provided, is used for data-switching and transmission; The processor that comprises an internal memory that is connected with the SL11H interface, the data that receive the SL11H interface are handled and are stored in the internal memory; Processor connects a floppy drive interface.
The data transmission of SL11H interface is by the realization that is connected with memory interface of two difference mode signal lines of D+ and D-.
The present invention also comprises a crystal oscillator clock, the time of control data transmission.
The present invention also comprises a transceiver/impact damper, be used to guarantee processor and floppy drive interface between the driving force of data transfer.The impact damper of using always has unidirectional 74LS244,74HCT244,74HCT240 etc., two-way have a 74LS245,74HC245,74HC242 etc., bidirectional buffer also is a transceiver, its pin of kind of different company's exploitation describes and function can be different, but generally speaking comprise the I/O pin, gate control such as direction control, I/O control pin etc., its function is in order to guarantee the driving force of processor, because the transmittance process of data is arranged between processor and floppy drive interface, this just needs the device of an assurance processor driving force.
As shown in Figure 2, processor connected with being connected by data line, address wire, look-at-me line of SL11H interface.
Be connected a floppy drive with floppy drive interface, be convenient to not have the equipment use of floppy drive.
With the USB hard disk is example, introduces formation of the present invention and principle of work in detail,
The signal wire of USB interface is connected with the respective signal line of USB interface device SL11H, processor one termination SL11H, one termination floppy drive interface, so far form the data transmission network of a decussate texture, data from the USB dish are stored in the processor memory through SL11H earlier, processor carries out exchanges data with floppy drive interface again, finishes the information transmission of coiling terminal machine from USB.● USB interface and USB device:
The USB dish adopts USB interface, USB interface is 4 " pins ", USB comes transmission signals and power supply by a quadded cable, wherein D+ and D-are the signal wires of a pair of differential mode, VBus and GND then provide+power supply of 5V, it comprises the Hub power supply can for some equipment, and the pin number of USB interface all lacks than serial ports, parallel port, game port.
The process of usb data transmission as shown in Figure 3,
1) hardware device of USB physical equipment at some useful terminal user functions of the terminal execution of USB cable.
2) device driver is carried out the program that is equivalent to USB device on main frame.This client software uses separately by the operating system support or by USB device.
3) the USB system software is supported USB software on special operating system.Do not rely on special USB device or client software by the operating system support.
4) the USB master controller allows USB device to be attached to the hardware and software of main frame.
On physical arrangement, the USB system is a star structure; Logically, the transmission of usb data is undertaken by pipeline.The USB system software is by default pipeline (corresponding with end points 0) management equipment, and device driver is come the functional interface of management equipment by other pipeline.Actual data transmission procedure is as follows: device driver is by sending input-output device request (IRP) to calling of USBD interface; After the USB driver is received request, call the HCD interface, IRP is converted into the transmission of USB, an IRP can comprise one or more USB transmission; HCD is decomposed into bus operation with the USB transmission then, is sent with the form of packing by primary processor.All data transmission are all begun by main frame, and any peripheral hardware all haves no right to begin a transmission.Each USB logical device all is directly to link to each other with USBHOST to carry out data transmission.On usb bus, every ms transmits 1 frame data.Every frame data can be made up of the transmission course of a plurality of packets.USB device can judge whether to respond this data transmission according to the address information in the packet.
Floppy drive will experience following a series of initialization operation from looking for data write:
1) FDD controller sends the selection signal #DS (" # " expression low level is effective) of driver and the enabling signal #MOTORON of motor according to Host Command to floppy drive.When driver was selected, spindle motor began rotation, and the #DS signal produces an internal control signal after driver is selected circuit conversion: dish selected signal #DS, use for internal drive control.The #DS signal is opened following gate circuit: index circuit, zero track testing circuit, write-protect circuit, tracking positioning control circuit, read/write circuit.
2) when inserting disc and Down Drive storehouse box behind the door, disc will be with the spindle motor quick rotation.Then, floppy drive sends 3 status signals to FDD controller: index signal #INDEX, 0 magnetic track detection signal #TRACK00 signal and write protect signal #WRT PROTECT.
3) FDD controller detects respectively above-mentioned 3 control signals.Whether effective according to the #TRACK00 signal, send tracking and detect instruction.When the #TRACK00 signal is effective, send out #DIRECTION (direction) useful signal.Send #STEP (stepping) control signal again, i.e. several negative pulses, (number of negative pulse is identical with the track number of floppy disk).Make magnetic head along radial direction to the core stepping, make it to reach maximum track location, then direction controller signal #DIRECTION becomes high level (invalid), the negative pulse that stepping control signal #STEP sends out quantity more same makes magnetic head again to " 0 magnetic track " addressing.When " 0 magnetic track " detection signal #TRACK00 low level, tracking detects and finishes.
4) after the road detected correctly, FDD controller inserted read operation.According to the #INDEX index pulse signal, seek the sector at specified file place, and it is read in internal memory.
5) when FDD controller detects write protect signal #WRT PROTECT and is high level (promptly invalid), allow to carry out write operation.
The present invention is equally applicable to other various memory devices, or without USB interface, but multi-purpose computer directly is connected with the SL11H interface, and wherein D+ and D-are the signal wires of a pair of differential mode, are used for transmitting data, link to each other with processor by data line again, processor has an internal memory, is used for storing data, and processor links to each other with FDD controller by data line, perhaps, directly link to each other with the floppy drive data line interface of industrial control equipment by data line without floppy drive.Various memory devices need connect a ground wire; The effect of crystal oscillator clock is exactly to control each unit to work simultaneously, not the generation time error; The existing introduction above the SL11H interface; Processor is meant the core cell of this Simulation drive device that is embedded with software; FDD controller promptly is existing general floppy drive driver
At first read in various data by various memory devices (as USB), be transferred to the SL11H interface by D+ or D-two signal line, the SL11H interface mainly is that serial data is converted to the discernible parallel data of processor, parallel data is delivered to processor again, processor is through data processing (realizing by the software that is embedded in wherein), data storage in internal memory, or is delivered to FDD controller by data line, regeneration floppy disk or be delivered to the data-interface of industrial control equipment by data line.This process is all finished under the unified control of crystal oscillator clock.
Principle of work of the present invention:
1) SL11H provides the entry address of program register and data register with suitable control line by 8 bit data mouths, both can be applied in multithreading data, address bus, can be applied to single-threaded data, address bus again.When being used to need the application system of multithreading support, SL11H enters the mouth with ALE control input, reading and writing order input internal register; When being used for the system of single-threaded support, if address selection A0 is low level (A0=0), internal register addresses writes SL11H by I/O mouth line, if address selection A0 is high level (A0=1), by I/O mouth read/write data.
2) processor is connected with USB interface by USB interface device SL11H, and SL11H defers to the USB1.1 standard, supports two kinds of patterns of host/device end, comprises 256 bytes of memory devices in the sheet.Signal from the USB dish is kept among the SARM of SL11H according to the USB interface agreement earlier, and then processor and SL11H carry out message exchange, and the data storage among the SL11H is in processor memory.Because SL11H adopts the crystal oscillator of 48MHZ (PIN13,14), so it must be by the processor coupling of two-stage d type flip flop conversion ability and 12HMHZ, other main pin connects as follows:
Processor SL11H
REST
Figure A0211510200091
nRST
IRQ INTRQ
D0~D7
Figure A0211510200093
D0~D7
A0 A0
-
IOR nRD
-
IOW
Figure A0211510200096
nWR
-CS nCS
The a pair of difference mode signal line D+ of USB is connected with DATA-with the DATA+ of SL11H respectively with D-.
3) processor is connected with floppy drive interface by transceiver/impact damper, floppy drive processor.The information that is stored in the processor memory mails to computer control system according to the agreement of general floppy drive interface, carries out control command.
The function of processor of the present invention is carried out by software, the major function of software just is the conversion and the transmission of data, widespread use at present, as exchanges data between present computer hard disc and the floppy drive and transmittance process, computer can be read into the data in the floppy disk the hard disk from floppy drive, also can be with the regeneration floppy disk in the floppy drive of the data transfer in the hard disk.
Processor software design cycle of the present invention as shown in Figure 4;
1) working equipment resets, USB interface, floppy drive interface, processor initialization;
2) whether processor detects to have and interrupts producing, if do not interrupt producing, carries out flow process 4); Interrupt producing if having, carry out flow process 3);
3) judge which kind of this interruption belongs to:, then should respond in succession and be provided with that order → send state information → announcement sends datagram if USB interrupts; If outer the interruption then answered monitor equipment status → generation data report;
4) judged whether that data will send,, then be back to flow process 1) if do not have; If have, carry out flow process 5);
5) with flow process 3) data report of gained deposits the USB buffer zone in, is provided with to send the position and wait for that a USB interrupts;
6) the USB buffer data is sent in the storer of SL11H;
7) with the data storage in the storer in processor memory;
8) processor and floppy drive interface are carried out data transfer, directly the control computer device systems;
9) be back to flow process 1), the work of beginning next round.

Claims (6)

1, non-floppy drive memory interface is converted to the device of floppy drive interface, including one can be the storer of distinct interface, be used to export various data-signal, it is characterized in that: a SL11H interface is connected with storer, the entry address of program register and data register is provided, is used for data-switching and transmission; The processor that comprises an internal memory that is connected with the SL11H interface, the data that receive the SL11H interface are handled and are stored in the internal memory; Processor connects a floppy drive interface.
2, non-floppy drive memory interface according to claim 1 is converted to the device of floppy drive interface, it is characterized in that: the data transmission of SL11H interface is by the realization that is connected with memory interface of two difference mode signal lines of D+ and D-.
3, non-floppy drive memory interface according to claim 1 and 2 is converted to the device of floppy drive interface, it is characterized in that: the present invention also comprises a crystal oscillator clock, the time of control data transmission.
4, non-floppy drive memory interface according to claim 1 and 2 is converted to the device of floppy drive interface, it is characterized in that: the present invention also comprises a transceiver/impact damper, be used to guarantee processor and floppy drive interface between the driving force of data transfer.
5, non-floppy drive memory interface according to claim 1 is converted to the device of floppy drive interface, it is characterized in that: processor connected with being connected by data line, address wire, look-at-me line of SL11H interface.
6, be converted to the device of floppy drive interface according to claim 1 or 2 or 5 described non-floppy drive memory interfaces, it is characterized in that: be connected a floppy drive with floppy drive interface.
CNB021151024A 2002-04-19 2002-04-19 Device for switching from non-software drive memory interface to software drive interface Expired - Fee Related CN1151443C (en)

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Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN100334573C (en) * 2003-11-27 2007-08-29 联想(北京)有限公司 Apparatus and method for data exchange based on computer and USB device
US7426632B2 (en) 2005-03-31 2008-09-16 Intel Corporation Clock distribution for interconnect structures
US9363203B2 (en) 2005-03-31 2016-06-07 Intel Corporation Modular interconnect structure
CN108182164A (en) * 2017-11-30 2018-06-19 北京时代民芯科技有限公司 The SoC interface circuit and access method that a kind of data address is adaptively converted

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN100334573C (en) * 2003-11-27 2007-08-29 联想(北京)有限公司 Apparatus and method for data exchange based on computer and USB device
US7426632B2 (en) 2005-03-31 2008-09-16 Intel Corporation Clock distribution for interconnect structures
US9363203B2 (en) 2005-03-31 2016-06-07 Intel Corporation Modular interconnect structure
CN108182164A (en) * 2017-11-30 2018-06-19 北京时代民芯科技有限公司 The SoC interface circuit and access method that a kind of data address is adaptively converted
CN108182164B (en) * 2017-11-30 2020-03-20 北京时代民芯科技有限公司 SoC interface circuit for data address self-adaptive conversion and access method

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