CN1497698A - Fault analytical method - Google Patents
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- CN1497698A CN1497698A CNA200310102909XA CN200310102909A CN1497698A CN 1497698 A CN1497698 A CN 1497698A CN A200310102909X A CNA200310102909X A CN A200310102909XA CN 200310102909 A CN200310102909 A CN 200310102909A CN 1497698 A CN1497698 A CN 1497698A
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Abstract
A failure analysis device and a failure analysis method which enable easily a specification of a position of a failure point which is obtained from a back side upon a wiring pattern image which is obtained from a front side is provided. Part of a light (51a) which is irradiated upon a front surface of an analyzed wafer (100) is reflected from a metal wiring, and is taken as a first wiring pattern image which is a reflect image of the analyzed wafer (100) by the CCD (11). An infrared light component of the light (51a) which passes a gap between the metal wiring is taken as a second wiring pattern image which is a transmission image of the analyzed wafer (100) by an infrared light detector (12). Besides, the infrared light detector (12) also takes a failure light emission image by a failure point.
Description
Technical field
The present invention relates to the accident analysis of semiconductor integrated circuit, specifically, relate to the technology of the position of the localization of faults.
Background technology
In the past, as the semiconductor failure analytical method of the bad point (fault point) that detects semiconductor integrated circuit, radiometric analysis was widely known by the people.Radiometric analysis is by detecting the analytical method that the faint light that takes place because of the leakage of the electric current in the fault point is taken the picture of fault point and determined the position of this fault point.
On the other hand, be accompanied by the integrated of in recent years semiconductor integrated circuit, the multiple stratification of metallic wiring layer also further develops.Because metal wiring transmitted light not, thereby for example luminous in the metallic wiring layer of lower floor or the semiconductor element it under is difficult to observe from the face side of the wafer that forms semiconductor chip.Thereby, be conceived to the fact of the above infrared light of silicon transmissive wavelength 1 μ m, the infrared light component that light comprised that sends from silicon chip rear side (rear side of wafer) detection failure point and the gimmick (back side radiometric analysis) (for example, patent documentation 1) of detection failure point have been proposed.
[patent documentation 1]
The spy opens 2001-33526 communique (4-5 page or leaf, 1-3 figure)
[problem that invention solves]
Behind the radiometric analysis detection failure point of the back side, carry out physical analysis to find out the reason of fault, this analysis is carried out in the face side of semiconductor device usually.Thereby the position of correct definite luminous point seems very important on the Wiring pattern picture of taking from the face side of device.
In traditional back side radiometric analysis, the Wiring pattern of the luminous picture of the fault point of taking by superimposed rear side from wafer and the device taken from the rear side of wafer equally looks like to determine the position of should unusual (fault) putting.Thereby, in the time must determining the position of unusual (fault) point from the Wiring pattern picture that the face side of device is taken, at first, as above-mentioned patent documentation 1, the use cad tools waits the layout of proofreading Wiring pattern and the Wiring pattern picture of taking from rear side, determines the position of the fault point on the layout for the time being earlier.Then, Wiring pattern picture and layout that check and correction is taken from face side, the position of definite fault point from the Wiring pattern picture of face side shooting.
Like this, when the position of the definite fault point of taking from the back side of the Wiring pattern picture of taking from the surface, must proofread operation by elder generation and layout, operation is trouble quite.
The present invention, in view of the solution of above problem, its purpose can easily be determined from the fail analysis device and the failure analysis methods of the position of the fault point that the rear side of wafer obtains on the Wiring pattern picture of obtaining from face side for providing.
Summary of the invention
Failure analysis methods according to one aspect of the invention comprises: the operation that (a) includes the 1st light of the component more than the wavelength 1 μ m to the surface irradiation of the semiconductor chip that becomes analytic target; (b) promptly the 1st Wiring pattern picture and transmission picture are the operation of the 2nd Wiring pattern picture to take reflection image that above-mentioned the 1st light by above-mentioned semiconductor chip forms; (c) take the operation of the luminous picture that the fault point by above-mentioned semiconductor chip forms from above-mentioned semiconductor chip backside side.It is characterized in that above-mentioned the 2nd Wiring pattern picture and above-mentioned luminous picture are taken with same video camera.
Failure analysis methods according to a further aspect of the present invention, comprise: (a) include the laser beam of the component more than the wavelength 1 μ m to the semiconductor chip scanning that becomes analytic target and irradiation, promptly the 1st Wiring pattern picture and reflection image are the operation of the 2nd Wiring pattern picture to take transmission picture that the above-mentioned laser beam by above-mentioned semiconductor chip forms; (b) operation of the picture of the fault point of the above-mentioned semiconductor chip of shooting.It is characterized in that, above-mentioned operation (a) is carried out by the 1st video camera of the face side configuration of above-mentioned semiconductor chip and the 2nd video camera of rear side configuration, above-mentioned operation (b) is carried out by the 3rd video camera of above-mentioned semiconductor chip backside side configuration, reach (b) before in above-mentioned operation (a), calibrate the position of above-mentioned the 2nd video camera and above-mentioned the 3rd video camera.
Description of drawings
Fig. 1 is the pie graph of the fail analysis device of embodiment 1.
Fig. 2 is the key diagram of action of the fail analysis device of embodiment 1.
Fig. 3 is the pie graph of the fail analysis device of embodiment 2.
Fig. 4 is the key diagram of action of the fail analysis device of embodiment 2.
Fig. 5 is the pie graph of the fail analysis device of embodiment 3.
Fig. 6 is the pie graph of the fail analysis device of embodiment 4.
Fig. 7 is the pie graph of the fail analysis device of embodiment 5.
Fig. 8 is the pie graph of the fail analysis device of embodiment 5.
[explanation of symbol]
1 wafer chuck, 2 wafer station, 3 probes, 4 probe, 51 the 1st light sources, 52 the 2nd light sources, 61,62 half-reflecting mirrors, 71,72 lens optical systems, 11CCD, 12,21,22,31,32,33,42 infrared light detectors, 100 analyzed wafers.
Embodiment
Fig. 1 is the pie graph of the fail analysis device of embodiments of the invention 1.Shown in this figure, the wafer chuck 1 that has been used for fixing as the formation of analytic target the analyzed wafer 100 of semiconductor chip is installed in the horizontal direction movably on the wafer station 2.Wafer chuck 1 is generally formed by quartz glass.The probe 3 that the chip of analyzed wafer 100 is carried out the input and output of voltage signal is fixed on the probe 4.
The 1st light source 51 and the 2nd light source 52 send the light that comprises the above infrared light component of wavelength 1 μ m, for example Halogen lamp LED.The light 51a of the 1st light source 51 radiation via the lens optical system 71 that is used to enlarge/dwindle analyzed area (visual field), shines analyzed wafer 100 from face side with half-reflecting mirror 61 reflections.
Fig. 2 is the key diagram of action of the fail analysis device of present embodiment, is the amplification sectional view of the analyzed area of analyzed wafer 100 and wafer chuck 1.Here, suppose that the analyzed wafer 100 shown in this figure has multilayered wiring structure.Shine metal wiring 103 reflections of a part of light 51a on the surface of analyzed wafer 100 by forming on the device cambium layer 102 of analyzed wafer 100.Then, incide CCD11 via lens optical system 71, half-reflecting mirror 61, the reflection image of being taken analyzed wafer 100 by CCD11 is the 1st Wiring pattern picture.That is, the 1st Wiring pattern similarly is the Wiring pattern picture of taking from the surface of analyzed wafer 100.
In addition, without metal wiring 103 reflections, the infrared light component transmission silicon chip 101 of the light 51a in the gap by metal wiring 103, incide infrared light detector 12 via wafer chuck 1, lens optical system 72, half-reflecting mirror 62, the transmission picture of being taken analyzed wafer 100 by infrared light detector 12 is the 2nd Wiring pattern picture.That is, the 2nd Wiring pattern similarly is the Wiring pattern picture of taking from the back side of analyzed wafer 100.
On the other hand, the light 52a that the 2nd light source 52 sends shines analyzed wafer 100 via lens optical system 72 and wafer chuck 1 from rear side with half-reflecting mirror 62 reflections.Lens optical system 72 has the filter that only allows the infrared light component of light 52a pass through when enlarging/dwindling analyzed area (visual field).
Shine the silicon chip 101 of the analyzed wafer 100 of infrared light component transmission of light 52a at the back side of analyzed wafer 100, arrive device cambium layer 102.Its part is by metal wiring 103 reflections that form on the device cambium layer 102.Then, incide infrared light detector 12 via silicon chip 101, wafer chuck 1, lens optical system 72, half-reflecting mirror 62, the reflection image of being taken analyzed wafer 100 by infrared light detector 12 is the 3rd Wiring pattern picture.That is, the 3rd Wiring pattern similarly is the Wiring pattern picture of taking from the back side of analyzed wafer 100.
In addition, infrared light detector 12 also is used for the detection of the fault point of analyzed wafer 100.As if the voltage signal that is applied regulation by the chip of probe 3 on analyzed wafer 100, then fault point 110 is leaked luminous because of electric current.The infrared light component 110a of this light is via silicon chip 101, wafer chuck 1, lens optical system 72, half-reflecting mirror 62 incident infrared light detectors 12, taken the picture (below, claim " the luminous picture of fault ") of fault points by infrared light detector 12.
In addition, because a little less than fault point luminous atomic, infrared light detector 12 must have high luminous sensitivity.But, when adopting light source 51,52 to carry out the shooting of Wiring pattern picture, compare with the luminous picture of fault, very strong light incident infrared light detector 12, thereby, must regulate to suppress luminous sensitivity.
As more than, it is the 1st Wiring pattern picture that CCD11 takes the Wiring pattern picture of taking from the surface of analyzed wafer 100, and the Wiring pattern picture that infrared light detector 12 shootings are taken from the back side of analyzed wafer 100 i.e. the 2nd Wiring pattern picture, the 3rd Wiring pattern picture and the luminous picture of fault.
Because luminous picture of fault and the 2nd Wiring pattern picture and the 3rd Wiring pattern picture are taken by same infrared light detector 12, thereby, carry out the calibration of mutual alignment easily, so that both analyzed areas (visual field) unanimity.In addition, the 1st Wiring pattern similarly is the reflection image from the surface, thereby, can obtain the Wiring pattern picture of the multilayer wired at least the superiors from the 1st Wiring pattern picture.In addition, because the 2nd Wiring pattern similarly is the transmission picture, wherein also comprise the Wiring pattern picture of the multilayer wired the superiors.Thereby looking like with the Wiring pattern of the superiors is benchmark, and the position correction of the 1st Wiring pattern picture and the 2nd Wiring pattern picture also carries out easily.
Thereby according to present embodiment, the 1st Wiring pattern picture of taking from the face side of analyzed wafer 100 and the position correction of the luminous picture of fault can easily carry out.That is, can easily determine from the position of the fault point that rear side is taken at the Wiring pattern picture of obtaining from face side.
Embodiment 2
Among the embodiment 1, adopted CCD, then replaced in the present embodiment with infrared light detector as the means of taking the Wiring pattern picture from the surface of analyzed wafer 100.That is, as shown in Figure 3, the fail analysis device of present embodiment possesses the 1st infrared light detector 21 and the 2nd infrared light detector 22.In addition, among Fig. 3, enclose prosign with the key element that Fig. 1 is same, thereby detailed here.
Fig. 4 is the action specification figure of the fail analysis device of present embodiment, is the enlarged cross section figure of the analyzed area of analyzed wafer 100 and wafer chuck 1.The light 51a of the 1st light source 51 radiation shines analyzed wafer 100 via lens optical system 71 from face side with half-reflecting mirror 61 reflections.Lens optical system 71 has the filter that only allows the infrared light component of light 51a pass through.
Shine metal wiring 103 reflections that form on the device cambium layer 102 of a part by analyzed wafer 100 of infrared light component of light 51a on surface of analyzed wafer 100.Then, via lens optical system 71, half-reflecting mirror 61 incidents the 1st infrared light detector 21, the reflection image of being taken analyzed wafer 100 by the 1st infrared light detector 21 is the 1st Wiring pattern picture.
In addition, the infrared light component transmission silicon chip 101 of the light 51a in the gap by metal wiring 103, via wafer chuck 1, lens optical system 72, half-reflecting mirror 62 incidents the 2nd infrared light detector 22, the transmission picture of being taken analyzed wafer 100 by the 2nd infrared light detector 22 is the 2nd Wiring pattern picture.
On the other hand, the light 52a that the 2nd light source 52 sends shines analyzed wafer 100 via lens optical system 72 and wafer chuck 1 from rear side with half-reflecting mirror 62 reflections.
The part of infrared light component of light 52a at the back side of shining analyzed wafer 100 is by 103 reflections of the metal wiring that forms on the device cambium layer 102.Via silicon chip 101, wafer chuck 1, lens optical system 72, half-reflecting mirror 62 incidents the 2nd infrared light detector 22, the reflection image of taking analyzed wafer 100 by the 2nd infrared light detector 22 i.e. the 3rd Wiring pattern picture by the infrared light component of the light 52a of metal wiring 103 reflection.
The infrared light component of the light 52a in the gap by metal wiring 103 is via lens optical system 71, half-reflecting mirror 61 incidents the 1st infrared light detector 21, and the transmission picture of taking analyzed wafer 100 by the 1st infrared light detector 21 i.e. the 4th Wiring pattern picture.
In addition, the 2nd infrared light detector 22 is same with the infrared light detector 12 among the embodiment 1, takes the luminous picture of fault of the fault point of analyzed wafer 100.
As more than, it is the 1st Wiring pattern picture and the 4th Wiring pattern picture that the 1st infrared light detector 21 is taken the Wiring pattern picture of taking from the surface of analyzed wafer 100, and the Wiring pattern picture that 22 shootings of the 2nd infrared light detector are taken from the back side of analyzed wafer 100 i.e. the 2nd Wiring pattern picture, the 3rd Wiring pattern picture and the luminous picture of fault.
Because luminous picture of fault and the 2nd Wiring pattern picture and the 3rd Wiring pattern picture are taken by same infrared light detector 12, thereby their position correction carries out easily.In addition, the 1st Wiring pattern similarly is the reflection image from the surface, thereby can obtain the Wiring pattern picture of the multilayer wired at least the superiors from the 1st Wiring pattern picture.Because the 3rd Wiring pattern similarly is the reflection image from the back side, thereby can obtain multilayer wired at least undermost Wiring pattern picture from the 3rd Wiring pattern picture.On the other hand, because the 2nd Wiring pattern picture and the 4th pattern image are the transmission pictures, thereby they also comprise the multilayer wired the superiors, orlop two sides' Wiring pattern picture.Thereby looking like with the superiors or undermost Wiring pattern is benchmark, and they can easily carry out the calibration of mutual alignment.
Thereby,, can carry out the 1st Wiring pattern picture taken from the face side of analyzed wafer 100 and the position correction of the 4th Wiring pattern picture and the luminous picture of fault easily according to present embodiment.That is, determine from the position of the fault point that rear side is taken at the Wiring pattern picture of obtaining from face side easily.In addition, owing to can obtain the 1st Wiring pattern picture and the 4th Wiring pattern picture as the Wiring pattern picture of obtaining from face side, thereby, can determine the position more accurately than embodiment 1 by they are proofreaded mutually.
Fig. 5 is the pie graph of the fail analysis device of embodiment 3.Among this figure, enclose prosign, omit detailed explanation here with the key element that Fig. 1 is same.In the present embodiment,, adopt from the back side to the laser optical system 53 of analyzed wafer 100 scannings and illuminating laser beam 53a as light source in order to the Wiring pattern picture that obtains analyzed wafer 100.The laser beam 53a that laser optical system 53 sends comprises the above infrared light component of wavelength 1 μ m.
The laser beam 53a that sends from laser optical system 53 arrives analyzed wafer 100 via half-reflecting mirror 62, lens optical system 72, wafer chuck 1.Infrared light component by the metal wiring 103 laser light reflected bundle 53a in the analyzed wafer 100 incides the 2nd infrared light detector 32.On the other hand, the infrared light component of the laser beam 53a in the gap by metal wiring 103 incides the 1st infrared light detector 31.
The 1st infrared light detector 31 and the 2nd infrared light detector 32 according to the Strength Changes of the incident light of the scan-synchronized of laser beam 53a, obtain the laser scanning picture respectively.That is, the transmission picture that the 1st infrared light detector 31 is taken the laser beam 53a of analyzed wafer 100 is the 1st Wiring pattern picture, as the laser scanning picture.In addition, the reflection image that the 2nd infrared light detector 32 is taken the laser beam 53a of analyzed wafer 100 is the 2nd Wiring pattern picture, as the laser scanning picture.
On the other hand, in the present embodiment, the shooting of the luminous picture of fault of the fault point of analyzed wafer 100 is undertaken by the 3rd infrared light detector 33.The action of the 3rd infrared light detector 33 is identical with infrared light detector 12 among the embodiment 1.
But in the present embodiment, the 2nd infrared light detector 32 and the 3rd infrared light inspection device 33 carry out position adjustments in advance, make analyzed area (visual field) identical.Generally, characteristic according to lens optical system 72, the center distortion of analyzed area is few, thereby this position adjustments can be that the center of analyzed area of the center (being the center of analyzed area) that makes the zone of laser optical system 53 scanning laser beam 53a and the 3rd infrared light detector 33 is consistent.For example, the position of scalable the 3rd infrared light detector 33 makes the centre coordinate of reflection of light light incident the 3rd infrared light detector 33 at center of the scanning area of illuminating laser beam 53a.But because the luminous intensity of laser beam 53a is high, must suppress the sensitivity of the 3rd infrared light detector 33 this moment.
As more than, the 1st infrared light detector 31 is taken i.e. the 1st Wiring pattern picture of the Wiring pattern picture taken from the surface of analyzed wafer 100, the 2nd infrared light detector 32 is taken i.e. the 2nd Wiring pattern picture of the Wiring pattern picture taken from the back side of analyzed wafer 100.In addition, the 3rd infrared light detector 33 is obtained the luminous picture of taking from the back side of fault.
Because the 1st Wiring pattern picture and the 2nd Wiring pattern picture all are based on the laser scanning picture of the scanning of same laser bundle 53a, thereby can carry out position correction easily, so that analyzed area is in full accord.In addition, because the 2nd infrared light detector 32 is consistent with the analyzed area of the 3rd infrared light detector 33, thereby can easily carry out position correction.
Thereby,, carry out the 1st Wiring pattern picture taken from the face side of analyzed wafer 100 and the position correction of the luminous picture of fault easily according to present embodiment.That is, determine from the position of the fault point that rear side is taken at the Wiring pattern picture of obtaining from face side easily.
As the detection gimmick of the fault point of semiconductor device, known have OBIC method (OpticalBeam Induced Current method) and an OBIRCH method (Optical Beam InducedResistance Change method).The OBIC method is scanning and an illuminating laser beam under the state that applies low-voltage to the semiconductor device as analytic target, turns the gimmick that shows the picture of taking the fault point for the brightness variation into by the electrorheological with each scanning place simultaneously.The OBIRCH method is to semiconductor device scanning and illuminating laser beam as analytic target, changes the gimmick that shows the picture of taking the fault point as brightness by the resistance variations that the temperature rising of distribution is followed.
Because metal wiring is the transmission laser bundle not, thereby in OBIC method and the OBIRCH method, if the metallic wiring layer multiple stratification then is difficult to observe from the face side of wafer.Thereby, infrared OBIC method (IR-OBIC:Infrared OBIC) or infrared OBIRCH method (IR-OBIRCH:Infrared OBIRCH) method that the rear side (silicon chip side) from wafer is shone infrared laser beam have been proposed.
For example, fail analysis device as present embodiment, if possess the structure of the laser optical system 53 of the laser beam 53a that can comprise the infrared light component, then can adopt it to carry out IR-OBIC method or IR-OBIRCH method from the rear side scanning and the irradiation of analyzed wafer 100.That is, also can adopt IR-OBIC analytical equipment or IR-OBIRCH analytical equipment to replace the 3rd infrared light detector 33, the picture of fault point be taken as the 3rd video camera.In addition, this occasion by making the laser scanning zone of carrying out IR-OBIC method or IR-OBIRCH method consistent with the laser scanning zone of taking the 1st and the 2nd Wiring pattern picture, can make both analyzed area (visual field) unanimities.Thereby, can easily determine the position of the fault point in the 1st and the 2nd Wiring pattern picture.
Fig. 6 is the pie graph of the fail analysis device of embodiment 4.Among this figure, enclose prosign with the key element that Fig. 1 and Fig. 5 are same.In the present embodiment,, adopt from the surface the laser optical system 54 of analyzed wafer 100 scannings and illuminating laser beam 54a as the light source of the Wiring pattern picture that obtains analyzed wafer 100.The laser beam 54a that laser optical system 54 sends comprises the above infrared light component of wavelength 1 μ m.
The laser beam 54a that laser optical system 54 sends shines the surface of analyzed wafer 100 via half-reflecting mirror 61, lens optical system 71.Infrared light component incident the 1st infrared light detector 31 by the metal wiring 103 laser light reflected bundle 54a in the analyzed wafer 100.On the other hand, infrared light component incident the 2nd infrared light detector 32 of the laser beam 54a in the gap by metal wiring 103.That is, the reflection image that the 1st infrared light detector 31 is taken the laser beam 54a of analyzed wafer 100 is the 1st Wiring pattern picture, and on the other hand, the transmission picture that the 2nd infrared light detector 32 is taken the laser beam 54a of analyzed wafer 100 is the 2nd Wiring pattern picture.
In addition, identical with embodiment 3, the 3rd infrared light detector 33 is taken the luminous picture of fault of the fault point of analyzed wafer 100.In addition, in the present embodiment, the 2nd infrared light detector 32 and the 3rd infrared light detector 33 also carry out position adjustments in advance, make analyzed area (visual field) identical.
Because the 1st Wiring pattern picture and the 2nd Wiring pattern picture all are based on the laser scanning picture of the scanning of same laser bundle 54a, thereby can carry out position correction easily, so that analyzed area is in full accord.In addition, owing to make the 2nd infrared light detector 32 consistent in advance with the analyzed area of the 3rd infrared light detector 33, thereby can easily carry out position correction.
Thereby, identical with embodiment 3, can easily carry out the 1st Wiring pattern picture taken from the face side of analyzed wafer 100 and the position correction of the 2nd Wiring pattern picture and the luminous picture of fault.That is, can easily determine from the position of the fault point that rear side is taken at the Wiring pattern picture of obtaining from face side.In addition, owing to face side illuminating laser beam 54a, thereby has the effect that can obtain more brightly from the 1st Wiring pattern picture of face side shooting from analyzed wafer 100.
Embodiment 5
Among the embodiment 3 and 4, form and to possess respectively in order to the means (the 2nd infrared light detector 32) that obtain the Wiring pattern picture of taking from the rear side of analyzed wafer 100 with in order to the structure of the means (the 3rd infrared light detector 33) of taking the luminous picture of fault.In the present embodiment, these two pictures are taken by 1 video camera.
Fig. 7 is the pie graph of the fail analysis device of present embodiment.Among this figure, enclose prosign, omit detailed explanation here with the key element that Fig. 1 and Fig. 5 are same.
The transmission picture that the 1st infrared light detector 31 is taken the laser beam 53a of analyzed wafer 100 is the 1st Wiring pattern picture.On the other hand, the reflection image of the laser beam 53a of the analyzed wafer 100 of the 2nd infrared light detector 42 shootings is the luminous picture of fault of the 2nd Wiring pattern picture and fault point.But, because the strength ratio fault point of laser beam 53a is luminous much better than, thereby the luminous sensitivity of the 2nd infrared light detector 42 must suppress the shooting of the 2nd Wiring pattern picture the time.
In addition, the 1st infrared light detector 31 according to the Strength Changes of the incident light of the scan-synchronized of laser beam 53a, obtain the 1st Wiring pattern picture as the laser scanning picture.That is, carry out the calculation process that becomes image in order to the data conversion that timesharing is obtained.But,, directly obtain the 2nd Wiring pattern picture from the incident light intensity that each pixel obtained because the 2nd infrared light detector 42 that also adopts in the shooting of the luminous picture of fault can detect light in pixel unit, thereby also can not carry out such calculation process.In addition, owing to also can timesharing in the 2nd infrared light detector 42 obtain the intensity data of incident light, thereby certainly also can be with the laser scanning picture of calculation process as the 2nd Wiring pattern picture.
Because the 1st Wiring pattern picture and the 2nd Wiring pattern picture all are based on the laser scanning picture of the scanning of same laser bundle 53a, thereby can easily carry out position correction, so that analyzed area is in full accord.In addition, because the 2nd Wiring pattern picture and the luminous picture of fault taken by same the 2nd infrared light detector 42, thereby can easily carry out position correction, make both analyzed areas (visual field) identical.
Thereby according to present embodiment, the 1st Wiring pattern picture of taking from the face side of analyzed wafer 100 and the position correction of the luminous picture of fault can easily carry out.That is, determine from the position of the fault point that rear side is taken at the Wiring pattern picture of obtaining from face side easily.
In addition, among Fig. 7, light source as the Wiring pattern picture that obtains analyzed wafer 100, illustrated to adopt and scanned the also structure of the laser optical system 53 of illuminating laser beam 53a from the back side to analyzed wafer 100, but, for example, as shown in Figure 8, also can adopt from the laser optical system 54 of surface scan and illuminating laser beam 54a.This occasion, except above-mentioned effect, owing to face side illuminating laser beam 54a from analyzed wafer 100, thereby, have the effect that can obtain more brightly from the 1st Wiring pattern picture of face side shooting.
[effect of invention]
According to the failure analysis methods of one aspect of the invention because the luminous picture of trouble point and The 2nd Wiring pattern picture is taken with same video camera, thereby carries out position correction easily, makes both Analyzed area (visual field) consistent. In addition, the 1st Wiring pattern similarly is the reflection image from the surface, Thereby, can look like to obtain from the 1st Wiring pattern that semiconductor chip at least forms is multilayer wired The Wiring pattern picture of the superiors. In addition, because the 2nd Wiring pattern similarly is the transmission picture, thereby its In also comprise the Wiring pattern picture of the multilayer wired the superiors. Thereby, also carry out easily the 1st and join Line pattern picture and the calibration of the 2nd Wiring pattern the position of image. Thereby, carry out from semiconductor core easily The luminous the position of image calibration of the 1st Wiring pattern picture that the face side of sheet is taken and fault. That is, exist Determine easily from the position of the trouble point that rear side is taken on the Wiring pattern picture of obtaining from face side Put.
Failure analysis methods according to a further aspect of the present invention because the 1st Wiring pattern picture and The 2nd Wiring pattern picture all is based on the laser scanning picture of the scanning of same laser bundle, thereby easily Carry out position correction, make analyzed area in full accord. In addition, by carrying out in advance the 2nd shooting The position correction of machine and the 3rd video camera, the position of image school of the 2nd Wiring pattern picture and trouble point Standard also can easily be carried out. Thereby, the 1st wiring diagram of taking from the face side of semiconductor chip The luminous the position of image calibration of case picture and fault is also carried out easily.
Claims (6)
1. failure analysis methods comprises:
(a) include the operation of the 1st light of the component more than the wavelength 1 μ m to the surface irradiation of the semiconductor chip that becomes analytic target;
(b) promptly the 1st Wiring pattern picture and transmission picture are the operation of the 2nd Wiring pattern picture to take reflection image that above-mentioned the 1st light by above-mentioned semiconductor chip forms;
(c) take the operation of the luminous picture that the fault point by above-mentioned semiconductor chip forms from above-mentioned semiconductor chip backside side,
It is characterized in that above-mentioned the 2nd Wiring pattern picture and above-mentioned luminous picture are taken with same video camera.
2. the described failure analysis methods of claim 1 also comprises:
(d) include the operation of the 2nd light of the component more than the wavelength 1 μ m to the irradiation of above-mentioned semiconductor chip backside;
(e) take reflection image that above-mentioned the 2nd light by above-mentioned semiconductor chip forms promptly the 3rd Wiring pattern picture and transmission picture be the operation of the 4th Wiring pattern picture,
It is characterized in that above-mentioned the 3rd Wiring pattern picture is taken with above-mentioned same video camera.
3. failure analysis methods comprises:
(a) include the laser beam of the component more than the wavelength 1 μ m to the semiconductor chip scanning that becomes analytic target and irradiation, promptly the 1st Wiring pattern picture and reflection image are the operation of the 2nd Wiring pattern picture to take transmission picture that the above-mentioned laser beam by above-mentioned semiconductor chip forms;
(b) operation of the picture of the fault point of the above-mentioned semiconductor chip of shooting,
It is characterized in that,
Above-mentioned operation (a) is carried out by the 1st video camera of the face side configuration of above-mentioned semiconductor chip and the 2nd video camera of rear side configuration,
Above-mentioned operation (b) is carried out by the 3rd video camera of above-mentioned semiconductor chip backside side configuration,
Reach (b) before in above-mentioned operation (a), calibrate the position of above-mentioned the 2nd video camera and above-mentioned the 3rd video camera.
4. the described failure analysis methods of claim 3 is characterized in that:
Above-mentioned operation (b) is,
(c) take the operation of the luminous picture that the fault point by above-mentioned semiconductor chip forms from above-mentioned semiconductor chip backside side.
5. the described failure analysis methods of claim 3 is characterized in that:
Above-mentioned operation (b) is,
(d) from the scanning of above-mentioned semiconductor chip backside side and shine above-mentioned laser beam, the operation of taking the picture of above-mentioned fault point with OBIC method or OBIRCH method.
6. failure analysis methods comprises:
(a) include the laser beam of the component more than the wavelength 1 μ m to the semiconductor chip scanning that becomes analytic target and irradiation, promptly the 1st Wiring pattern picture and reflection image are the operation of the 2nd Wiring pattern picture to take transmission picture that the above-mentioned laser beam by above-mentioned half guiding element chip forms;
(b) operation of the picture of the fault point of the above-mentioned semiconductor chip of shooting,
It is characterized in that,
Above-mentioned operation (a) is carried out by the 1st video camera of the surface configuration of above-mentioned semiconductor chip and the 2nd video camera of back side configuration,
Above-mentioned operation (b) is carried out by above-mentioned the 2nd video camera.
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| CNA200310102909XA CN1497698A (en) | 2002-10-22 | 2003-10-22 | Fault analytical method |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103970922A (en) * | 2013-01-25 | 2014-08-06 | 英属开曼群岛商达盟系统有限公司 | Design-Based Process Optimization Apparatus in Semiconductor Fabs |
| CN104316856A (en) * | 2014-10-29 | 2015-01-28 | 上海华力微电子有限公司 | Back face detection type photon radiation microscope device and testing method thereof |
| CN111692977A (en) * | 2020-05-13 | 2020-09-22 | 苏州舜治自动化机械设备有限公司 | Wafer detection infrared light steering mechanism and method |
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2003
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103970922A (en) * | 2013-01-25 | 2014-08-06 | 英属开曼群岛商达盟系统有限公司 | Design-Based Process Optimization Apparatus in Semiconductor Fabs |
| CN104316856A (en) * | 2014-10-29 | 2015-01-28 | 上海华力微电子有限公司 | Back face detection type photon radiation microscope device and testing method thereof |
| CN104316856B (en) * | 2014-10-29 | 2017-06-23 | 上海华力微电子有限公司 | Back side detection type photon radiation microscopie unit and method of testing |
| CN111692977A (en) * | 2020-05-13 | 2020-09-22 | 苏州舜治自动化机械设备有限公司 | Wafer detection infrared light steering mechanism and method |
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