CN1492480A - Method for manufacturing wafer with strain channel layer - Google Patents

Abstract

The invention discloses a method for manufacturing a wafer with a strain channel layer. First, a first substrate having a porous silicon layer is provided, and a first thermal treatment is performed to form a first silicon surface layer on the surface of the porous silicon layer. And then, epitaxially growing a relaxed silicon-germanium layer on the first silicon surface layer, forming a bonding layer on the relaxed silicon-germanium layer, and bonding the bonding layer with a second substrate. And removing the porous silicon layer and the first substrate, and keeping the junction layer and the relaxed silicon-germanium layer on the second substrate. A second thermal treatment is performed to form a second silicon surface layer on the relaxed sige layer surface. Finally, an epitaxial silicon layer is epitaxially grown on the second silicon surface layer. The epitaxial silicon layer grown on the relaxed sige layer will have tensile strain.

Description

Method for fabricating wafer with strained channel layer

field of invention

The invention relates to a semiconductor manufacturing method, in particular to a wafer manufacturing method with a strained channel layer.

Background of the invention

With the rapid development of the electronics industry, the demand of the communication and computer markets has become the main driving force for the continuous improvement of semiconductor technology. Due to the increasing market demand for integrated circuit components with high integration density, small size and high operating efficiency, improving component performance and reducing component size has become an important development topic in the semiconductor industry today. When the size of the device is reduced in response to the high integration requirements of integrated circuits, the performance of the device, such as the driving current, will also change accordingly and cannot reach an ideal range. Therefore, it is still a big challenge for the current semiconductor technology to reduce the size of the device and improve the performance of the device without the introduction of new materials and new device structures.

In order to improve the performance of integrated circuit components, many studies have proposed applying the heterostructure technology to the field of transistors. Using the strain in the heterostructure to cause the difference in the band gap (Band Gap) to greatly improve the mobility of electrons and holes (Mobility), and improve the current speed of the transistor through high electron or hole mobility, thereby improving the component's performance. Since germanium has a smaller energy gap and higher electron/hole mobility than silicon, and germanium and silicon have a similar lattice structure, the heterostructure of silicon/silicon germanium (Silicon/SiGe) It has been widely used in various transistor components. For example, in the application of bipolar junction transistors (Bipolar Junctions Transistor, BJT), the presence of germanium can greatly change the characteristics of components such as collector current and so on. In the field effect transistor (Field Effect Transistor, FET) application, the strained silicon germanium can enhance the electron mobility of the carrier. The energy gap difference between strained silicon germanium and unstrained silicon mainly appears in the valence band, so the hole mobility of the P-channel field effect transistor can be improved.

The heterogeneous structure of silicon/silicon germanium is also widely used in metal oxide semiconductor (Metal Oxide Semiconductor, MOS) transistors, by using semiconductor technology to grow a structure with appropriate germanium content on silicon, so as to increase the energy band structure by using strain. The mobility of electrons and holes and the increase of driving current improve the performance of MOS transistors. For example, using silicon with biaxial tensile strain can increase electron mobility, and using silicon germanium with biaxial compressive strain can increase hole mobility, and so on. Since silicon with biaxial tension strain can improve the performance of both NMOS and PMOS, it is a more commonly used method in the semiconductor industry today.

In the prior art, when fabricating a transistor with a strained channel layer, a very thick buffer layer must be grown first, and then a desired strained channel layer is grown on the buffer layer. For example, when making a transistor with a tension-strained silicon layer, it is necessary to grow a layer of relaxed epitaxial silicon germanium first. This is because the lattice constant of silicon is smaller than that of silicon germanium, so it is formed on the relaxed silicon germanium layer. The silicon layer on the germanium layer has tensile stress, which induces tensile strain. However, in the current semiconductor technology, it is still a great challenge to grow a relaxed epitaxial SiGe layer with low dislocation and low defect density. For example, in U.S. Patent No. 6,107,653 to Eugene A. Fitzgerald, a method for forming an epitaxial silicon germanium layer with low dislocation density is disclosed, which is achieved by growing silicon germanium thin films at different levels (Graded), The surface of the silicon germanium film is planarized to reduce the surface roughness of the silicon germanium film, so that the subsequent growth of the epitaxial silicon germanium film on the flat surface has a low dislocation density. However, the thickness of the epitaxial silicon germanium layer grown by this method is very thick, and requires complicated manufacturing process and high manufacturing cost, so it is not easy to be integrated into the traditional semiconductor manufacturing process.

Therefore, there is an urgent need to develop a new semiconductor manufacturing method to manufacture a wafer with a strained channel layer under the premise of a simple manufacturing method and less cost.

Contents of the invention

In view of the above-mentioned background of the invention, to use the prior art to fabricate a transistor with a tensile strained silicon channel, it is necessary to grow a relaxed epitaxial silicon germanium layer to form a relaxed silicon germanium layer with low dislocation or low defect density. The epitaxial silicon germanium layer requires complicated manufacturing process and high cost. Therefore, the present invention provides a method for manufacturing a wafer with a strained channel layer, which can simply form a strained silicon layer on the relaxed epitaxial silicon germanium layer.

An object of the present invention is to provide a method for manufacturing a wafer with a strained channel layer, which uses relaxed epitaxial silicon in the manufacturing process of a silicon (Silicon-on-Insulator, SOI) wafer on an insulating layer. A strained silicon layer is formed on the germanium layer.

Another object of the present invention is to provide a method of manufacturing a wafer, which can be combined with the manufacturing process of a wafer with silicon on the insulating layer to simplify the manufacturing method and save manufacturing costs, and can be integrated into the general integrated circuit manufacturing process middle.

Another object of the present invention is to provide a method for fabricating a wafer with a strained channel layer, which uses the strained channel layer in the wafer to change the energy band structure to increase the mobility of electrons and holes, thereby improving the performance of transistors.

According to the purpose described above, the present invention discloses a method for manufacturing a wafer with a strained channel layer. First, a first substrate with a layer of porous silicon layer is provided, and the surface of the porous silicon layer is heat-treated so that The surface of the porous silicon layer forms a thin and flat first silicon surface layer. Next, grow a layer of relaxed silicon germanium ( _Six GE _1-x ) layer on the first silicon surface layer by epitaxial growth, and then form a bonding layer on the epitaxial silicon germanium layer superior. Then, the bonding layer is bonded to a second substrate, and then the porous silicon layer and the first substrate are removed, and the bonding layer and the epitaxial silicon germanium layer remain on the second substrate. The surface of the epitaxial silicon germanium layer is then heat-treated to form a second silicon surface layer on the surface of the epitaxial silicon germanium layer, and finally an epitaxial silicon layer is grown on the second epitaxial silicon layer by epitaxy. on the silicon surface. The epitaxial silicon layer grown on the relaxed epitaxial silicon germanium layer will be tensile strained, resulting in a wafer with a strained channel layer. The bonding layer includes a layer of epitaxial silicon and/or a layer of silicon dioxide, and the second substrate includes a substrate structure with silicon on an insulating layer. The step of removing the porous silicon layer includes cutting off the porous silicon layer with a water knife and etching the remaining part of the porous silicon layer and the first silicon surface on the second substrate until the epitaxial silicon germanium layer is exposed.

The invention also discloses a manufacturing method of a semiconductor base material. The method includes providing a first base material with a layer of porous silicon layer on a surface of the first base material. Next, a first silicon surface layer is formed on the first porous silicon layer, a silicon germanium layer is formed on the first silicon surface layer, and a bonding layer is formed on the silicon germanium layer. Afterwards, the bonding layer is bonded to a second substrate, the first substrate and the porous silicon layer are removed, and the bonding layer and the SiGe layer remain on the second substrate. Then, a second silicon surface layer is formed on the silicon germanium layer, and finally, a silicon layer is formed on the second silicon surface layer, and the silicon layer becomes the strain channel layer. Wherein, the bonding layer includes a layer of epitaxial silicon layer and/or a layer of silicon dioxide layer, the second substrate includes a substrate structure with silicon on an insulating layer, and the method for forming the silicon germanium layer and the silicon layer includes using epitaxy Way.

Brief description of the drawings

The preferred embodiment of the present invention will be described in more detail with the help of the following figures in the following explanatory text, wherein:

1 to 4 show a schematic cross-sectional view of the manufacturing process of a wafer according to a preferred embodiment of the present invention, wherein the first part of the wafer is manufactured; and

FIGS. 5-7 are schematic cross-sectional diagrams illustrating a wafer manufacturing process according to a preferred embodiment of the present invention, wherein the first part of the wafer is bonded to a handle wafer to form a wafer with a strained channel layer.

Detailed ways

The invention discloses a method for manufacturing a wafer with a strained channel layer, which can grow a layer on a relaxed epitaxial silicon germanium layer during the manufacturing process of a silicon on insulator (SOI) wafer epitaxial silicon layer, so that the epitaxial silicon layer becomes a silicon layer with tensile strain. The invention can be applied in CMOS transistors, and the mobility of electrons and holes can be increased by utilizing the change of the energy band structure caused by the strain, so as to improve the performance of the transistors. In order to make the description of the present invention more detailed and complete, the method for manufacturing the wafer with the strained channel layer of the present invention will be described below with preferred embodiments and accompanying drawings.

FIGS. 1-4 are cross-sectional schematic diagrams illustrating a manufacturing process of a wafer with a strained channel layer according to a preferred embodiment of the present invention. The figures show that a first part of the wafer 100 is being fabricated. Referring to FIG. 1 , firstly, a suitable silicon substrate 102 having a porous silicon layer 104 is provided, and the substrate 102 can be an N+ type or P+ type semiconductor substrate. Here, the porous silicon layer 104 serves as a seed layer for growing a relaxed epitaxial silicon germanium ( _Six GE _1-x ) layer. For easy understanding, the structure of the porous silicon layer in the drawings is shown to have several cylindrical shapes. However, as known by those skilled in the art, in practice the holes in the porous silicon layer should be of more complex shapes.

Next, as shown in FIG. 2 , heat treatment is performed on the surface of the porous silicon layer 104 to form a thin and flat silicon surface layer 106 on the surface of the porous silicon layer 104 . Preferably, hydrogen annealing (H ₂ Annealing) can be used as the heat treatment method, and the treatment temperature and time of hydrogen annealing can be determined according to actual process requirements and applications. Afterwards, as shown in FIG. 3 , a layer of epitaxial silicon germanium layer 108 is grown on the silicon surface layer 106 in an epitaxial manner. The formation method of the epitaxial silicon germanium layer 108 can be, for example, chemical vapor deposition (CVD), ultrahigh Vacuum chemical vapor deposition (UHVCVD), low pressure chemical vapor deposition (LPCVD) or plasma enhanced chemical vapor deposition (PECVD), etc. Since the porous silicon layer 104 can accommodate stress or strain, the epitaxial SiGe layer 108 epitaxially grown on the silicon surface layer will form a relaxed structure.

Referring to FIG. 4A, a bonding layer 110 is then formed on the relaxed epitaxial silicon germanium layer 108, and the bonding layer 110 is used as a buffer layer for bonding with another handling wafer (Handling Wafer). In a preferred embodiment of the present invention, the bonding layer 110 is made of an epitaxial silicon layer, which can be grown on the epitaxial silicon germanium layer 108 by an appropriate epitaxial method. Alternatively, in another preferred embodiment of the present invention, the material of the bonding layer 110 can be a silicon dioxide layer, which can be formed by depositing a layer on the epitaxial silicon germanium layer 108, for example, by chemical vapor deposition. silicon dioxide layer, or the epitaxial silicon germanium layer 108 can be thermally oxidized to form a silicon dioxide layer on the epitaxial silicon germanium layer 108 . In addition, as shown in FIG. 4B, in another preferred embodiment of the present invention, the material of the bonding layer 110 of the first partial wafer 100' may include a layer of epitaxial silicon and a layer of silicon dioxide, which form The method can firstly use an appropriate epitaxial method to grow a layer of epitaxial silicon layer 110a on the epitaxial silicon germanium layer 108, and then form a layer of silicon dioxide layer 110b on the epitaxial silicon layer 110a. The silicon dioxide layer 110b It is used as a buffer layer for bonding with another handle wafer. The silicon dioxide layer 110b can be formed by, for example, depositing a silicon dioxide layer on the epitaxial silicon layer 110a by chemical vapor deposition, or performing a thermal oxidation treatment on the epitaxial silicon layer 110a to form a layer on the epitaxial silicon germanium layer 108. A silicon dioxide layer is formed on it. So far, the fabrication of the first part of the wafer has been completed, and the fabrication process of bonding the first part of the wafer with a handle wafer to form a wafer with a strained channel layer will be described below.

Please refer to FIG. 5, using known semiconductor bonding techniques, such as anode bonding, to bond the above-mentioned first part of the wafer 100 with a handling wafer 120 (Handling Wafer), where the handling wafer 120 is used as a support . The handling wafer 120 may be a silicon on insulator (SOI) wafer structure, such an SOI structure may include, for example, an insulating layer 122 made of silicon dioxide and a silicon substrate 124, The handle wafer 120 is bonded to the bonding layer 110 of the first partial wafer 100 through the insulating layer 122 . In an embodiment of the present invention, when the bonding layer 110 is made of an epitaxial silicon layer, the first part of the wafer is bonded to the insulating layer 122 in the handle wafer through the epitaxial silicon layer. In another embodiment of the present invention, when the bonding layer 110 is made of a silicon dioxide layer, the first part of the wafer is bonded to the insulating layer 122 in the handling wafer through the silicon dioxide layer. In addition, in another embodiment of the present invention, when the bonding layer 110 is made of an epitaxial silicon layer and a silicon dioxide layer, the first part of the wafer is formed through the silicon dioxide layer in the bonding layer. Bonded to the insulating layer 122 in the handle wafer.

Afterwards, as shown in FIG. 6 , the porous silicon layer 104 and the silicon substrate 102 are removed to leave the relaxed epitaxial SiGe layer 108 on the handle wafer 120 . Since the structure hardness of the porous silicon layer with holes is relatively poor, in a preferred embodiment of the present invention, a water jet is used to cut the porous silicon layer 104 to remove part of the porous silicon layer 104 and the substrate. 102. Next, the portion of the porous silicon layer 104 remaining on the handle wafer 120 is selectively etched to expose the surface of the epitaxial silicon germanium layer 108 . Then, heat treatment is performed on the surface of the epitaxial SiGe layer 108 , for example, hydrogen annealing can be used to form a flat silicon surface layer 126 on the epitaxial SiGe layer 108 . Finally, as shown in FIG. 7 , an epitaxial silicon layer 130 is grown on the silicon surface layer 126 in a proper epitaxial manner. Since the epitaxial silicon layer 130 is epitaxially grown on the relaxed epitaxial silicon germanium layer 108 , it becomes a silicon layer with tensile strain.

FIG. 7 is a schematic cross-sectional view of a wafer with a strained channel layer manufactured according to a preferred embodiment of the present invention. As shown in FIG. 7, the structure of this wafer includes: a layer of epitaxial silicon layer 130 with tensile strain, a layer of flat silicon surface layer 126, a layer of relaxed epitaxial silicon germanium layer 108, and a layer of bonding layer 110. , and an SOI handle wafer 120 comprising an insulating layer 122 and a silicon substrate 124 . The insulating layer 122 can be made of a silicon dioxide layer, and the bonding layer 110 can be made of an epitaxial silicon layer or a silicon dioxide layer. In another preferred embodiment of the present invention, the bonding layer 110 may include an epitaxial silicon layer and a silicon dioxide layer, and the silicon dioxide layer is used as a buffer layer for bonding with the handling wafer.

In summary, the present invention provides a method for manufacturing a wafer with a strained channel layer, which can grow a layer on the porous silicon layer of the first wafer during the manufacturing process of the wafer with silicon on the insulating layer. Relaxed epitaxial silicon germanium layer, then bond the first part of the wafer with the relaxed epitaxial silicon germanium layer to a handle wafer with silicon on the insulating layer by semiconductor bonding technology, then remove the porous silicon layer, and then relax An epitaxial silicon layer is grown on the epitaxial silicon germanium layer, and the epitaxial silicon layer becomes a strained silicon layer. The manufacturing method of the wafer with the strained channel layer of the present invention can be combined with the manufacturing process of the silicon wafer on the insulating layer. The manufacturing process is simple and economical, and can be integrated into the general integrated circuit manufacturing process. The wafer with the strained channel layer manufactured by the method of the present invention can change the energy band structure through the strained channel layer in the wafer, thereby increasing the mobility of electrons and holes, thus improving the performance of the transistor.

As those skilled in the art understand, the above descriptions are only preferred embodiments of the present invention, and are not intended to limit the scope of the claims of the present invention; all other equivalents that do not depart from the spirit disclosed by the present invention are completed Changes or modifications should be included within the scope of the following claims.

Claims (10)

1, a kind of manufacture method of semiconductor substrate, this method comprises the following steps: at least

One first base material is provided, has a porous silicon layer on the surface of this first base material;

On this first porous silicon layer, form one first silicon face layer;

On this first silicon face layer, form a germanium-silicon layer;

On this germanium-silicon layer, form a knitting layer;

Engage this knitting layer to one second base material;

Remove this first base material and this porous silicon layer, and on this second base material, keep this knitting layer and this germanium-silicon layer;

On this germanium-silicon layer, form one second silicon face layer; And

On this second silicon face layer, form a silicon layer.

2, the method for claim 1, the step that wherein forms this first silicon face layer and this second silicon face layer comprises the use hydrogen annealing.

3, the method for claim 1, the step that wherein forms this germanium-silicon layer comprise uses crystal type of heap of stone.

4, the method for claim 1, wherein this knitting layer comprises a crystal silicon layer of heap of stone.

5, the method for claim 1, wherein this knitting layer comprises a silicon dioxide layer.

6, the method for claim 1, wherein this knitting layer comprises a crystal silicon layer of heap of stone and a silicon dioxide layer.

7, the method for claim 1, wherein this second base material comprises a silicon substrate and an insulating barrier.

8, the method for claim 1, wherein this engagement step comprises this knitting layer is engaged on this insulating barrier on this second base material.

9, the method for claim 1, the step that wherein removes this porous silicon layer and this first base material more comprises:

Cut this porous silicon layer with the water cutter, to remove this porous silicon layer and this first silicon substrate of part; And

Etching remaines in this porous silicon layer and this first silicon face of the part on this second base material, up to exposing this germanium-silicon layer.

10, the method for claim 1, the step that wherein forms this silicon layer on this second silicon face layer comprise uses crystal type of heap of stone.

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