CN1490645A - Pixel structure with storage capacitor, forming method thereof and liquid crystal display device - Google Patents

Abstract

A pixel storage capacitor structure includes a first capacitor electrode formed on a substrate. A capacitor dielectric layer is formed on the first capacitor electrode. A second capacitor electrode is formed on the capacitor dielectric layer, wherein the area of the second capacitor electrode is smaller than the area of the first capacitor electrode. A protective layer covers the second capacitor electrode, wherein the protective layer has an opening to expose the second capacitor electrode. A pixel electrode layer covers the protective layer and is connected to the second capacitor electrode through the opening of the protective layer.

Description

Pixel structure with storage capacitor, method for forming same, and liquid crystal display device

technical field

A display device, and particularly relates to a pixel storage capacitor structure.

Background technique

Displays are common devices in daily life. Especially the TV or computer used must be equipped with a display, so that the image can be displayed on the screen of the display and presented to the user. If a general display is designed with a cathode ray, it requires a large space and causes inconvenience. In particular, notebook computers cannot be used with cathode ray displays. Therefore, flat panel display products formed by dot array design, such as liquid crystal display (liquid crystal display, LCD) or thin film transistor (thin film transistor, TFT) liquid crystal display, have been successfully launched. The image of a TFT-LCD is composed of an array of pixels. Each pixel is controlled by a thin film transistor.

Please refer to FIG. 1 . FIG. 1 illustrates a driving circuit of a conventional thin film transistor liquid crystal display. The thin film transistor liquid crystal display includes a scanning circuit (scanning circuit) 100 and a signal-holding circuit (signal-holding circuit) 102 . The scan circuit 100 drives a set of scan lines 110 , and the signal hold circuit 102 drives a set of signal lines 112 . The scan lines 110 intersect with the signal lines 112 to form a two-dimensional array. Each intersection of the two-dimensional array includes a thin film transistor 104, a pixel storage capacitor 108, and a liquid crystal display unit 106, thus forming a pixel. The gate of the thin film transistor 104 is controlled by the corresponding scan line 110 , and the source of the thin film transistor 104 is controlled by the corresponding signal line 112 . The drain of the thin film transistor 104 is connected to a pixel electrode layer, and is also connected to an electrode of the pixel storage capacitor 108 . The pixel storage capacitor 108 is used to maintain the voltage required for controlling the liquid crystal. The other electrode of the pixel storage capacitor 108 may be connected to an adjacent scan line in earlier technologies.

In addition, with the increasing size of thin film transistor liquid crystal displays, in order to reduce the influence of the gate delay effect (gate delay) of the drive, the current pixel is designed with a common electrode type pixel storage capacitor (Cst On Common) as the mainstream. This type of design is due to the separation of the common electrode (common) from the grid. The other electrode of the capacitor is connected to a common voltage, such as a common electrode (Vcom).

Please refer to FIG. 2 . FIG. 2 illustrates a layout structure of a conventional thin film transistor liquid crystal display. The gate of the TFT 104 is connected to the scan line 110 . The sources of the thin film transistors 104 are connected to corresponding signal lines 112 . The drain of the thin film transistor 104 is connected to the pixel electrode layer 118 . In addition, the pixel storage capacitor is composed of a common lower electrode 114 and an upper electrode 116 . The pixel electrode layer 118 is connected to the upper electrode 116 through an opening 120 .

Wherein, the lower electrode 114 is formed on a transparent substrate 126 . The lower electrode 114 is generally also referred to as the first metal layer, which is generally defined together with the gate of the thin film transistor 104 . Next, a capacitive dielectric layer 124 is formed covering the lower electrode 114 . A metal electrode layer 116 is formed on the capacitor dielectric layer 124 as the upper electrode 116 of the storage capacitor, and the portion overlapping the lower electrode 114 is the main charge storage location. A protective layer 122 is formed to cover the capacitor top electrode 116 and cover other parts. The protection layer 122 has an opening 120 exposing the capacitor top electrode 116 . A pixel electrode layer 118 passes through the opening 120 and can be connected to the capacitor top electrode 116 . In addition, other structures to complete the liquid crystal display, such as integrating a color filter substrate on the bright substrate 126 and filling a liquid crystal layer (not shown), etc., are well known by those skilled in the art and will not be described in detail here.

In the above known structure, during the array manufacturing process, the channel region of the thin film transistor 104 is generally formed of amorphous silicon hydride (a-Si:H). During the definition forming process, the foreign matter 115 of amorphous silicon is likely to remain on the capacitor dielectric layer 24 along the edge of the capacitor bottom electrode 114 . When the so-called second metal layer fabrication process (metal2) is performed to form the upper capacitor electrode 116 and the signal line 112, the upper capacitor electrode 116 will cover the lower capacitor electrode 114 of the overcapacitor and straddle its edge. At this time, if any conductive residual foreign matter 115 remains on the capacitor dielectric layer 24 along the edge of the capacitor bottom electrode 114 , it will short-circuit the capacitor top electrode 116 and the signal line 112 , resulting in a defect of the array.

In addition, the residual foreign matter 115 may also cause a short circuit between the upper and lower capacitor electrodes, causing the pixel storage capacitor 108 to lose its effect, resulting in a bright spot defect of the pixel. When the foreign matter 115 remains to cause a bright spot defect, generally, the common electrode 114 is also disconnected in addition to removing the foreign matter with a laser. Disconnection will cause the occurrence of gate light lines. Therefore, in order to prevent the occurrence of light lines, when a point defect generated by a defective capacitor occurs, the general practice tends not to repair the point defect, thus forming a bright spot.

However, today's market has increasingly stringent requirements for display image quality. How to repair bright spots into dark spots with laser repair technology, so as to achieve the goal of zero bright spots, is the current mainstream trend. At present, the above-mentioned laser repair technology cannot perform dark spots, because the existing dark spot technology will cause a short circuit between the common electrode and the grid, resulting in bright line defects. Therefore, how to solve the problem of point defects in the storage capacitor and the inability to make dark spots is an important key to further improve the image quality.

Contents of the invention

In view of this, the present invention provides a pixel storage capacitor structure. By shrinking the edge of the upper electrode of the capacitor, the lower electrode of the capacitor is larger than the upper electrode of the capacitor. In this way, when conductive foreign matter remains on the edge of the lower electrode of the capacitor, because the upper electrode of the capacitor does not overlap with the edge of the lower electrode of the capacitor, even if the foreign matter remains, the probability of a short circuit between the capacitor and the signal line can be reduced.

The invention provides a pixel storage capacitor structure, which includes a first capacitor electrode formed on a substrate. A capacitor dielectric layer is formed on the first capacitor electrode. A second capacitor electrode is formed on the capacitor dielectric layer, wherein the area range of the second capacitor electrode is smaller than the area range of the first capacitor electrode. A protective layer covers the second capacitor electrode, wherein the protective layer has an opening exposing the second capacitor electrode. A pixel electrode layer is covered on the protective layer, and is connected with the second capacitance electrode through the opening of the protective layer.

In the above, the pixel electrode is connected with a switch element.

In the above, because the area range of the second capacitor electrode is smaller than the area range of the first capacitor electrode, its edges do not overlap, thus effectively reducing the probability of capacitor short circuit.

The present invention provides a liquid crystal display device, comprising a plurality of scanning lines; a plurality of signal lines; and a plurality of pixels, each pixel includes a liquid crystal unit, has a pixel electrode connected to a storage capacitor, and a switch component connected to the liquid crystal One of the unit and the signal line, and one of the switch components is connected to one of the scanning lines; wherein, the storage capacitor also includes a first capacitor electrode, a capacitor dielectric layer and a second capacitor electrode, and the second capacitor electrode and the first capacitor electrode An overlapping area of a capacitor electrode is substantially equal to the area of the second capacitor electrode.

The invention further provides a method for forming a pixel storage capacitor, including forming a first capacitor electrode on a substrate. A capacitor dielectric layer is formed on the first capacitor electrode. On the capacitor dielectric layer, a second capacitor electrode is formed, wherein an area range of the second capacitor electrode is smaller than that of the first capacitor electrode. A covering protection layer is formed on the second capacitor electrode. The protective layer is defined to form an opening exposing the second capacitor electrode. A pixel electrode layer is formed, covered on the protective layer, and connected to the second capacitance electrode through the opening of the protective layer.

In order to make the above-mentioned objects, features, and advantages of the present invention more comprehensible, a preferred embodiment will be described in detail below together with the accompanying drawings.

Description of drawings

FIG. 1 illustrates a driving circuit of a conventional thin film transistor liquid crystal display.

FIG. 2 illustrates a layout structure of a conventional thin film transistor liquid crystal display.

FIG. 3A illustrates the layout structure of a thin film transistor liquid crystal display according to the present invention.

FIG. 3B shows a cross-sectional view along line II-II in FIG. 3A according to the present invention.

Label description:

100 Scanning circuit 102 Signal holding circuit

104 Thin Film Transistor 106 Pixel LCD

108 storage capacitor 110 scanning lines

112 Signal line 114 Common electrode line

115 Foreign matter 116,200 Capacitor upper electrode

118, 204 pixel electrodes 120, 202 openings

122 Protective layer 124 Capacitor dielectric layer

126 Substrate

Detailed ways

One of the main features of the pixel storage capacitor structure of the present invention is that the lower electrode of the capacitor is larger than the upper electrode of the capacitor by narrowing the edge of the upper electrode of the capacitor or expanding the edge of the lower electrode of the capacitor. In this way, when the conductive foreign matter remains on the capacitor dielectric layer along the edge of the lower electrode of the capacitor, since the upper electrode of the capacitor does not overlap with the edge of the lower electrode of the capacitor, even if the conductive foreign matter remains, the probability of a short circuit between the capacitor and the signal line can be reduced. An embodiment is given below as a description of the features of the present invention.

Please refer to FIG. 3A . FIG. 3A shows the layout structure of a thin film transistor liquid crystal display according to the present invention. The gate of the TFT 104 is connected to the scan line 110 . The TFT 104 includes a gate 104g, a source 104s, and a drain 104d. There are generally two designs of the TFT 104, one is that the gate 104g is on the bottom, and the source 104s and the drain 104d are on the top. Another design is that the gate 104g is on top, and the source 104s and drain 104d are on the bottom. Now with the gate 104g underneath, it is first formed on a transparent substrate. The grid 104g is generally defined and formed together with the capacitor bottom electrode 114, which is also called the first metal (metal 1) manufacturing process. There is a channel region 104a between the source 104s and the drain 104d. Generally, the channel region 104a is formed of conductive amorphous silicon, and the source electrode 104s and the drain electrode 104d are defined and formed of conductive material of amorphous silicon with N-type doping. A general liquid crystal display includes upper and lower pixel electrode layers and a liquid crystal layer therebetween. In addition, it also includes a color filter layer, a phase difference plate, a polarizer, etc., which are all well-known technologies for those skilled in the art, and will not be described in detail. The liquid crystal display control mechanism is briefly described below.

Please also refer to FIG. 1 , the gate 104 g of the thin film transistor 104 is connected to the scan line 110 . The scan lines 110 are controlled by the scan circuit 100 . The source 104s is connected to the corresponding signal line 112 . The signal line 112 is controlled by the hold circuit 102 . The drain 104d of the TFT 104 is connected to a pixel electrode layer 204 . In addition, the pixel storage capacitor is composed of a capacitor lower electrode 114 and a capacitor upper electrode 200 . The capacitor bottom electrode 114 is also connected to a common electrode Vcom, for example. The pixel electrode layer 204 is connected to the capacitor top electrode 200 through an opening 202 . There is a liquid crystal layer on the pixel electrode layer 204, and a pixel electrode layer (not shown) above the liquid crystal layer. The pixel electrode layer 204 is generally formed of indium tin oxide.

The scanning circuit 100 and the holding circuit 102 each supply a different clock pulse to the scanning line 110 and the signal line 112 in a sequence. The scan line 110 controls the thin film transistor 104 to be turned on and off. The signal line 112 applies a voltage to the thin film transistor 104 . The drain of the TFT 104 is connected to the pixel storage capacitor 108 . If the thin film transistor 104 is turned on, the required voltage can be supplied to the pixel storage capacitor 108 via the signal line 112 , thereby controlling the voltage of the pixel electrode ITO. The voltages applied by the upper and lower pixel electrodes ITO can therefore control the rotation characteristics of the liquid crystal molecules within the pixel range. When the pixel storage capacitor is charged by turning on the thin film transistor 104, the brightness of the liquid crystal in the pixel can be controlled and maintained according to the selection.

Since the manufacturing process of the pixel array needs to go through at least four manufacturing processes, there may be some foreign matter remaining therein, causing defects of the components, such as some problems caused by the above-mentioned FIG. 2 . In order to solve the problem of improper short circuit caused by the residue of foreign matter, the upper electrode of the capacitor is designed by using the present invention, which can solve the above problem.

The design of the present invention makes the range covered by the capacitor upper electrode 200 smaller than the capacitor lower electrode 114, so that the edge of the capacitor lower electrode 114 will not overlap with the capacitor upper electrode 200, that is, the overlapping area of the capacitor upper electrode 200 and the capacitor lower electrode 114 is about It is equivalent to the area of the upper electrode 200 of the capacitor. During the process of forming the capacitor, foreign matter 115 is likely to remain on the edge of the bottom electrode 114 . The foreign matter 115 is generally a conductive residue, such as amorphous silicon material forming a channel region, which tends to remain on the capacitor dielectric layer 124 along the edge of the capacitor bottom electrode 114 to form a conductive residue. Since the capacitor upper electrode 200 is generally formed together with the signal line 112 , if the capacitor upper electrode 200 overlaps with the edge of the capacitor lower electrode 114 . The foreign object 115 may cause a short circuit between the capacitor upper electrode 200 and the signal line 112 .

In addition, if the foreign object 115 touches the upper electrode 200 of the capacitor and the lower electrode 114 of the capacitor, the capacitor will short-circuit and fail. The design of the present invention makes the capacitor upper electrode 200 smaller than the capacitor lower electrode 114, so as to avoid short circuit of the capacitor or short circuit of the pixel electrode layer 204 to the signal line.

The present invention requires that the area range of the upper electrode 200 of the capacitor is smaller than that of the lower electrode 114 of the capacitor in order to avoid overlapping of its edges. Thus the shape or size of the area can vary depending on the actual design, as long as overlapping of edges is avoided.

The function of the thin film transistor 104 is generally similar to a switch element, which can control the charging state of the capacitor. The formation of the opening 202 can be achieved by a general defined manufacturing process, such as lithographic etching. The position of the opening 202 is for the connection between the pixel electrode and the upper capacitor electrode 200 , generally within the range of the upper capacitor electrode 200 , for example, it may be formed at about the middle.

Among the above, the main feature of the present invention is that the upper electrode 200 of the capacitor is smaller than the lower electrode 114 of the capacitor, so that the foreign object 115 will not touch the upper electrode 200 of the capacitor and cause a short circuit. FIG. 3B shows a cross-sectional view along line II-II in FIG. 3A according to the present invention. Referring to FIGS. 3A and 3B , a capacitor bottom electrode 114 is formed on a substrate 126 . A capacitive dielectric layer 124 is formed covering the bottom overcapacitor electrode 114 . The capacitor top electrode 200 is formed on the capacitor dielectric layer 124 . The capacitor bottom electrode 114 , the capacitor dielectric layer 124 and the capacitor top electrode 200 form a storage capacitor. A passivation layer 122 is formed on the capacitor top electrode 200 and covers the substrate 126 . The protection layer 122 has an opening 202 exposing the capacitor top electrode 200 . A pixel electrode layer 204 is formed on the passivation layer 122 . The pixel electrode layer 204 is connected to the capacitor upper electrode 200 through the opening 202 .

In the above, the range of the upper capacitor electrode 200 is smaller than that of the lower capacitor electrode 114 , so it does not overlap with the edge of the lower capacitor electrode 114 . When the foreign matter 115 remains on the edge of the lower electrode 114 of the capacitor, it will not touch the upper electrode 200 of the capacitor to cause improper short circuit. For example, when the foreign object 115 extends to the signal line 112 , if the upper electrode 200 of the capacitor touches the foreign object 115 , a short circuit will be caused between the upper electrode 200 of the capacitor and the signal line 112 .

The position distribution of the above-mentioned residual foreign matter 115 is only a schematic diagram. The remaining foreign matter 115 may also be discontinuous, but the foreign matter 115 remaining on the edge of the lower electrode 114 of the capacitor and causing an improper short circuit is a problem often encountered in the traditional manufacturing process.

One of the features of the present invention is that the edge of the capacitor bottom electrode 114 is not overlapped with the capacitor top electrode 200 . Because the edges do not overlap, it can effectively prevent improper short circuit. In order to have a sufficient storage capacitance value, in addition to reducing the area range of the upper capacitor electrode 200, the area range of the lower capacitor electrode 114 can also be enlarged. Even the shape of the edges changing the area does not deviate from the features proposed by the invention.

In other words, the feature of the present invention is that the edges of the lower capacitor electrode 114 and the upper capacitor electrode 200 do not overlap. As for the adjustment of the area range, it is only a design change condition. In addition, the present invention is not limited to the design of the storage capacitor on the common electrode (Cs on common), and can also be applied to the design of the storage capacitor on the gate (Cs on gate).

Claims (16)

1, a kind of dot structure with reservior capacitor is characterized in that: comprising:

One first capacitance electrode is formed on the substrate;

One capacitance dielectric layer is formed on this first capacitance electrode;

One second capacitance electrode is formed on this capacitance dielectric layer, and wherein an area scope of this second capacitance electrode is less than an area scope of this first capacitance electrode;

One protective seam covers too on this second capacitance electrode, and wherein this protective seam has an opening, exposes this second capacitance electrode;

One pixel electrode layer is covered on this protective seam, and this opening that sees through this protective seam is connected with this second capacitance electrode.

2, the dot structure with reservior capacitor as claimed in claim 1 is characterized in that: this first capacitance electrode has an area that equates haply with this second capacitance electrode with an overlapping region of this second capacitance electrode.

3, the dot structure with reservior capacitor as claimed in claim 1 is characterized in that: this pixel electrode is connected with a switch module.

4, the dot structure with reservior capacitor as claimed in claim 1 is characterized in that: this pixel electrode is connected with a thin film transistor (TFT).

5, the dot structure with reservior capacitor as claimed in claim 1 is characterized in that: this first capacitance electrode is connected in energising altogether and presses.

6, a kind of dot structure with reservior capacitor is characterized in that: comprising:

One first capacitance electrode is formed on the substrate;

One capacitance dielectric layer is formed on this first capacitance electrode;

One second capacitance electrode is formed on this capacitance dielectric layer, and wherein an edge of this second capacitance electrode does not stride across an edge of this first capacitance electrode.

7, the dot structure with reservior capacitor as claimed in claim 6 is characterized in that: also comprise:

One protective seam covers too on this second capacitance electrode, and wherein this protective seam has an opening, exposes this second capacitance electrode;

One pixel electrode layer is covered on this protective seam, and this opening that sees through this protective seam is connected with this second capacitance electrode.

8, the dot structure with reservior capacitor as claimed in claim 6 is characterized in that: this edge of this first capacitance electrode, residual have a foreign matter.

9, the dot structure with reservior capacitor as claimed in claim 8 is characterized in that: this foreign matter comprises amorphous silicon.

10, the dot structure with reservior capacitor as claimed in claim 6 is characterized in that: this first capacitance electrode and the formed capacitor of this second capacitance electrode are controlled by a thin film transistor (TFT).

11, a kind of formation method with dot structure of reservior capacitor is characterized in that: comprising:

Form one first capacitance electrode, on a substrate;

Form a capacitance dielectric layer, on this first capacitance electrode;

Form one second capacitance electrode, on this capacitance dielectric layer, wherein an area scope of this second capacitance electrode is less than this first capacitance electrode;

Forming a protective seam covers too on this second capacitance electrode;

Define this protective seam to form an opening, expose this second capacitance electrode;

Form a pixel electrode layer, be covered on this protective seam, this opening that sees through this protective seam is connected with this second capacitance electrode.

12, the formation method with dot structure of reservior capacitor as claimed in claim 11 is characterized in that: an overlapping region of this first capacitance electrode and this second capacitance electrode has an area that equates haply with this second capacitance electrode.

13, the formation method with dot structure of reservior capacitor as claimed in claim 11, it is characterized in that: this pixel electrode is connected with a switch module.

14, the formation method with dot structure of reservior capacitor as claimed in claim 11 is characterized in that: also comprise connecting this pixel electrode to one thin film transistor (TFT).

15, the formation method with dot structure of reservior capacitor as claimed in claim 11 is characterized in that: also comprise connecting this first capacitance electrode to energising pressure altogether.

16, a kind of liquid crystal indicator is characterized in that: comprising:

A plurality of sweep traces;

A plurality of signal wires;

A plurality of pixels, each pixel comprises a liquid crystal cells, has a pixel electrode and is connected to a storage capacitors, and a switch module, connecting one of this liquid crystal cells and those signal wires, one of this switch module is connected to one of those sweep traces;

Wherein, this storage capacitors comprises one first capacitance electrode, a capacitance dielectric layer and one second capacitance electrode, and an overlapping region of this second capacitance electrode and this first capacitance electrode is equal to the area of this second capacitance electrode haply.

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