CN1479362A - Method for forming shallow trench isolation structure - Google Patents

Abstract

The present invention discloses a method for forming a shallow trench isolation structure. First, a substrate having at least one trench is provided. Then, a polycrystalline silicon layer or an amorphous silicon layer is conformally formed on the surface of the trench by a low-pressure chemical vapor deposition method or a single reaction chamber chemical vapor deposition method. Then, a high-temperature furnace tube oxidation method is used to oxidize the polycrystalline silicon layer or the amorphous silicon layer to form a liner oxide silicon layer on the surface of the trench. Finally, an insulating layer is filled in the trench.

Description

A method of forming a shallow trench isolation structure

technical field

The present invention relates to a semiconductor manufacturing process, in particular to a method for forming a shallow trench isolation structure to prevent the corners of the isolation structure from being recessed due to over-etching.

technical background

Among various device isolation technologies, local oxidation of silicon (LOCOS) and shallow trench isolation process are the two most commonly used technologies, especially the latter because of its small isolation area and the advantages of maintaining substrate flatness after completion. , and it is a semiconductor manufacturing technology that has received much attention recently.

Figures 1a to 1e illustrate schematic cross-sectional views of traditionally fabricated shallow trench isolation structures. First, please refer to FIG. 1 a , on the surface of a silicon substrate 10 , a pad oxide layer (padoxide) 12 and a silicon nitride layer 14 are sequentially formed. Afterwards, a photoresist layer 16 is coated on the silicon nitride layer 14, and its pattern is defined according to the lithography process to expose the part where the trench isolation region is to be formed. Next, using the photoresist layer 16 as a mask, the silicon nitride layer 14 and the pad silicon oxide layer 12 are sequentially etched to form an opening 18 .

Next, referring to FIG. 1 b, after stripping off the photoresist layer 16, the silicon nitride layer 14 and the pad silicon oxide layer 12 are used as a mask to etch the silicon substrate 10 below the opening 18 to form a trench 20. to define the active area of the component.

Next, referring to FIG. 1c , a thermal oxidation process is performed to form a thin silicon oxide on the surface of the trench 20 as a liner oxide layer 22 . However, because the stress will be concentrated on the top and bottom corners 20a, 20b of the trench when the lining silicon oxide layer 22 is formed by oxidation, so the formation speed of the lining silicon oxide layer 22 here is relatively slow, so that it is formed at the top and bottom corners of the trench. The thickness of 20a, 20b is relatively thin. Next, a silicon monoxide layer 24 is formed on the silicon nitride layer 14 by high density plasma chemical vapor deposition (high density plasma CVD, HDPCVD), and fills up the trench 20 .

Next, referring to FIG. 1d, a chemical mechanical polishing (CMP) process is performed to remove the redundant silicon oxide layer 24 on the silicon nitride layer 14, so as to form a shallow trench isolation structure 24a with a flat surface. Finally, the silicon nitride layer 14 and the pad silicon oxide layer 12 are removed to complete the shallow trench isolation process, and the structure shown in FIG. 1e is obtained.

Since the wet etching rate of the shallow trench isolation structure 24a for hydrofluoric acid (HF) is faster than that of the pad silicon oxide layer 12 and the liner silicon oxide layer 22, when the pad silicon oxide layer 12 is removed by dipping with hydrofluoric acid, The STI structure 24a is etched, exposing the trench top corner 20a and causing a recess 26 next to the trench top corner 20a.

The depression 26 will cause the concentration of the electric field, leading to _the deterioration of the insulation properties, thus causing abnormal device properties, _such as double peaks ( double hump) of the neck knot effect (kink effect). In addition, the silicon oxide layer 22 lining the bottom corner 20b of the trench is relatively thin, which is likely to cause stress concentration, which also leads to deterioration of insulation properties and leakage current.

Contents of the invention

In view of this, the object of the present invention is to provide a method for forming a shallow trench isolation structure, which first forms a silicon layer on the surface of the trench, and then oxidizes it as a lining silicon oxide layer, to replace the traditional process of using heat The lining silicon oxide layer formed by oxidation method.

Another object of the present invention is to provide a method for forming a shallow trench isolation structure, which forms a liner silicon oxide layer whose etching rate is lower than that of the insulating layer used to fill the trench, so as to prevent the top corner of the isolation structure from being damaged due to over-etching. A depression is formed.

The present invention provides a method for forming a shallow trench isolation structure, which at least includes the following steps:

providing a base 30 on which a mask layer 35 is formed;

Etching the mask layer 35 to form at least one opening 38 and exposing the surface of the substrate 30;

etching the substrate 30 below the opening 38 to form a trench 40 in the substrate 30;

conformally forming a silicon layer 42 on the mask layer 35 and the surface of the trench 40;

Oxidizing the silicon layer 42 to form a lining silicon oxide layer 42a on the mask layer 35 and the surface of the trench 40;

forming an insulating layer 44 above the mask layer 35 and filling the trench 40;

removing the insulating layer 44 and the lining silicon oxide layer 42a above the mask layer 35;

And removing the mask layer 35 .

In the method for forming a shallow trench isolation structure, the substrate 30 is a silicon substrate.

In the method for forming a shallow trench isolation structure, the mask layer 35 includes a silicon nitride layer 34 .

In the method for forming the shallow trench isolation structure, the silicon layer 42 is formed by any one of low pressure chemical vapor deposition and single reaction chamber chemical vapor deposition.

In the method for forming the shallow trench isolation structure, the silicon layer is any one of a polycrystalline silicon layer and an amorphous silicon layer.

In the method for forming a shallow trench isolation structure, the thickness of the silicon layer 42 is in the range of 50 to 300 angstroms.

In the method for forming the shallow trench isolation structure, the thickness of the silicon layer 42 is about 150 angstroms.

In the method for forming a shallow trench isolation structure, the lining silicon oxide layer is formed by a high temperature furnace tube oxidation method.

In the method for forming the shallow trench isolation structure, the temperature for forming the liner silicon oxide layer 42a is in the range of 800°C-1200°C.

In the method for forming a shallow trench isolation structure, the insulating layer 44 is a high-density plasma oxide layer.

Because the etching rate of the liner silicon oxide layer 42a in the top corner 40a of the trench is lower than that of the trench isolation structure 44a, no recess will be caused, and the neck junction effect described in the prior art can be avoided. In addition, the method according to the present invention can form a rounded liner silicon oxide layer 42a at the bottom corner 40b of the trench, thereby preventing leakage current caused by stress concentration.

Description of drawings

Figures 1a to 1e are schematic cross-sectional views of traditionally fabricated shallow trench isolation structures;

2a to 2f are schematic cross-sectional views of the shallow trench isolation structure manufactured by the present invention.

Symbol Description

10, 30 Substrate 12, 32 Pad silicon oxide layer

14, 34 Silicon nitride layer 16, 36 Photoresist layer

18, 38 Opening 20, 40 Groove

20a, 40a Trench top corner 20b, 40b Trench bottom corner

22, 42a lining silicon oxide layer 24 silicon oxide layer

24a, 44a Shallow trench isolation structure 26 Recess

35 veil layer 42 silicon layer

44 insulation layer

Detailed ways

A method for forming a shallow trench isolation structure according to a specific embodiment of the present invention will be described below with reference to FIGS. 2 a to 2 f.

First, referring to FIG. 2a, a substrate 30 is provided, such as a silicon substrate, and a mask layer 35 is formed on the surface of the substrate 100. The preferred thickness of the mask layer 35 is 200-3500 angstroms, which can be a single-layer structure or Stacked structure of several layers.

As shown in the figure, the mask layer 35 is preferably composed of a pad silicon oxide layer 32 and a thicker silicon nitride layer 34 . Wherein, the method for forming the pad silicon oxide layer 32 may be thermal oxidation or deposited by known atmospheric or low pressure chemical vapor deposition (LPCVD). The silicon nitride layer 34 on the pad silicon oxide layer 32 can be deposited by low pressure chemical vapor deposition using dichlorosilane (SiCl ₂ H ₂ ) and ammonia gas (NH ₃ ) as raw materials.

Next, a photoresist layer 36 is formed on the surface of the mask layer 35 . Afterwards, an opening is formed in the photoresist layer 36 according to a known lithography process, and the opening is used to define a trench isolation region.

Next, using the photoresist layer 36 with openings as an etching mask, an anisotropic etching process, such as reactive ion etching (reactiveion etching, RIE), is performed to transfer the opening pattern of the photoresist layer 36 to the mask layer. 35 and an opening 38 is formed therein.

Next, please refer to FIG. 2 b, after removing the photoresist layer 36 with a suitable etching solution or ashing treatment, the mask layer 35 is used as an etching mask to perform an anisotropic etching process, such as reactive ion etching, to open the opening Substrate 30 below 38 is etched to a predetermined depth to form trench 40 with a depth of about 3000-6000 Angstroms.

Next, please refer to FIG. 2c and FIG. 2d to carry out the key steps of the present invention, by known deposition techniques, such as low pressure chemical vapor deposition (LPCVD) or single reaction chemical vapor deposition (single-chamber CVD) on silicon nitride A silicon layer 42 , such as a polycrystalline silicon layer or an amorphous silicon layer, is deposited conformally on layer 34 and on the surface of trench 40 . In this specific embodiment, the process temperature required to deposit the polysilicon layer is about 580°C-630°C, and the required process pressure is in the range of 0.2 to 0.5 Torr, and the preferred temperature and pressure are 600 ℃ and 0.25 Torr. In addition, the process temperature required for depositing the amorphous silicon layer is about 500° C.-550° C., and the required process pressure is in the range of 0.25 to 1 Torr, and the preferred temperature and pressure are 520° C. and 1 Torr respectively. Additionally, the thickness of silicon layer 42 is in the range of 50 to 300 angstroms, with a preferred thickness of about 150 angstroms.

Next, please refer to FIG. 2d, by high temperature oxidation and passing oxygen (O ₂ ) or other oxidizing gases, such as ozone (O ₃ ), to oxidize the silicon layer 42 and in the silicon nitride layer 34 A lining silicon oxide layer 42a is formed on the surface of the trench 40 . It is characterized in that the process temperature required for forming the lining silicon oxide layer 42a is about 800° C.-1200° C., preferably 1050° C., and the required process pressure is about 1 atm. In addition, the thickness of the formed lining silicon oxide layer 42a is about 100-300 angstroms.

Next, an insulating layer 44 is formed on the mask layer 35 and filled into the trench 40 . The aforementioned insulating layer 44 can be made of undoped silicon oxide. The undoped silicon oxide includes silicon oxide composed of tetraethyl silicate (TEOS), or high density plasma silicon oxide (HDPoxide). In this embodiment, the insulating layer 44 is made of high-density plasma silicon oxide, and its deposition method is high-density plasma chemical vapor deposition (HDPCVD). Afterwards, a tempering process or rapid thermal process (rapid thermal process, RTP) is performed to densify the insulating layer 44 .

In this embodiment, since the etching rate of the lining silicon oxide layer 42a formed by the high-temperature furnace tube oxidation method is lower than that of the insulating layer 44 (high-density plasma silicon oxide), the mask layer 35 is subsequently removed, And other wet processing procedures 65, can avoid the liner silicon oxide layer 42a being over-etched to produce deep recesses at the top corners 40a of the trenches.

In addition, the silicon oxide layer 42 a lining the bottom corner 40 b of the trench is not directly formed by the silicon oxide substrate 30 , but is formed by the silicon oxide layer 42 . Therefore, a rounded liner silicon oxide layer 42a can be formed at the bottom corner 40b of the trench. Next, referring to FIG. 2e, the excess insulating layer 44 and the lining silicon oxide layer 42a above the mask layer 35 can be removed by etching back or chemical mechanical polishing (CMP) to form a shallow trench isolation structure 44a.

Finally, referring to FIG. 2f, the mask layer 35 is peeled off. It is characterized in that the method for stripping the silicon nitride layer 34 is a wet etching method, such as soaking hot phosphoric acid as an etching solution to remove it; the method for stripping the pad silicon oxide layer 32 is a wet etching method, which is, for example, Soak in hydrofluoric acid as etching solution.

While stripping the pad silicon oxide layer 32, part of the shallow trench isolation structure 44a will also be partially stripped. However, as mentioned above, since the etching rate of the lining silicon oxide layer 42a in the top corner 40a of the trench is lower than that of the trench isolation structure 44a, no dishing will be caused, and the neck junction effect described in the prior art can be avoided. In addition, the method according to the present invention can form a rounded liner silicon oxide layer 42a at the bottom corner 40b of the trench, thereby preventing leakage current caused by stress concentration.

The above is only a preferred embodiment of the present invention, but the protection scope of the present invention is not limited thereto. Any person familiar with the technology can easily think of changes or changes within the technical scope disclosed in the present invention. All replacements shall fall within the protection scope of the present invention. Therefore, the protection scope of the present invention should be determined by the protection scope of the claims.

Claims (10)

1, a kind of method that forms fleet plough groove isolation structure is characterized in that comprising the following steps: to provide a substrate at least, is formed with a cover curtain layer on it; This cover curtain layer of etching is to form at least one opening and to expose this substrate surface; The substrate of this opening below of etching is to form a groove in this substrate; The surperficial compliance that reaches this groove on this cover curtain layer forms a silicon layer; This silicon layer of oxidation forms a lining silicon oxide layer to reach this flute surfaces on this cover curtain layer; Above this cover curtain layer, form an insulating barrier and fill up this groove; Remove this insulating barrier and this lining silicon oxide layer of this cover curtain layer top; And remove this cover curtain layer.

2, the method for formation fleet plough groove isolation structure as claimed in claim 1 is characterized in that this substrate is a silicon base.

3, the method for formation fleet plough groove isolation structure as claimed in claim 1 is characterized in that this cover curtain layer comprises a silicon nitride layer.

4, the method for formation fleet plough groove isolation structure as claimed in claim 1 is characterized in that by any of Low Pressure Chemical Vapor Deposition and single reactor chemical vapour deposition technique to form this silicon layer.

5, the method for formation fleet plough groove isolation structure as claimed in claim 1 is characterized in that this silicon layer is any of a compound crystal silicon layer and noncrystalline silicon layer.

6, the method for formation fleet plough groove isolation structure as claimed in claim 1 is characterized in that the scope of the thickness of this silicon layer at 50 to 300 dusts.

7, the method for formation fleet plough groove isolation structure as claimed in claim 1 is characterized in that the thickness of this silicon layer is about 150 dusts.

8, the method for formation fleet plough groove isolation structure as claimed in claim 1 is characterized in that forming this lining silicon oxide layer by the high temperature furnace pipe oxidizing process.

9, the method for formation fleet plough groove isolation structure as claimed in claim 8, the temperature that it is characterized in that forming this lining silicon oxide layer is 800 ℃-1200 ℃ scope.

10, the method for formation fleet plough groove isolation structure as claimed in claim 1 is characterized in that this insulating barrier is a high-density electric slurry oxide layer.

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