CN1452229A - Secondary half-etching preparation method and packaging structure of image sensor single-layer lead frame - Google Patents
Secondary half-etching preparation method and packaging structure of image sensor single-layer lead frame Download PDFInfo
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Abstract
Description
技术领域technical field
本发明涉及影像传感器,尤其涉及一种采用上下两次半蚀刻制备方法制作芯片座与引脚立体结构的影像传感器单层导线架二次半蚀刻制备方法及其封装结构。The invention relates to an image sensor, in particular to a method for preparing a single-layer lead frame of an image sensor with a two-time half-etching preparation method and a packaging structure thereof for manufacturing a three-dimensional structure of a chip holder and pins.
背景技术Background technique
参阅图6至图9所示,其为现有的影像传感器(Image sensor)封装技术,现有的导线架(Lead frama)制作方法为冲压式或堆栈式。其中,冲压式制作方法是先在平板状导体基材蚀刻(Etching)出芯片座(Die pad)71与各引脚(Lead)72的位置与形状,再由底部冲压芯片座71使其浮出引脚72平面。另外,冲压式制作方法也有直接冲压导体平板,直接冲出芯片座71与各引脚72立体结构的方式,但是这两种方式都需要经机械冲压加工,不容易达到准确的尺寸精度,因此不适合现代影像感测芯片普遍小面积大量引脚的封装要求;而且,冲压过程不容易控制引脚72的平整度,通常需要配合引脚72的导正程序,这对于现今高密度、高画素的影像感测芯片封装技术要求,确实难以适应,也不易使产品达到良好质量。Referring to FIGS. 6 to 9 , they are the existing image sensor (Image sensor) packaging technology, and the existing lead frame (Lead frame) manufacturing method is stamping or stacking. Among them, the stamping method is to etch the position and shape of the die pad 71 and each lead 72 on the flat conductor substrate, and then punch the die pad 71 from the bottom to make it float out. pin 72 plane. In addition, the stamping method also has the method of directly stamping the conductor plate, and directly punching out the three-dimensional structure of the chip holder 71 and each pin 72, but both of these methods need to be processed by mechanical stamping, and it is not easy to achieve accurate dimensional accuracy. It is suitable for the packaging requirements of modern image sensor chips with a small area and a large number of pins; moreover, it is not easy to control the flatness of the pin 72 in the stamping process, and it is usually necessary to cooperate with the alignment process of the pin 72, which is suitable for today's high-density, high-pixel It is indeed difficult to adapt to the technical requirements of image sensor chip packaging, and it is not easy to make products of good quality.
如图7所示,现有的另一种堆栈式制作方法,是以两道手续分别制作上下两层的导线架样板81、82,上层样板81包括芯片座83与各引脚84,下层样板82仅包括各引脚85;上下层样板81、82堆栈后,芯片座83底部相对于引脚85底面凹入,通过塑料封装与电性隔离,其整体封装过程如图8、图9所示。然而,这种堆栈方式涉及上下两层样板81、82的尺寸精度配合问题,对于小面积、大量引脚84、85的影像感测芯片封装,细腻的引脚,高精度的要求,这种制备过程同样具有困难,不容易保证产品质量良好;再者,两导线架样板81、82的接触电阻也是一个难题,不容易良好控制至一均匀水准,而影响微细感测信号传递的效果,确实有改进的必要。As shown in Figure 7, another existing stacking manufacturing method is to make two upper and lower layers of
发明内容Contents of the invention
为了克服现有的产品制备方法存在的上述缺点,本发明提供一种影像传感器单层导线架二次半蚀刻制备方法及其封装结构,其以两次半蚀刻过程,克服上述现有技术存在的难题,由于导线架的立体结构是以两次半蚀刻制备过程制作,精度可以达到集成电路的微米等级,因而与感测芯片信号接点的焊接可以有更好的精度配合,从而可以适用当今高密度、高画素的影像感测芯片封装技术的要求,能够保证产品质量的良好;另外,本发明两次半蚀刻过程是化学加工,精度可达分子等级,同时避免机械冲压过程,因而可以更好的控制引脚的平整度,完全不需要配合引脚导正程序,同时也解决了堆栈式制备方法接触电阻的问题,制造精度及速度一次完成;再者,对后续的焊线封装过程也可保证更好的信赖质量;还有,两次半蚀刻过程可完全在同一机台完成,免去中途运送导线架至他处冲压的成本,同时节省加工时间,提高产量,实用效果理想。In order to overcome the above-mentioned shortcomings of the existing product preparation methods, the present invention provides a method for preparing a single-layer lead frame of an image sensor by half-etching twice and its packaging structure. Difficulties, because the three-dimensional structure of the lead frame is made by two half-etching preparation processes, the precision can reach the micron level of the integrated circuit, so the welding with the sensor chip signal contact can have better precision, so it can be applied to today's high-density , high-pixel image sensing chip packaging technology requirements, can ensure good product quality; in addition, the present invention twice half-etching process is a chemical process, the precision can reach the molecular level, while avoiding the mechanical stamping process, so it can be better Controlling the flatness of the pins does not need to cooperate with the pin alignment program at all, and also solves the problem of contact resistance in the stacking method, and the manufacturing accuracy and speed are completed at one time; moreover, the subsequent wire bonding packaging process can also be guaranteed Better trust in quality; in addition, the two half-etching processes can be completely completed on the same machine, eliminating the cost of transporting the lead frame to another place for stamping, saving processing time and increasing output, and the practical effect is ideal.
本发明解决其技术问题所采用的技术方案是:The technical solution adopted by the present invention to solve its technical problems is:
本发明影像传感器的单层导线架二次半蚀刻(Etching)制备方法,其特征在于,该制备方法包括:第一步骤:在平板状导体基材的顶面以半蚀刻方式蚀出芯片座(die pad)与各引脚(lead)的位置与形状,并在适当位置蚀出数个通孔,以利于后续塑料预模的镶嵌固定;第二步骤:在平板状导体基材的底面以半蚀刻方式,在芯片座底部与各引脚内侧底部蚀出凹入结构,进行塑料预模的镶嵌与电性隔离;第三步骤:将第一、第二步骤蚀刻完成的导线架(lead fram)进行电镀处理,再以射出方式镶嵌在塑料预模之中,该塑料预模在芯片座周围形成凸墙;然后将感测芯片(chip)胶粘在芯片座的顶面,并在感测芯片与各引脚内侧顶面间焊线(Wire bonding),最后在塑料预模的凸墙顶面粘贴玻璃盖板,以包覆该感测芯片,完成封装程序。The second half-etching (Etching) preparation method of the single-layer lead frame of the image sensor of the present invention is characterized in that the preparation method comprises: a first step: half-etching the chip holder ( die pad) and the position and shape of each pin (lead), and etched several through holes at appropriate positions to facilitate the inlay and fixation of the subsequent plastic pre-mold; the second step: halfway on the bottom surface of the flat conductor substrate Etching method, etch the concave structure at the bottom of the chip holder and the inner bottom of each pin to inlay and electrically isolate the plastic pre-mold; the third step: the lead frame (lead frame) that is etched in the first and second steps Electroplating treatment is carried out, and then embedded in the plastic pre-mold by injection, the plastic pre-mold forms a convex wall around the chip holder; then the sensing chip (chip) is glued on the top surface of the chip holder, and the sensing chip Wire bonding to the inner top surface of each pin, and finally stick a glass cover plate on the top surface of the convex wall of the plastic pre-mold to cover the sensing chip and complete the packaging process.
前述的影像传感器的单层导线架二次半蚀刻(Etching)制备方法,其特征在于,所述芯片座蚀刻出数个贯穿的通孔,使塑料预模射出过程在芯片座顶面形成数个凸粒,以控制感测芯片粘贴的水平角度,防止感测芯片倾斜,影响焊线质量。The aforementioned single-layer lead frame secondary half-etching (Etching) preparation method of the aforementioned image sensor is characterized in that the chip seat is etched with several through holes, so that the plastic pre-mold injection process forms several holes on the top surface of the chip seat. Bumps, to control the horizontal angle of the sensing chip paste, to prevent the sensing chip from tilting and affect the quality of the bonding wire.
前述的影像传感器的单层导线架二次半蚀刻(Etching)制备方法,其特征在于,所述各引脚适当位置蚀出锚孔,各引脚锚孔,在塑料预模射出过程,作为塑料预模固定于导线架的基础,强化塑料预模与各引脚的接合,提高封装的质量。The aforementioned single-layer lead frame secondary half-etching (Etching) preparation method of the image sensor is characterized in that anchor holes are etched out at the appropriate positions of the pins, and the anchor holes of each pin are used as plastic during the injection process of the plastic pre-mold. The pre-mold is fixed on the base of the lead frame, and the bonding between the plastic pre-mold and each lead is strengthened, and the quality of the package is improved.
前述的影像传感器的单层导线架二次半蚀刻(Etching)制备方法,其特征在于,所述各引脚内侧环绕芯片座周缘定义为内引脚(inner lead),其作为连接感测芯片的信号接点,各引脚外侧延伸至封装体下缘定义为外引脚(out lead),其作为焊接外部印刷电路版的SMT接脚。The aforementioned single-layer lead frame secondary half-etching (Etching) preparation method of the aforementioned image sensor is characterized in that the inside of each pin is defined as an inner lead around the periphery of the chip seat, which serves as a lead for connecting the sensing chip. The signal contact, each pin extending from the outside to the lower edge of the package is defined as an out lead, which is used as an SMT pin for soldering an external printed circuit board.
本发明影像传感器的单层导线架二次半蚀刻(Etching)制备方法的封装结构,包括感测芯片、导线架与玻璃盖板;其特征在于,所述导线架为单层导线架,其具有一芯片座与数个引脚,各引脚内侧环绕芯片座周缘,各引脚外侧延伸至封装体下缘与外部印刷电路板的SMT接脚焊接;所述感测芯片粘贴在芯片座顶面,并以金属线连接各引脚内侧顶面以传递电信号;所述玻璃盖板覆盖在感测芯片上方,由塑料材料使上述三者封装为一体。The package structure of the single-layer lead frame secondary half-etching (Etching) preparation method of the image sensor of the present invention includes a sensing chip, a lead frame and a glass cover plate; it is characterized in that the lead frame is a single-layer lead frame, which has A chip seat and several pins, the inner side of each pin surrounds the periphery of the chip seat, and the outer side of each pin extends to the lower edge of the package body to be welded with the SMT pins of the external printed circuit board; the sensing chip is pasted on the top surface of the chip seat , and connect the inner top surface of each pin with a metal wire to transmit electrical signals; the glass cover plate covers the sensor chip, and the above three are packaged as one by plastic material.
本发明的有益效果是,可以解决现有导线架机械冲压制备过程所导致的问题,从而提供了一种单层导线架二次半蚀刻制备方法与封装结构,由于导线架2的立体结构是以两次半蚀刻过程制作,精度可达到集成电路的微米等级,因而与感测芯片1信号接点的焊接可以有更好的精度配合,对于当今高密度、高画素的影像感测芯片封装,实为优选的方法,容易保证良好的产品质量。其次,本发明两次半蚀刻过程属于化学加工,精度可达分子等级,同时避免了机械冲压制作过程,因而引脚22的平整度可以得到更好的控制,完全不需要配合引脚22的导正程序,也解决了堆栈式制备方法接触电阻的问题,制造精度及速度一次完成。再者,确实保证后续的焊线封装的质量。还有,两次半蚀刻过程可完全在同一机台完成,免去中途运送导线架2至他处冲压的成本,同时可以节省加工时间,提高产量,实用效果理想,达到预期的设计目的。The beneficial effect of the present invention is that it can solve the problems caused by the mechanical stamping preparation process of the existing lead frame, thereby providing a single-layer lead frame secondary half-etching preparation method and packaging structure, because the three-dimensional structure of the
附图说明Description of drawings
下面结合附图和实施例对本发明进一步说明。The present invention will be further described below in conjunction with the accompanying drawings and embodiments.
图1为本发明导体基材顶面半蚀刻侧视示意图。Fig. 1 is a schematic side view of the half-etched top surface of the conductor substrate of the present invention.
图2为本发明导体基材底面半蚀刻侧视示意图。Fig. 2 is a schematic side view of the half-etched bottom surface of the conductor substrate of the present invention.
图3为本发明导线架电镀示意图。Fig. 3 is a schematic diagram of the electroplating of the lead frame of the present invention.
图4为本发明导线架蚀刻完成状态俯视示意图。FIG. 4 is a schematic top view of the lead frame of the present invention in an etching-completed state.
图5为本发明感测芯片封装完成示意图。FIG. 5 is a schematic diagram of the completion of the sensing chip package of the present invention.
图6为现有冲压式导线架制备方法封装完成示意图。FIG. 6 is a schematic diagram showing the completion of encapsulation in the conventional manufacturing method of stamping type lead frame.
图7为现有堆栈式导线架侧视示意图。FIG. 7 is a schematic side view of a conventional stacked lead frame.
图8为现有堆栈式导线架塑料预模镶嵌示意图。FIG. 8 is a schematic diagram of the existing stacked lead frame plastic pre-mold inlay.
图9为现有堆栈式导线架制备方法封装完成示意图。FIG. 9 is a schematic diagram of the completion of encapsulation in the conventional stacked lead frame manufacturing method.
图中标号说明Explanation of symbols in the figure
现有技术部分:71芯片座、72各引脚、81上层样板、82下层样板、83芯片座、84引脚、85引脚;Part of prior art: 71 chip holders, 72 pins, 81 upper model, 82 lower model, 83 chip holders, 84 pins, 85 pins;
本发明部分:1感测芯片、11金属线、2单层导线架、21芯片座、22引脚、221内引脚、222外引脚、23通孔、24锚孔、25凹入结构、3塑料预模、31凸粒、32凸墙、4玻璃盖板。Parts of the present invention: 1 sensing chip, 11 metal wire, 2 single-layer lead frame, 21 chip seat, 22 pins, 221 inner pins, 222 outer pins, 23 through holes, 24 anchor holes, 25 recessed structure, 3 plastic pre-molds, 31 convex grains, 32 convex walls, 4 glass cover plates.
具体实施方式Detailed ways
参阅图1至图5所示,本发明是有关一种影像传感器之单层导线架二次半蚀刻制备方法及其封装结构。Referring to FIG. 1 to FIG. 5 , the present invention relates to a method for preparing a single-layer lead frame of an image sensor by secondary half-etching and its packaging structure.
如图5所示,本发明影像传感器的结构包括:一感测芯片1,一单层导线架2与一玻璃盖板4;该导线架设有一芯片座21与数个引脚22,各引脚22内侧环绕芯片座21周缘定义为内引脚(inner lead)221,其是用于连接感测芯片1的信号接点,各引脚22外侧延伸至封装体下缘定义为外引脚(outlead)222,其是用于焊接外部印刷电路板的SMT接脚,以传递电信号;该感测芯片1粘贴在芯片座21的顶面,并用金属线11连接各内引脚221顶面,而将感测芯片1的各信号接点连接至外界信号接脚,以利感测芯片1与外界通讯;该玻璃盖板4覆盖在感测芯片1的上方,以保护该感测芯片1,并利于光线穿透至感测芯片1;以上三者是以塑料材料封装为一体,其主要制备程序如下:As shown in Figure 5, the structure of the image sensor of the present invention includes: a sensing chip 1, a single-
第一步骤:如图1所示,在平板状导体基材的顶面以半蚀刻方式蚀出芯片座21与各引脚22的位置与形状,并在适当位置蚀出数个贯穿的通孔23、锚孔24;其中,通孔23在后续塑料预模3射出的过程,将在芯片座21顶面形成数个凸粒31,以控制感测芯片1粘贴至芯片座21时的水平角度,防止感测芯片1倾斜,影响后续焊线的质量,另一方面,其也强化塑料预模3与芯片座21的接合;位于各引脚22适当位置的锚孔24,在塑料预模3射出的过程,将作为塑料预模3固定在导线架2的基础,强化塑料预模3与各引脚22的接合,增加整体封装质量的可信赖度。The first step: as shown in FIG. 1, the position and shape of the
第二步骤:如图2所示,在平板状导体基材的底面再以半蚀刻方式,在芯片座21底部与各内引脚22底部蚀出凹入结构25,以利塑料预模3的镶嵌与电性隔离,经过两次半蚀刻过程,如图2、图4所示,整体导线架2的立体结构已经成型。The second step: as shown in Figure 2, on the bottom surface of the flat conductor base material, etch the
第三步骤:如图3所示,将第一、第二步骤蚀刻完成的导线架2进行电镀处理;再如图5所示,以射出方式将导线架2镶嵌在塑料预模3之中,并且在该塑料预模3与芯片座21周围形成凸墙32,然后将感测芯片1以银胶胶粘在芯片座21顶面,并在感测芯片1与各内引脚221顶面间焊接金属线11,以利电信号传导;再在塑料预模3的凸墙32顶面通过UV胶粘贴玻璃盖板3,以包覆该感测芯片1,完成封装制作程序。The third step: as shown in Figure 3, the
以上所述,仅是本发明的较佳实施例而已,并非对本发明作任何形式上的限制,凡是依据本发明的技术实质对以上实施例所作的任何简单修改、等同变化与修饰,均仍属于本发明技术方案的范围内。The above are only preferred embodiments of the present invention, and are not intended to limit the present invention in any form. Any simple modifications, equivalent changes and modifications made to the above embodiments according to the technical essence of the present invention still belong to within the scope of the technical solutions of the present invention.
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2003
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| CN101252096B (en) * | 2007-11-16 | 2010-08-11 | 日月光半导体制造股份有限公司 | Chip packaging structure and manufacturing method thereof |
| CN101866867A (en) * | 2010-06-18 | 2010-10-20 | 日月光封装测试(上海)有限公司 | Lead frame manufacturing method for semiconductor package structure without outer leads |
| CN102593271A (en) * | 2011-01-14 | 2012-07-18 | 九介企业股份有限公司 | Light-emitting diode packaging structure and method for forming lead frame of slot-type packaging |
| CN102842515A (en) * | 2011-06-23 | 2012-12-26 | 飞思卡尔半导体公司 | Method for assembling semiconductor device |
| CN104425528A (en) * | 2013-08-19 | 2015-03-18 | 索尼公司 | Imaging apparatus and electronic apparatus |
| CN104425528B (en) * | 2013-08-19 | 2018-10-16 | 索尼公司 | Imaging device and electronic device |
| CN103531486A (en) * | 2013-09-28 | 2014-01-22 | 宁波康强电子股份有限公司 | Method for manufacturing lead frame |
| CN103531486B (en) * | 2013-09-28 | 2016-08-17 | 宁波康强电子股份有限公司 | A kind of preparation method of lead frame |
| TWI899076B (en) * | 2019-06-11 | 2025-10-01 | 新加坡商安靠科技新加坡控股私人有限公司 | Semiconductor device and method of manufacturing a semiconductor device |
| TWI758227B (en) * | 2021-09-06 | 2022-03-11 | 復盛精密工業股份有限公司 | Manufacturing method of package lead frame |
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