CN1332287C

CN1332287C - Frequency voltage device for power management and method for frequency voltage control

Info

Publication number: CN1332287C
Application number: CNB2004100941779A
Authority: CN
Inventors: 达瑞恩斯·D.·盖金斯
Original assignee: Via Technologies Inc
Current assignee: Via Technologies Inc
Priority date: 2003-12-17
Filing date: 2004-12-17
Publication date: 2007-08-15
Anticipated expiration: 2024-12-17
Also published as: CN1645293A

Abstract

The invention provides a frequency voltage device and a frequency voltage control method for power management. The first phase-locked loop generates a first source pulse signal at a first frequency. The second phase-locked loop generates a second source pulse signal at a second frequency. The selection logic circuit generates a core pulse signal. The pulse control logic circuit generates a first frequency control signal and generates a selection signal. The voltage control logic circuit is used for adjusting the operating voltage corresponding to the frequency of the core pulse signal. By using the present invention, not only can significant power efficiency advantages be created, but power consumption can also be dynamically adjusted without excessive delay.

Description

The method of the voltage mechanism of power management and voltage to frequency control

The mutual reference of related application

The application of the application's right of priority is according to this United States Patent (USP) provisional application, application number: 60/530323, and the applying date: 12/17/2003; Also according to U.S. Patent application, application number 10/816004, the applying date: 04/01/2004.

The application is relevant with the U.S. patent application case in the following application that coexists, and all have the identical applying date, applicant and inventor that at least one is identical, and it can be incorporated herein by reference all at this.

Application case number	Date of application	Title
Application case number	Date of application	Title	10/816020	2004/4/1	INSTANTANEOUS FREQUENCY-BASED MICROPROCESSOR POWER MANAGEMENT moment is based on the power supply of microprocessor management of frequency

Technical field

The present invention manages relevant for power supply of microprocessor, and more especially relevant for proposing can not cause the mode of excessive deferral, and the voltage regulation techniques of more only adjusting frequency has more the mode of power advantage, and the device and method of the power of dynamically adjusting microprocessor and being consumed.

Background technology

The power consumption management is the computer system of the many patterns major issue of (comprising portable apparatus, laptop computer and so-called " green " computing machine).For example, battery life is the laptop computer user's of major part a major issue.Microprocessor can consume a large amount of power, so that be target with the technology that reduces power supply often.Microprocessor Design person's challenge is to propose to change the device of the power rating of microprocessor, and finish such conversion as soon as possible in mild and quite seamless mode.Known several difference reduces the technology of the power consumption of microprocessors, for example comprises the frequency of the core pulse signal that dynamically changes microprocessor.The frequency of the electrical source consumption of microprocessor and its core pulse signal is proportional.

Fig. 1 is the simplification calcspar of traditional power-supply management system 100, and it illustrates based on the power management of frequency and how to finish in existing microprocessor.Sensing interface 101 (for example, sensing bus or similar bus) can be sent to power management logic circuit 103 with one or more power sensing signals.103 meetings of power management logic circuit are based on the present and/or original state of the sensing signal of sensing interface 101, the power rating that decides microprocessor to carry out.The sensing signal of the example on the sensing interface 101 for example comprises by software (mechanical specific register, converter temperature (not shown), remaining power supply signal equivalence of being write as operating system (operating system, OS) software or similar software).In order to carry out in particular power state, power management logic circuit 103 can be set core ratio (core ratio, the CORERATIO) numerical value of bus, and be sent to PLL (phase lock loop, PLL) 105.PLL 105 can produce the core pulse signal, and it is the frequency of bus pulse signal, and the numerical value that comes from the core ratio bus of power management logic circuit 103, and wherein the core pulse signal can feed back to PLL 105.For example, core pulse rate value is three (3), will indicate PLL 105, is produced as the core pulse signal of the treble frequency of bus pulse signal.

As understood by those skilled in the art, PLL 105 can increase the external bus pulse signal exponentially, and produces inner employed core pulse signal.For example, during sufficient power supply situation, the bus pulse signal of 500MHz can multiply by 8 (for example, core ratio=8), and drives the machine of 4.0GHz.PLL 105 can keep homophase with core pulse signal and bus pulse signal.The numerical value that is produced via the core ratio bus represents to be used to reduce the reduction frequency of power potential, the power potential as 25% (core ratio=2), 50% current potential (core ratio=4), current potential (core ratio=6) of 75% or the like.

Because the PLL 105 in the conventional power source management system 100 has significant delay when making a frequency change to next frequency, so use traditional power-supply management system 100, in the power rating fashion that dynamically changes microprocessor some shortcomings are arranged.This delay comes down to the stratum as hundreds of recurrence intervals.During each PLL frequency shift delay, computer system can temporarily stop.For example, when on microprocessor, carrying out suitable simple functions (as DVD decoding or similar functions), then probably can carry out, and save power because of reduction frequency (as half frequency) as if application program.Power management logic circuit 103 can detect the power sensing signal that reduces power rating in order to expression, and via the core ratio bus, and indication PLL 105 reduces frequency.When PLL 105 reduces frequency, the delay that can match.In addition, reduce frequencies in the near future during PLL 105 reduction frequencies or at PLL 105, OS can wake other work up, goes back to operating frequency originally.Such incident can cause extra delay and usefulness to reduce, and goes back up to the complete operation frequency up to PLL 105.Taking place sometimes to pin in the application apparatus of phenomenon, it is just to detect by the user often that these frequency shifts postpone.Therefore, existing frequency modulating technology can produce adverse influence for overall efficiency.

Summary of the invention

A kind of voltage mechanism that is used for power management according to one embodiment of the invention comprises first PLL (PLL) and second PLL, selection logical circuit, pulse control logic circuit and Control of Voltage logical circuit.First PLL is based on the bus pulse signal, and generation is in the first source pulse signal of first frequency.Second PLL is based on first frequency control signal and bus pulse signal, and generation is in the second source pulse signal of second frequency.Select logical circuit based on the selection signal, and between the first source pulse signal and second source pulse signal, select, and produce the core pulse signal.The pulse control logic circuit is via at least one power sensing signal, comes the detection power situation, in order to according to power situation, selects signal and produce the first frequency control signal and produce.The Control of Voltage logic circuits coupled is to the pulse control logic circuit, and in order to the frequency corresponding operating voltage of adjustment with the core pulse signal, extremely the frequency with this core pulse signal matches.

What recognize is, this voltage mechanism proposes can not causing the mode of excessive deferral, and the voltage regulation techniques of more only adjusting frequency has more the mode of power advantage, and dynamically adjusts the device of the power that is consumed.The pulse control logic circuit can be selected a source pulse signal, when the second source pulse signal arrives the frequency that needs, can switch then.Switch and to be actually that moment takes place, as for example being in a recurrence interval of bus pulse signal.First PLL can be embodied as fixed frequency device (for example, being in the maximum frequency current potential), or as with the similar programmable device of second PLL.For example, first PLL can come source signal and produce first frequency based on the second frequency control signal, and produces the second pinning signal of representing it.In this case, the pulse control logic circuit can produce the second frequency control signal, and can receive the second pinning signal.

In various embodiments, when the second source pulse signal arrived by the represented reduction frequency of first frequency control signal, second PLL can produce first frequency and pin signal.In this case, the pulse control logic circuit can respond first frequency and pin signal, and the core pulse signal is switched to second PLL from first PLL.After switching the core pulse signal, the Control of Voltage logical circuit can reduce operating voltage.The Control of Voltage logical circuit can be in response to increasing power situation, and increase operating voltage, and after increasing operating voltage, the pulse control logic circuit can switch to first PLL then.If first PLL is able to programme, then before switching, the pulse control logic circuit can wait for further that second pins signal.In one embodiment, pulse control logic circuit and Control of Voltage logical circuit can operate together, just increasing operating voltage before the frequency that increases the core pulse signal, and just reduce operating voltage after the frequency that reduces the core pulse signal.

Power supply unit is adjusted operating voltage based on the voltage step signal that comes from the Control of Voltage logical circuit.Power supply unit can pin the voltage of representing it signal and be sent to the pulse control logic circuit.Therefore, only after voltage was increased to suitable potential, the pulse control logic circuit just can increase the frequency of core pulse signal.

A kind of microprocessor according to one embodiment of the invention comprises power situation sensing interface, operating voltage interface, first PLL and second PLL, impulse controller, selection logical circuit and voltage controller.Power situation sensing interface is in order to receive at least one power sensing signal of expression power situation.First PLL is based on bus pulse signal and first frequency ratio bus value, is in first of a frequency and comes source signal and produce, and pin signal in order to produce one corresponding first.Second PLL is based on the bus pulse signal, and generation is in the second source signal of a frequency.Impulse controller is in order to produce in order to the selection signal that switches between first PLL and second PLL, in order to the first core ratio bus value that produces the frequency that control first comes source signal and in order to receive the first pinning signal.Select logical circuit based on the selection signal, and between first PLL and second PLL, select, and produce the core pulse signal.Voltage controller is coupled to this impulse controller and this operating voltage interface, in order to the frequency corresponding operating voltage of adjustment with the core pulse signal.

In various embodiments, second PLL can be fixing or able to programme.Impulse controller and voltage controller can operate together, with after the frequency that reduces the core pulse signal, can reduce operating voltage, and before the frequency that increases the core pulse signal, can increase operating voltage.

A kind of method that is used for the voltage to frequency control of power supply of microprocessor management comprises based on the bus pulse signal and the first ratio bus value, and produces the first source pulse that is in first frequency; Based on the bus pulse signal and the second ratio bus value, and produce the second source pulse that is in second frequency; The sense power situation; Based on the power situation of sensing, and switch the first core operation frequency of originating between pulse signal and the second source pulse signal; And the operating voltage that matches of selection and core operation frequency.

The method also can comprise the initial selection first source pulse signal; Based on the reduction power situation, and produce the second ratio bus value, to show the frequency that reduces; In response to the second ratio bus value, and make the second source pulse signal get back to the frequency of reduction; When the second source pulse signal arrives the frequency that reduces, detect first and pin indication; When detecting the pinning indication, switch to the second source pulse signal; And after this switches, reduce and the corresponding operating voltage of frequency that reduces.The method can be included in a bus and switch in the recurrence interval.The method can comprise that sensing increases power situation; Increase and the corresponding operating voltage of sense power situation; And switch to first the source pulse signal.In the situation of this latter, before switching to the first source pulse signal, the method can comprise that decision is suitable for increasing the increase power potential of power situation; Based on the increase power potential, and produce the first ratio bus value that expression increases frequency; Make the first source pulse signal get back to the increase frequency; Improve and the corresponding operating voltage of increase frequency; And when the first source pulse signal arrives the increase frequency, detect second and pin indication.

Utilize the voltage mechanism of power management of the present invention and the method for voltage to frequency control, can not cause the mode of excessive deferral, and the voltage regulation techniques of more only adjusting frequency has more the mode of power advantage, and the power of dynamically adjusting microprocessor and being consumed.

Description of drawings

Benefit of the present invention, characteristic and advantage will cooperate the following description, and accompanying drawing and become more understands, wherein:

Fig. 1 is the simplification calcspar that traditional power management is united, and it illustrates based on the power management of frequency and how to finish in existing microprocessor;

Fig. 2 is the calcspar of the voltage to frequency power-supply management system implemented according to one embodiment of the invention;

The calcspar of another voltage to frequency power-supply management system that Fig. 3 is according to another embodiment of the present invention to be implemented;

Fig. 4 is any the simplification calcspar of microprocessor that comprises in the voltage to frequency power-supply management system of Fig. 2 and 3; And

Fig. 5 is the process flow diagram that illustrates according to the example running of the power-supply management system of Fig. 3 of one embodiment of the invention.

Wherein, description of reference numerals is as follows:

100: power-supply management system

101: the sensing interface

103: the power management logic circuit

105: PLL (PLL)

200: the voltage to frequency power-supply management system

201: PLL (PLL)

203: PLL (PLL)

205: multiplexer

206: core logic circuit

207: the pulse control logic circuit

209: the sensing interface

211: voltage controller or Control of Voltage logical circuit

213: external power source supply (VRM)

215: voltage interface

300: the voltage to frequency power-supply management system

301: PLL (PLL)

400: microprocessor

401: pin

403: external interface

405: internal buffer

Embodiment

Below explanation makes general those skilled in the art can finish and use the present invention, is provided in this paper as application-specific and demand thereof.Yet, to those skilled in the art, will be obviously as can be known, and can be applicable to other embodiment in this defined rule to the various modifications of preferred embodiment.Therefore, the present invention is not intended to be subject to the specific embodiment of and explanation shown at this, but meets the principle that discloses at this and the widest scope of novelty.

For the purpose of power management, the present inventor has understood and need change the frequency speed of microprocessor in quick seamless mode, yet also can change voltage.Therefore, it has developed into a kind of device and method that is used for the voltage mechanism of power supply of microprocessor management, will cooperate Fig. 2～5, and be further detailed in beneath.

Fig. 2 is the calcspar of the voltage to frequency power-supply management system 200 implemented according to one example of the present invention embodiment.Power-supply management system 200 comprises two PLLs 201 and 203 (being shown as PLL 1 and PLL 2) of parallel running, and each is in order to receive the external bus pulse signal, as producing on the motherboard of computer system (not shown).PLL 201 can be exported first core source pulse signal (CORE SRC 1), and PLL 203 can be exported second core source pulse signal (CORE SRC 2), and these signals can be sent to the input separately (1 and 2) of multiplexer (MUX) 205.CORE SRC 1 signal can feed back to the input of PLL 201 according to the PLL running, and PLL 201 can make CORE SRC 1 signal and bus pulse signal keep synchronously.In a similar fashion, CORE SRC 2 signals can feed back to the input of PLL 203, and it can make CORE SRC 2 signals and bus pulse signal keep synchronously.The output meeting of multiplexer 205 is sent to core logic circuit 206 with the core pulse signal, and wherein, the core pulse signal can be based in order to receive selecting the selection input of signal (SEL), and is one of selection in CORE SRC 1 signal and CORE SRC 2 signals.Selected core pulse signal is used by the core logic circuit 206 of microprocessor 400 (Fig. 4).

For system 200, PLL 201 can be revised and carry out constantly, and the frequency of external bus pulse signal can multiply each other with prearranged multiple, and makes the complete computing frequency and the complete power mode activation of microprocessor 400.PLL 203 is able to programme, falls into selecting and often lower frequency in the frequency range that can be used for the power management purposes and produce.Pulse control logic circuit (or controller) the 207th, with as be used for the above-mentioned similar fashion of power management logic circuit 103, and, come the power situation of sensing system via the power sensing signal on the sensing interface 209 (for example, bus).Pulse control logic circuit 207 can be via core ratio bus value RATIO2, and indication PLL 203 rises or drop in order to reach as the characteristic frequency multiple by the power management target of the represented core logic circuit 206 of power sensing signal.In shown specific embodiment, though in other form can be included in, and generally will consider frequency control signal, the RATIO2 bus value is the multiple value relevant with the bus pulse signal.PLL 203 can respond the RATIO2 bus value, and changes frequency, and meeting marker pulse control logic circuit 207, and it operates on specified frequency by enable signal LOCK2.At this moment, if the power situation of new frequency current potential is still effective, then pulse control logic circuit 207 can optionally be indicated multiplexer 205, via SEL, selects CORE SRC 2 to be used as the core pulse signal.From the transformation of CORE SRC 1 to CORE SRC 2 is " moment ", as in the single cycle of bus pulse signal.In another embodiment, after the value of setting RATIO2, pulse control logic circuit 207 can postpone the recurrence interval of programmable number, indicates multiplexer 205 then, selects CORE SRC 2 to be used as the core pulse signal.In this another embodiment, can not use signal LOCK2.The number of recurrence interval is via writing machine specific register (not shown) or via the fuse (not shown) of blowing on the parts (part), and able to programme.The another kind of variation is that pulse control logic circuit 207 comprises the logical circuit (not shown), in order to before switching to CORE SRC 2, postpones the recurrence interval of fixed number.

Be noted that up to PLL 203 and pin the fresh target frequencies and before changing, power-supply management system 200 can use CORE SRC 1 when the core pulse that elect; And when PLL 203 pinned the fresh target frequency, the core pulse signal can switch in quick seamless mode.Therefore, switch to next power rating from a kind of power rating moment, can be more a lot of soon than switch speed before.The user can receive benefits from the power adjustment, and can not cause excessive deferral or usefulness to reduce.

If computing environment changes (as representing by sensing interface 209), so that the time durations that is just rising or descending at PLL 203, can need the complete operation frequency once more, pulse control logic circuit 207 can not make multiplexer 205 switch to CORE SRC 2 from CORE SRC 1 then.In this way, even power needs to change once more, but, can not cause the reduction of usefulness the intercycle of PLL 203 in the transition period.Moreover, after switching to CORE SRC 2, if computing environment changes, so that need complete power, or show any other power potential, then pulse control logic circuit 207 meeting switchbacks immediately, and select the CORE SRC 1 that comes from PLL 201 to be used as the core pulse signal.Moreover, switch to moment and seamless, as in the one-period of bus pulse.After switching back to CORE SRC 1, pulse control logic circuit 207 can be programmed to PLL 203 the frequency current potential of any needs again.

In shown embodiment, PLL 201 can keep pinning complete power running, can at any time take place so that switch back to CORE SRC 1, and can take place repeatedly in the quite short cycle.For example, suppose that power situation represents 50% power potential, so that PLL 203 can make CORE SRC 2 get back to 50% frequency current potential, and core pulse meeting switches to CORESRC 2, can need 75% current potential suddenly afterwards.In the case, pulse control logic circuit 207 is switchback CORE SRC 1 immediately, sets the value of RATIO2 bus then, to show 75% current potential of PLL 203.Even temporary transient power ratio necessity that consumes is more, but system delay phenomenon can not take place.When using PLL 203 to pin the LOCK2 signal activation of 75% frequency current potential with expression CORE SRC 2 frequency signals, if power situation still shows the power potential of needs 75%, then the core pulse signal can switch to CORE SRC 2 immediately.

Except changing frequency, present microprocessor also comprises the supply (provision) that drives the voltage of core logic circuit in order to modulation.Those skilled in the art will understand that the core logic circuit that operates on lower frequency also can operate on low voltage, and can not cause loss of efficacy.For example, present CMOS manufacture craft need for example be 1.5 volts a core voltage, drives the parts of 1GHz.But when operating frequency is reduced to 500MHz, do not need 1.5 volts core voltage, and replacement is only to need 1.1 volts core voltage.Therefore, by combination frequency and voltage modulation, can save power further.

Sensing interface 209 can further be coupled to voltage controller or Control of Voltage logical circuit 211, its configuration is in order to the modulation of the operating voltage of the core logic circuit 206 in the control microprocessor 400, to guarantee that for known operating frequency the power consumption of microprocessor 400 is minimum.Pulse control logic circuit 207 is understood via one or more signal OPRATIO, and present operational ratio is sent to Control of Voltage logical circuit 211.Control of Voltage logical circuit 211 can be sent to pulse control logic circuit 207 with operating voltage status signal OPVTG.Control of Voltage logical circuit 211 is via signal VDDSTEP, and the operating voltage that indication needs is to external power source supply (being shown as VRM 213), and it externally is coupled to microprocessor 400 via voltage interface 215.VRM 213 understands via the power bus VDD that couples by voltage interface 215, and the operating voltage of needs is sent to microprocessor 400, and wherein VDD internally is sent to core logic circuit 206.When VRM 213 had made the operating voltage that needs arrive VDD, it can make signal VDDLOCK activation, and this signal internally is sent to pulse control logic circuit 207 from voltage interface 215.

The time durations that is just rising or descending at PLL 203, or if computing environment changes, so that need complete operation ratio (as represented on the sensing interface 209), then pulse control logic circuit 207 can be via SEL, and indication multiplexer 205 continues to use CORE SRC 1 to be used as the core pulse signal.If the ensuing switching of computing environment becomes CORE SRC 2 and low voltage, then Control of Voltage logical circuit 211 can make the activation of VDDSTEP signal, and makes operating voltage VDD increase to the voltage that matches with the complete operation ratio.VRM 213 can receive the VDDSTEP signal, then the VDD signal is increased, and when the VDD signal stabilization, can make the activation of VDDLOCK signal.Pulse control logic circuit 207 can detect the order that increases operating voltage via the OPVTG signal.Pulse control logic circuit 207 can detect the VDDLOCK signal, and switches the SEL signal, and selects PLL 201, and CORE SRC 1 is used as the core pulse signal.In another embodiment, in Control of Voltage logical circuit 211, receive OPVTG after, the frequency ratio control logic circuit can postpone the recurrence interval of programmable number, indicates multiplexer 205 then, selects CORE SRC 1 to be used as the core pulse signal.In this another embodiment, can not use signal VDDLOCK.The number of recurrence interval is via writing machine specific register (not shown) or via the fuse (not shown) of blowing on the parts, and able to programme.Another kind is that before switching to CORE SRC 1, pulse control logic circuit 207 comprises the logical circuit (not shown) in the recurrence interval that postpones fixed number.

Control of Voltage logical circuit 211 and pulse control logic circuit 207 be running together, with guarantee operating voltage (that is, VDD) be enough to support the existing frequency and the new frequency of core pulse signal.Therefore, after the frequency that reduces the core pulse signal, operating voltage can be reduced, and before the frequency that increases the core pulse signal, operating voltage can be increased.Operate the frequency of core pulse signal in this way, can not exceed the suitable potential of operating voltage.

The present invention also comprises some embodiment, and it can change frequency and voltage (if the words that need) simultaneously along with computing environment shown on the sensing interface 209 changes.According to these embodiment, if showing, sensing interface 209 reduces frequency, then pulse control logic circuit 207 can be indicated the frequency that reduces the core pulse signal, and reduction operating voltage, the activation (or postponing some recurrence intervals) of LOCK x and VDDLOCK can be waited for then, the new CORE SRC x of core pulse can be switched to then.Only after finishing this change, these embodiment just can detect the new change on the sensing interface 209.Therefore, as if the time durations that is just rising or descending at PLL 201,203, or the time durations that is just rising or descending at VRM 213, computing environment changes, then up to switching core pulse (and VDD, if the words that need) afterwards, just can detect the change on the sensing interface 209.

The calcspar of another voltage to frequency power-supply management system 300 that Fig. 3 is implemented according to another embodiment of the present invention.System 300 and system 200 are similar, the identical reference number of wherein similar assembly hypothesis.For system 300, PLL 201 replaces by programmable PLL 301 (its configuration and function and PLL 203 are similar).Pulse control logic circuit 207 can be sent to PLL 301 with another ratio bus RATIO1, and with the previous described similar fashion that is used for PLL 203, with the frequency program of CORE SRC 1.When CORE SRC1 signal pinned by the represented frequency of the value of RATIO1 bus, PLL 301 can transfer back to pulse control logic circuit 207 with pinning signal LOCK1.Pulse control logic circuit 207 comprises the supply in order to monitoring VDDLOCK and LOCK1 signal, to guarantee can to pin operating voltage and PLL 301 simultaneously before switching to the CORE SRC 1 that is used as the core pulse signal.System 300 can not fix because of CORE SRC 1 signal, and replacement is to may be programmed to any frequency except maximum operating frequency, and can increase elasticity.Switch running with Control of Voltage logical circuit 211 as discussed previously and 207 runnings of pulse control logic circuit, with guarantee operating voltage (that is, VDD) can support the existing frequency and the new frequency of previously mentioned core pulse signal.

Except above embodiment (as cooperating Fig. 2), the present invention looked forward to pulse control logic circuit 207 before switching, and can wait for the recurrence interval of fixing or programmable number, used the embodiment that pins signal LOCK1, LOCK2, VDDLOCK to replace.In addition, can be included in before the sensing interface 209 of monitoring once more, can switch core pulse (and operating voltage, if the words that need) about the ensuing change of computing environment, next can be via sensing interface 209, and an embodiment of detection computations environment change.

Fig. 4 comprises the simplification calcspar of the microprocessor 400 of voltage to frequency power-supply management system 200 or 300.One or more pins 401 of microprocessor 400 can receive the bus pulse signal (being produced on the motherboard as computer system) that comes from external source, and wherein the bus pulse signal can be sent to the power-supply management system 200/300 in the microprocessor 400.PLL 201 or 301 in the power-supply management system 200/300, and 203 can make core pulse signal and bus pulse signal maintenance homophase.The external interface 403 that comprises one or more pins is understood the outside sensing signal of reception, and it is understood via sensing interface 209, and is sent to power-supply management system 200/300.Outside sensing signal can for example comprise any other power sensing signal that signal, afterpower signal (for example, showing low battery power) or those skilled in the art of being produced by converter temperature or similar device are known.Sensing interface 209 also can receive inner sensing signal, as comes from internal buffer 405 or similar device.The operating system that comprises the computer system of microprocessor 400 for example can be set one or more positions of one or more buffers 405, with the new power potential of command processor 400.Voltage interface 215 also shows meeting via VDDSTEP as discussed previously, VDDLOCK and VDD signal, and is coupled to VRM 213, and wherein VDD is internally in order to be used as the operating voltage of core logic circuit 206.

Power-supply management system 200/300 can come the change of responding power situation by the frequency of modification core pulse signal as discussed previously and the voltage of VDD.System 200 can switch between programmable frequency and maximum frequency, and system 300 can switch between two programmable frequencies in office.

Fig. 5 illustrates the process flow diagram according to the example running of the power-supply management system 300 of one embodiment of the invention.The running of power-supply management system 200 is similar before to have been discussed, and was summarized as follows.At first square 501, power-supply management system 300 can initialization.At next square 503, pulse control logic circuit 207 can be set the value of RATIO1 bus, and selects CORE SRC 1 signal to be used as the core pulse signal, in order to be used as the initial default value of complete power mode.Moreover at square 503, Control of Voltage logical circuit 211 can make the VDDSTEP activation, is input operating range and select VDD, in order to be used as the default value of complete power mode.At next square 505, can scan via the received power sensing signal of sensing interface 209, to judge whether to show new and different power potential.Running can continue to query block 507, judges the processing based on square 505, whether should change power potential.If power potential is suitable at present, then running can be proceeded query block 508, whether reduces VDD with decision, and if so, can proceed to change or reduce VDDSTEP, and proceeds to the square 510 that VDD reduces.As described below, when expection can improve frequency when increasing power, can increase VDD earlier, but during the power potential that no longer needs to increase if power situation changes, then square 510 is in order to be lowered into suitable potential with VDD.From any of square 508 or 510, as long as present power potential is suitable, then operates the loop and can return square 505, and the running loop between square 505,507 and 508.

If judge as square 507, need new power potential, whether running can be proceeded query block 509, can increase from present current potential to judge power.Increase power if power is in to reduce current potential and need, then running can be proceeded square 511, wherein can change or increase the VDDSTEP signal, and the VDD current potential of new power potential is suitably increased.At square 511, make after the activation of VDDSTEP signal, or judge as square 509, do not increasing power (that is, reducing power), then running can be proceeded query block 513, to judge whether at present selected be CORE SRC 1 signal.If judge as square 513, at present selected is CORE SRC 1 signal, then running can be proceeded square 515, and its medium frequency logical circuit 207 can be set the value of RATIO2 bus for suitable potential, and makes PLL 203 be programmed for new frequency current potential.Running can be proceeded next query block 517, and whether the two passes through PLL 203 and 213 activations of VRM respectively wherein can to judge LOCK2 and VDDLOCK signal.Because PLL 203 can spend many core recurrence intervals, pin new frequency, so often can not make the activation of LOCK2 signal immediately.If square 511 do not change the VDDSTEP signal, then VDD can be assumed to be stable, and activation VDDLOCK signal.If square 511 changes the VDDSTEP signals, this fashion activation VDDLOCK signal not then.Before the frequency that increases the core pulse signal, must wait for up to making the activation of VDDLOCK signal, and finish the increase of power potential.

If do not wait for VDDLOCK and LOCK2 signal, then operate the loop and can return square 505, and rescan and the processing power sensing signal.When still needing to change new power potential, the running meeting forms the loop between square 505,507,509,513,515 and 517, is activation up to LOCK2 and VDDLOCK signal.And if when in square 517, detect LOCK2 and VDDLOCK signal all during activation, and running can be proceeded square 519, and wherein pulse control logic circuit 207 can switch, and selects CORE SRC 2 signals to be used as the core pulse signal.Whether then, running can be proceeded query block 521, reduce with the determination frequency current potential.If the frequency current potential reduces, then running can be proceeded square 523, and wherein Control of Voltage logical circuit 211 can change the VDDSTEP signals, and makes VDD be reduced to suitable potential about the new frequency current potential of core pulse signal.After square 523 changes the VDDSTEP signal, or as if what determined in square 521, frequency does not reduce, and then operates the loop and can return square 505.

Return with reference to square 513, if present non-selected CORE SRC 1 signal, then get and generation be that running can be proceeded square 525, wherein pulse control logic circuit 207 can be set the value of RATIO1 bus for suitable potential, and makes PLL 301 be programmed for new frequency current potential.Running can be proceeded next query block 527, and whether the two passes through PLL 301 and 213 activations of VRM respectively wherein can to judge LOCK1 and VDDLOCK signal.Because PLL 301 can many core recurrence intervals of cost, pin new frequency, or if its when increasing the VDD signal can change, so square 505 can be initially returned in the running loop.Do not wait for VDDLOCK and LOCK1 signal, the running loop can return square 505, and with previous described similar fashion, rescan and the processing power sensing signal.When still needing to change new power potential, the running meeting forms the loop between square 505,507,509,513,525 and 527, is activation up to LOCK1 and VDDLOCK signal.And if when in square 527, detect LOCK1 and VDDLOCK signal all during activation, and running can be proceeded square 529, and wherein pulse control logic circuit 207 can switch, and selects CORE SRC 1 signal to be used as the core pulse signal.Then, running can be proceeded query block 521, whether reduces (as discussed previously) with the determination frequency current potential, with at square 523, judges whether to change the VDD signal.

Be noted that if show new power potential (at square 507), and when PLL 203 or 301 is just rising or drop to new frequency current potential, still can select present selected CORE SRC1 or CORE SRC 2 signals.Only pin new frequency current potential (VDD pinning), and as long as new frequency current potential is still effective, pulse control logic circuit 207 just can switch the core pulse signal at the PLL of beating.For example, be noted that, if select PLL 301, and PLL 203 is just being beated and is being arrived different power potential, need different power (as when waiting for the activation of LOCK2 then suddenly, square 505 in the loop is detected), then square 507 can judge whether present power potential mates with new power potential.If so, the running meeting forms the loop between square 505,507 and 508.As previously mentioned, if at square 511, change the VDDSTEP signal, and VDD is increased, then before activation VDDLOCK, if square 507 judges that present power potential is for effective once more, then square 510 can make VDD reduce, and gets back to the suitable potential about the present frequency of core pulse signal.

The process flow diagram of power-supply management system 200 can be because do not need square 525, and running can directly be carried out square 527 and simplifies.Moreover, because PLL 201 keeps synchronous with the maximum frequency of peak power, so, only can check the VDDLOCK signal at square 527.Moreover after square 529 switched, in case because VDDLOCK is enabled, VDD just can switch back to the peak power current potential, and needn't reduce VDD, so the running meeting is directly returned square 505 from square 527.For system 200, only PLL 203 programmings can be selected to reduce power mode, and just jump to new frequency current potential and when reaching new power potential when PLL 203, can temporary transient selection PLL 201.

In shown any form, switch and to take place to moment, so that microprocessor 400 can at any time not suspend.In this way, the user can not experience system halt, or the application apparatus pinning, and can receive benefits from low-power mode.

Though the present invention is with reference to its some preferred versions, and quite explain, other form and variation be feasible and can be included in.For example, be used for microprocessor, can comprise other circuit unit though the present invention shows.Moreover power source management controller may be implemented in the outside, controls a plurality of assemblies.At last, what those skilled in the art should recognize is, do not breaking away under defined spirit of the present invention of accompanying Claim and the scope, in order to carry out the purpose identical with the present invention, it can use the notion and the certain embodiments of announcement immediately, the basis of being used as design or revising other structure.

Claims

1. A frequency voltage device for power management, characterized in that it comprises:

a first phase-locked loop for generating a first source pulse signal at a first frequency based on a bus pulse signal;

a second phase-locked loop for generating a second source pulse signal at a second frequency based on a first frequency control signal and the bus pulse signal;

a selection logic circuit, based on a selection signal, selects between the first source pulse signal and the second source pulse signal to generate a core pulse signal;

a pulse control logic circuit for detecting a power condition according to at least one power sensing signal, for generating the first frequency control signal according to the power condition, and for generating the selection signal; and

A voltage control logic circuit, coupled to the pulse control logic circuit, is used to adjust an operating voltage to match the frequency of the core pulse signal.

2. The frequency voltage device as claimed in claim 1, wherein within a pulse period of the bus pulse signal, the selection logic circuit switches the core pulse signal according to the selection signal.

3. The frequency voltage device as claimed in claim 1, wherein when the second source pulse signal reaches a reduced frequency represented by the first frequency control signal, the second phase-locked loop will generate a first frequency Lock signal.

4. The frequency voltage device as claimed in claim 3, wherein the pulse control logic circuit responds to the first frequency lock signal, and controls the selection signal to select the second phase-locked loop to generate the core pulse signal .

5. The frequency voltage device of claim 4, wherein the voltage control logic circuit reduces the operating voltage after switching the core pulse signal.

6. The frequency voltage device of claim 4, wherein the voltage control logic increases the operating voltage in response to an increased power condition, and wherein after increasing the operating voltage, the pulse control logic controls the selection signal to select the first source pulse signal to generate the core pulse signal.

7. The frequency voltage device as claimed in claim 6, further comprising:

the voltage control logic circuit enables a voltage step signal to adjust the voltage; and

A power supply adjusts the operating voltage based on the voltage step signal, and transmits an indicative voltage lock signal to the pulse control logic circuit.

8. The frequency voltage device as claimed in claim 1, wherein the first phase-locked loop enables the first frequency source signal based on a second frequency control signal, and makes the signal representing the first frequency source A second frequency lock signal is enabled, and wherein the pulse control logic circuit generates the second frequency control signal and receives the second frequency lock signal.

9. The frequency voltage device of claim 1 , wherein the pulse control logic circuit and the voltage control logic circuit work together to increase the operating voltage before increasing the frequency of the core pulse signal, and decrease the core The frequency of the pulse signal is then reduced to the operating voltage.

10. A microprocessor, characterized in that it comprises:

a power condition sensing interface for receiving at least one power sensing signal representing a power condition;

an operating voltage interface;

A first phase-locked loop, based on a bus pulse signal and a first core ratio bus value, generates a first source signal at a frequency, and is used to generate a corresponding first lock signal;

a second phase-locked loop for generating a second source signal at a frequency based on the bus pulse signal;

a pulse controller, coupled to the power condition sensing interface and the first phase-locked loop and the second phase-locked loop, for generating pulses in the first phase-locked loop and the second phase-locked loop a select signal for switching between, for generating the first core ratio bus value controlling the frequency of the first source signal, and for receiving the corresponding first lock signal;

a selection logic circuit, based on the selection signal, selects and outputs one of the first source signal and the second source signal to generate a core pulse signal; and

A voltage controller, coupled to the pulse controller and the operating voltage interface, is used to adjust the operating voltage to correspond to the frequency of the core pulse signal.

11. The microprocessor of claim 10, wherein:

The second phase-locked loop generates the second source signal at a maximum power frequency level;

wherein the pulse controller initially selects the second source signal of the second phase locked loop, determines a reduced power level sufficient to meet the power condition, generates the first core ratio bus representing a reduced frequency of the core pulse signal value, after reaching the reduced power level, in response to receiving the first lock signal, switching the selection signal to select the first source signal of the first phase locked loop;

wherein the first phase locked loop returns the first source signal to the reduced frequency and generates the first locked signal indicative thereof; and

After the pulse controller switches the core pulse signal, the voltage controller reduces the operating voltage to be commensurate with the core pulse signal.

12. The microprocessor of claim 11, wherein:

the voltage controller detects an increased power potential sufficient to meet the power condition and increases the operating voltage; and

After the operating voltage increases, the pulse controller adjusts the selection signal to select the first source signal of the first phase-locked loop.

13. The microprocessor as claimed in claim 10, wherein the second phase-locked loop adjusts the frequency of the second source signal based on the bus pulse signal and a second core ratio bus value, and is used to generate the signal representing the A second lock signal of the second source signal, and the pulse controller generates the second core ratio bus value and receives the corresponding first lock signal.

14. The microprocessor of claim 13 , wherein the pulse controller and the voltage controller work together to reduce the operating voltage after reducing the frequency of the core pulse signal, and to increase the frequency of the core pulse signal Increase the operating voltage before the frequency.

15. A method for frequency and voltage control of microprocessor power management, comprising: generating a first source pulse signal at a first frequency based on a bus pulse signal and a first ratio bus value;

generating a second source pulse signal at a second frequency based on the bus pulse signal and a second ratio bus value;

sensing a power condition;

selecting and outputting one of the first source pulse signal and the second source pulse signal to obtain a core operating frequency of a core pulse signal based on the sensed power condition; and

Choose an operating voltage commensurate with the core operating frequency.

16. The method of claim 15, further comprising:

initially selecting the first source pulse signal as the core pulse signal;

generating the second ratio bus value to indicate a reduced frequency based on reduced power conditions;

returning the second source pulse signal to the reduced frequency in response to the second ratio bus value;

detecting a first lock indication when the second source pulse signal reaches the reduced frequency;

Selecting to output the second source pulse signal when the first lock indication is detected; and

After the second source pulse signal is selected to be output, the operating voltage corresponding to the reduced frequency is reduced.

17. The method of claim 16, wherein switching to the second source pulse signal comprises switching within a bus pulse cycle.

18. The method of claim 16, comprising:

sensing increased power conditions;

increasing the operating voltage corresponding to the sensed power condition; and

Select to output the first source pulse signal.

19. The method of claim 18, wherein, before switching to the first source pulse signal, further comprising:

determining an increased power potential suitable for the increased power condition;

generating the first ratio bus value representing an increasing frequency based on the increasing power potential;

returning the first source pulse signal to the increased frequency;

The increasing the operating voltage includes increasing the operating voltage corresponding to the increasing frequency; and

When the first source pulse signal reaches the increased frequency, a second lock indication is detected.

20. The method of claim 18, wherein switching to the first source pulse signal comprises switching within a bus pulse cycle.