[go: up one dir, main page]

CN1328660C - 具有共享存储器的改进结构 - Google Patents

具有共享存储器的改进结构 Download PDF

Info

Publication number
CN1328660C
CN1328660C CNB038067447A CN03806744A CN1328660C CN 1328660 C CN1328660 C CN 1328660C CN B038067447 A CNB038067447 A CN B038067447A CN 03806744 A CN03806744 A CN 03806744A CN 1328660 C CN1328660 C CN 1328660C
Authority
CN
China
Prior art keywords
memory
processor
processors
access
bank
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
CNB038067447A
Other languages
English (en)
Chinese (zh)
Other versions
CN1668999A (zh
Inventor
鲁迪·弗伦策尔
拉杰·库马尔·贾因
马库斯·特施鲁泽
克里斯蒂安·霍拉克
斯特凡·乌勒曼
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Infineon Technologies AG
Original Assignee
Infineon Technologies AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US10/117,668 external-priority patent/US20030088744A1/en
Priority claimed from US10/133,941 external-priority patent/US7346746B2/en
Application filed by Infineon Technologies AG filed Critical Infineon Technologies AG
Publication of CN1668999A publication Critical patent/CN1668999A/zh
Application granted granted Critical
Publication of CN1328660C publication Critical patent/CN1328660C/zh
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Images

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1605—Handling requests for interconnection or transfer for access to memory bus based on arbitration
    • G06F13/1652—Handling requests for interconnection or transfer for access to memory bus based on arbitration in a multiprocessor architecture
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/06—Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication
    • G06F12/0607—Interleaved addressing

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Multi Processors (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
CNB038067447A 2002-04-04 2003-04-04 具有共享存储器的改进结构 Expired - Fee Related CN1328660C (zh)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US10/117,668 2002-04-04
US10/117,668 US20030088744A1 (en) 2001-11-06 2002-04-04 Architecture with shared memory
US10/133,941 US7346746B2 (en) 2002-04-26 2002-04-26 High performance architecture with shared memory
US10/133,941 2002-04-26
PCT/EP2003/003547 WO2003085524A2 (en) 2002-04-04 2003-04-04 Improved architecture with shared memory

Publications (2)

Publication Number Publication Date
CN1668999A CN1668999A (zh) 2005-09-14
CN1328660C true CN1328660C (zh) 2007-07-25

Family

ID=28793881

Family Applications (1)

Application Number Title Priority Date Filing Date
CNB038067447A Expired - Fee Related CN1328660C (zh) 2002-04-04 2003-04-04 具有共享存储器的改进结构

Country Status (6)

Country Link
US (1) US20060059319A1 (de)
EP (2) EP1628216B1 (de)
KR (1) KR100701800B1 (de)
CN (1) CN1328660C (de)
DE (1) DE60316197T2 (de)
WO (1) WO2003085524A2 (de)

Families Citing this family (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7174437B2 (en) * 2003-10-16 2007-02-06 Silicon Graphics, Inc. Memory access management in a shared memory multi-processor system
US7631132B1 (en) * 2004-12-27 2009-12-08 Unisys Corporation Method and apparatus for prioritized transaction queuing
KR100688537B1 (ko) 2005-03-16 2007-03-02 삼성전자주식회사 다수개의 프로세서들에 억세스 가능한 메모리 장치를 갖는시스템
KR100728650B1 (ko) * 2005-07-26 2007-06-14 엠텍비젼 주식회사 복수 경로를 통한 다중 분할된 메모리 공유 방법 및 장치
KR100658588B1 (ko) * 2005-11-16 2006-12-15 엠텍비젼 주식회사 메모리 공유 시스템 및 그 방법
KR100658591B1 (ko) * 2005-11-23 2006-12-15 엠텍비젼 주식회사 공유 메모리를 이용한 디스플레이 제어 방법 및 장치
US8074031B2 (en) 2005-12-20 2011-12-06 Nxp B.V. Multi-processor circuit with shared memory banks
KR100740635B1 (ko) 2005-12-26 2007-07-18 엠텍비젼 주식회사 휴대형 단말기 및 휴대형 단말기에서의 공유 메모리 제어방법
KR100700040B1 (ko) * 2006-03-08 2007-03-26 엠텍비젼 주식회사 공유 메모리를 구비한 장치 및 공유 메모리 억세스 상태정보 제공 방법
KR100748191B1 (ko) 2006-04-06 2007-08-09 엠텍비젼 주식회사 공유 메모리를 구비한 장치 및 공유 메모리 억세스 상태정보 제공 방법
KR100843580B1 (ko) * 2006-05-24 2008-07-04 엠텍비젼 주식회사 접근 권한 레지스터 로직을 갖는 다중 포트 메모리 장치 및그 제어 방법
KR100834373B1 (ko) * 2006-06-05 2008-06-02 엠텍비젼 주식회사 다중 포트 메모리 장치 및 그 접근 권한의 제어 방법
KR100855701B1 (ko) * 2007-01-26 2008-09-04 엠텍비젼 주식회사 복수의 프로세서 코어가 통합된 칩 및 데이터 처리 방법
KR101091844B1 (ko) * 2007-05-17 2011-12-12 삼성전자주식회사 고속으로 배드 블록을 검색하는 플래시 메모리 시스템 및그것의 배드 블록 관리 방법
US8239566B2 (en) * 2008-02-28 2012-08-07 Silicon Graphics International, Corp. Non-saturating fairness protocol and method for NACKing systems
CN101706788B (zh) 2009-11-25 2012-11-14 惠州Tcl移动通信有限公司 一种嵌入式文件系统的跨区访问方法
CN101867833A (zh) * 2010-06-12 2010-10-20 北京东方艾迪普科技发展有限公司 一种视频图像格式转换方法和装置
WO2012070319A1 (ja) 2010-11-25 2012-05-31 インターナショナル・ビジネス・マシーンズ・コーポレーション 複数のプロセッサのメモリ共有化のためのメモリアクセス装置、及びそのアクセス方法
KR20150139718A (ko) 2014-06-03 2015-12-14 에스케이하이닉스 주식회사 불휘발성 메모리를 제어하는 컨트롤러 및 그것을 포함하는 반도체 장치
CN104794065B (zh) * 2015-05-04 2018-01-09 常州工学院 一种多分组定长数据循环存取方法
KR101772921B1 (ko) 2016-11-25 2017-08-30 전남대학교 산학협력단 메모리 경합 인지를 통한 그래픽 처리 장치의 전력관리 기법 및 그 기법을 수행하는 전력관리 유닛, 그래픽 처리 장치
JP2022175420A (ja) * 2021-05-13 2022-11-25 富士通株式会社 演算処理装置および演算処理方法
CN115145859B (zh) * 2022-06-27 2025-09-23 曙光信息产业(北京)有限公司 一种数据传输方法、装置、电子设备和存储介质

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3931613A (en) * 1974-09-25 1976-01-06 Data General Corporation Data processing system
US4918587A (en) * 1987-12-11 1990-04-17 Ncr Corporation Prefetch circuit for a computer memory subject to consecutive addressing
US5857110A (en) * 1991-03-19 1999-01-05 Hitachi, Ltd. Priority control with concurrent switching of priorities of vector processors, for plural priority circuits for memory modules shared by the vector processors

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5412788A (en) * 1992-04-16 1995-05-02 Digital Equipment Corporation Memory bank management and arbitration in multiprocessor computer system
US5809533A (en) * 1993-02-18 1998-09-15 Unisys Corporation Dual bus system with multiple processors having data coherency maintenance
US20030088744A1 (en) * 2001-11-06 2003-05-08 Infineon Technologies Aktiengesellschaft Architecture with shared memory

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3931613A (en) * 1974-09-25 1976-01-06 Data General Corporation Data processing system
US4918587A (en) * 1987-12-11 1990-04-17 Ncr Corporation Prefetch circuit for a computer memory subject to consecutive addressing
US5857110A (en) * 1991-03-19 1999-01-05 Hitachi, Ltd. Priority control with concurrent switching of priorities of vector processors, for plural priority circuits for memory modules shared by the vector processors

Also Published As

Publication number Publication date
EP1628216A2 (de) 2006-02-22
EP1490764A2 (de) 2004-12-29
CN1668999A (zh) 2005-09-14
KR20040093167A (ko) 2004-11-04
EP1628216B1 (de) 2007-09-05
DE60316197D1 (de) 2007-10-18
WO2003085524A2 (en) 2003-10-16
DE60316197T2 (de) 2008-04-10
WO2003085524A3 (en) 2004-08-19
EP1628216A3 (de) 2006-06-21
US20060059319A1 (en) 2006-03-16
KR100701800B1 (ko) 2007-04-02

Similar Documents

Publication Publication Date Title
CN1328660C (zh) 具有共享存储器的改进结构
US20240370387A1 (en) Memory controller with a plurality of command sub-queues and corresponding arbiters
US6272579B1 (en) Microprocessor architecture capable of supporting multiple heterogeneous processors
US5329629A (en) Apparatus and method for reading, writing, and refreshing memory with direct virtual or physical access
US6170070B1 (en) Test method of cache memory of multiprocessor system
US20070094450A1 (en) Multi-level cache architecture having a selective victim cache
US20100169578A1 (en) Cache tag memory
US12073114B2 (en) Stacked command queue
US20030088744A1 (en) Architecture with shared memory
US11995008B2 (en) Memory controller with hybrid DRAM/persistent memory channel arbitration
US6546465B1 (en) Chaining directory reads and writes to reduce DRAM bandwidth in a directory based CC-NUMA protocol
TWI235916B (en) Multilevel cache structure and method using multiple issue algorithm with over subscription avoidance for high bandwidth cache pipeline
US6094710A (en) Method and system for increasing system memory bandwidth within a symmetric multiprocessor data-processing system
US20080016282A1 (en) Cache memory system
US7346746B2 (en) High performance architecture with shared memory
EP0196244A2 (de) Anordnung von Cachespeicherverwaltungseinheiten
US7028142B2 (en) System and method for reducing access latency to shared program memory
US7159078B2 (en) Computer system embedding sequential buffers therein for performing a digital signal processing data access operation and a method thereof
US6604163B1 (en) Interconnection of digital signal processor with program memory and external devices using a shared bus interface
US20050071574A1 (en) Architecture with shared memory
Frailong et al. The next-generation SPARC multiprocessing system architecture
JPH07282023A (ja) データ転送量可変プロセッサ及びそれを用いたシステム
HK1090451A1 (en) System and method for direct deposit using locking cache
HK1090451B (en) System and method for direct deposit using locking cache
JPH01300355A (ja) キャッシュメモリの制御方法及びその装置

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant
C19 Lapse of patent right due to non-payment of the annual fee
CF01 Termination of patent right due to non-payment of annual fee