CN1325508A - Device and method for synchronizing local clock with clock of wireless communication network - Google Patents

Abstract

The invention relates to a method for synchronising the local clock of a device with the clock of a wireless communication network to which said device is connected, the network clock being transmitted by a reference device and reflecting frames according to a TDMA mode, characterised in that it comprises a step for determining the phase shift of the timing between the network clock received on a reception channel and the local clock of the device. A step of correcting the local clock received at the receiving channel according to said determined phase shift by a first correction in the time domain on the integer part of the phase shift and a second correction on the fractional part comprising the first correction uncovered by the remaining phase shift. The invention is particularly suitable for application in home wireless communication networks.

Description

Device and method for synchronizing local clock with clock of wireless communication network

The invention relates to a method of synchronizing the local clock of a device with the clock of a wireless communication network to which said device is connected. The invention also relates to a synchronization device operable according to said method in a wireless communication network.

The present invention is particularly suitable for application in home wireless communication networks.

In an IEEE1394-type bus described in IEEE Std. 1394-1995, each item of equipment connected to the bus (a "node" in IEEE1394 terminology) stamps a packet sent by the receiving device with time information representing the instant at which the packet was reconstructed by the receiving device.

Each device item (or "node") connected to the bus includes a 32-bit clock register that increments at the bus clock frequency (ie, 24.576 MHz). This register (referred to as "cyclic clock register" according to IEEE1394-1995 standard terminology) is divided into 3 areas (12 low-order bits, 13 mid-order bits and 7 high-order bits), which are divided into 24.576 Frequency increments of MHz, 8kHz and 1kHz.

When there is a device item that can perform isochronous services, and in order to synchronize this device, one of the devices is selected as the "cycle master node" or "cycle master" (according to the IEEE1394 term "cycle master"). The cycle master generates isochronous frame packets or "cycle start packets" (IEEE1394 terminology) every 125 μs (corresponding to 8 kHz frequency). This packet includes the value of the 32-bit clock register of the transmitting instantaneous loop master. Devices receiving this packet use their 32-bit registers to store the values received from the cyclic master.

The aforementioned IEEE text 1394-1995 deals with serial bus structures. Additional standards are currently being developed regarding the interconnection of several buses by means of what are commonly referred to as "bridges". The latest version of this draft currently released by IEEE involves P1394.1 Draft0.03 released on October 18, 1997.

When several buses are interconnected by means of wireless bridges, isochronous data must be sent with the same clock signal to all devices in the network. According to the terminology adopted in the text article P1394.1, from now on the item of equipment that allows connection to the bus via wireless network will be called "entry". In order to synchronize the entire network, a device item connected to one bus acts as a "network loop master" ("network loop master" according to IEEE1394 terminology). According to IEEE1394 terminology, the entry of the network loop host or the entry connected to the bus connected to the network loop host is called a "loop server". The task of the cycle server is to send the clock generated by the network cycle master to other entrances. In this way, cyclic masters on other buses set their own clocks to the clocks received from their ingress.

However, the portal's local clock must be able to be properly synchronized with the rotation server clock.

The purpose of the present invention is to provide a solution that can meet this requirement.

To this end, the object of the present invention is also to provide a method for synchronizing the local clock of a device with the clock of the wireless communication network to which the device is connected, characterized in that, using frames transmitted according to the TDMA method, the The method includes the following steps:

● Determine the timing phase between the network clock received on the receive channel and the device's local clock

Move steps.

● by a first correction in the time domain for the integer part of the phase shift, and for

A second correction for the fractional part of the remaining phase shift, according to which phase shift is determined,

Steps to correct the local clock received on the receive channel.

Therefore, with a correctly recovered network clock, the received signal is sampled with the correct phase so that reception can be performed between samples without interference.

According to one embodiment, the check sliding window is a predetermined time interval, and its start is defined according to the start of the transmitted frame, and each frame specified by each sending device corresponds to a check sliding window, and the determining step includes detecting when a frame is specified The step of the non-changing pattern that occurs at the beginning of each verification sliding window of the device that is the sender of the network clock, said pattern can provide an instant corresponding to the network clock pulse.

According to one embodiment, the detection step is accomplished using a correlation between the network clock pulses and the device's local clock pulses. In this way, the repeated appearance of the pattern in the received frame can precisely identify the exact instant when the benchmark-device-specific calibration sliding window starts. The maximum correlation number achieved at multiples of the local clock sampling frequency provides the instant of initiation of the reference device calibration sliding window with an accuracy at a subharmonic of the local clock sampling period.

In the case of an incomplete connection (ie at least when there is no direct link between the two accesses), verification information must be transmitted over the wireless network, the method comprising the step of sending on the sending channel the network clock determined on the receiving channel. Thus, the method can transfer the network clock and can send the network clock to, for example, a device on the wireless network that is not directly connected to the cycle server.

According to one embodiment, the determining step comprises the step of tracking network clock pulses.

According to one embodiment, said correction of the integer part is achieved by phase shifting the local clock pulses to a subharmonic of the device sampling period.

According to one embodiment, a second correction of the fractional part can be achieved in the frequency domain by rotating the vector representing the received samples.

According to one embodiment, the step of determining a timing phase shift is taken for a third correction of the integer part and a fourth correction of the fractional part of said phase shift of the local clock to be transmitted on the transmission channel.

According to one embodiment, said fourth correction is performed in the frequency domain by interpolating a vector representing the transmitted samples.

According to one embodiment, the correction of the fractional part is performed in the time domain by interpolation.

According to one embodiment, the phase shift introduced into the transmit channel is larger than the phase shift introduced into the receive channel, therefore, during the transmit frame, the processing time spent on encoding symbols, addressing symbol constellation, symbol modulation should be considered , to anticipate this processing time when building the clock to send.

A further object of the invention is to provide a synchronization device adapted to implement the method according to one of the preceding claims for synchronizing the local clock of a device with the clock of a wireless communication network to which said device is connected, characterized in that With frames transmitted according to the TDMA mode, the apparatus comprises:

● Used to determine the alignment between the network clock received on the receive channel and the local clock of the device

Time phase shifting device;

● First assembly for correcting the local clock of the device according to the determined phase shift at the receive channel

position, the first set of means includes first means for correcting the integer part of the phase shift in the time domain and

Second means for correcting the fractional part of the phase shift including the residual phase shift.

According to one embodiment, the determining means comprises: a correlator for providing network clock pulses within the device sampling period at the subharmonic; and a local clock tracking unit for locking the local clock to the network clock.

According to one embodiment, said first set of correction means comprises:

a first unit for passing the delay corresponding to the integer part of said phase shift determined,

It is used to perform timing phase shift on the receiving channel that causes the phase shift of the local clock pulse;

The first processing unit is used to correspond to the fractional part determined in the receiving channel

move.

According to one embodiment, said synchronizing means comprise a second set of means for correcting the local clock of said device on the transmit channel according to the determined phase shift, the second set of means comprising: third means for correcting in the time domain an integer part of the phase shift; fourth means for correcting the fractional part of the phase shift including the residual phase shift.

According to one embodiment, the second set of correction means includes:

a second unit for passing the delay corresponding to the integer part of said phase shift determined,

Phase shift the sending channel that causes the phase shift of the local clock pulse;

The second processing unit is used to perform the phase corresponding to the fractional part determined in the receiving channel

move.

According to one embodiment, the first processing unit and the second processing unit respectively include a unit for calculating Fourier transform and a unit for calculating inverse Fourier transform, and each processing unit includes a vector representing frame samples that can be rotated in the frequency domain the phase shifter.

According to one embodiment, said first processing unit and said second processing unit each comprise an interpolator capable of interpolating the phase shift according to the determined fractional part and capable of delaying the device clock by calculating the delay over the transmission channel.

Other characteristics and advantages of the invention will become more apparent from the following description of an embodiment, as a non-limiting example, with reference to the accompanying drawings, in which:

Fig. 1 shows three IEEE1394 buses connected by a network bridge comprising three portals communicating with each other through wireless transmission;

Figure 2 shows a synchronization device according to an embodiment of the present invention;

Figure 3 shows a synchronization device according to an alternative embodiment of the invention.

To simplify the description, the same reference numerals denote elements with the same function.

Although this embodiment relates to the IEEE1394 bus and related wireless networks, and although some of the terms related to this type of bus are used in this specification, the present invention is not limited to the IEEE1394 bus and the present invention can be applied to other application environments .

Figure 1 shows a network comprising three IEEE1394 buses, reference numbers 1, 2, and 3 are interconnected through a wireless network 50, and each bus is connected to the wireless network 50 through known devices, according to the terminology adopted in the P1394.1 text, reference numbers 1, 2, 3 are referred to as "entrances" WL1, WL2 and WL3. In this example, the portals communicate with each other at radio frequency via wireless transmission. The connections between the portals can be considered to form what are currently called wireless "bridges" interconnecting the buses.

These entries WL1, WL2, WL3 are also part of the bus 1, 2, 3 respectively and constitute nodes in the sense of the IEEE1394 standard in the same way as the other equipment items 5, 6 connected to the bus.

In order to synchronize the entire network, a device 4 connected to the bus 1 acts as a "network loop master" ("network loop master" according to IEEE1394 terminology). Note that this concept is broader than "loop master" which is limited to one bus. The network cyclic master 4 which can act as an entry can be designated as a "bridge manager" (according to IEEE1394 terminology) among the cyclic masters of the various buses.

The entry WL1 connected to the bus to which the network loop master 4 is connected is called a "loop server" according to IEEE1394 terminology. In this example, device WL1 is the loop server. The task of the cycle server WL1 is to send the clock generated by the network cycle master device 4 to other access devices WL2 and WL3. The cycle masters of the other bus 2, 3 are set to the clock received from the other corresponding entry device WL2, WL3.

Wireless networks use the principle of TDMA (which stands for "Time Division Multiple Access") to access wireless transmission channels, subdividing TDMA frames into sliding windows during which various devices can transmit. The check sliding window is a predetermined time interval, and the start of the frame is defined according to the start of the frame, and each frame specified by each entrance device of the wireless network that can be sent corresponds to a check sliding window.

The ingress device WL1 sends the network clock to the wireless network, and the devices WL2 and WL3 receive the sent network clock. For easier understanding, the process of keeping the device 5 in sync with the clock is now focused on. Obviously, this description can be extended to other devices on the wireless network. In the specific case where a device (not shown) in a wireless network is not connected to device WL1, that is, when there is no direct link between the device and device WL1, the device can be considered to have a direct link with it. And can transmit the clock synchronization of the network clock device.

FIG. 2 shows the synchronization means 7 contained in the device WL2 according to a first embodiment of the invention. This device 7 comprises two channels 8, 9 connected to a wireless network 50 for reception and transmission respectively. The device 7 comprises in its receive channel 8, on which TDMA frames are received, a phase correlator 10 connected in parallel with a first phase shift unit 11, in which it is known to comprise a delay line and by means of which a variable The delay is used as the sampling instant of the native clock. The operation of this circuit is explained below. The output end of the correlator 10 is connected to the input end of the phase estimator 12, and the other input end of the phase estimator 12 is connected to the output end of the first integrator 13, and the first integrator 13 can take the phase of the local clock The shift is added to the network clock received on the receive channel. The output of the phase estimator 12 is connected to the input of a loop filter 14 which outputs the phase error to the phase integrator 13 and the second phase integrator 130 . In the receiving channel, the integrator 13 controls an input terminal of the phase shift unit 11 and an input terminal of the phase shifter 15, while in the transmitting channel, the integrator 130 controls an input terminal of the second phase shift unit 16 and a phase shifter An input terminal of device 17 is controlled. The output of the phase shift unit 11 is connected to a Fourier transform calculation unit 18 which sends the samples in the frequency domain to the phase shifter 16 . The output of the phase shifter 16 as output of the means 7 is partly connected, for example, to a constellation decoding unit (or "constellation demapping block") driving a Viterbi decoder, neither of which items of equipment are shown.

The device 7 comprises at its input connected to the transmission channel 9 a phase shifter 17 controlled by an integrator 130 whose output is connected to an inverse Fourier transform calculation unit 19 which can transmit samples in the time domain. These samples are then sent to a phase shift unit 16 . The input of the means 7 is connected at the transmission channel, for example to a constellation addressing circuit followed by an encoding circuit, neither of which is shown. The integrator 13 controls the phase shifter 17 and the second phase shift unit 16 . The output of the second phase shifting unit 16 is the output of the device 7 which, as described below, sends out a clock synchronized with the network clock.

According to the embodiment shown in FIG. 2, during the acquisition phase (i.e., for example after restarting the network) and in the standby state, at the beginning of the dedicated verification sliding window, the device WL1 transmits the known preamble P wirelessly All device items for the network. According to an alternate embodiment, in order to save energy, the preamble is sent periodically every q sliding windows for checking, where q is a positive integer. The means 7 detect the presence of this known preamble P by performing conventional correlation operations with the correlator 10 . The maximum correlation number is realized with the sampling frequency multiplication of the device 7, and the device 7 provides the initial instant of the calibration sliding window of the device WL1, and its accuracy is equal to the subharmonic of the sampling period of the device 7. In fact, the correlator 10 transmits a signal whose maximum value corresponds to the detected preamble P and is between 0 and 1. Phase estimator 12 receives this signal and compares it with the output signal of integrator 13 . Thus, the DC voltage output by phase estimator 12 represents the phase difference between the two signals applied to its input. The loop filter 14 allows the DC voltage to pass and sends the DC voltage to the first integrator 13 and the second integrator 130 . Thus, as long as the correlator 10 does not detect the preamble P at the beginning of the check sliding window, the integrator 13 increments until it locks to the network clock. Obviously, the latch time can be extended according to the gain of the loop filter 14 .

Once the integrator 13 records the timing phase shift between the network clock and the device 7 clock, the integrator 13 controls the phase shift unit 11 to phase shift the local clock by an integer part of the recorded phase shift. For example, if it has been determined that the local clock has a delay of 8.3 bits relative to the network clock, the integrators 13, 130 control the phase shift circuits 11, 16 to shift the phase by 8 bits at a timing. The sampling phase difference of the remaining 0.3 bits is smaller than the subharmonic of the above sampling period. The samples arriving according to the timing logic are then applied to a Fourier transform calculation unit 18 which transforms these samples into a frequency plane. However, it is well known that by rotating the vector (I,Q) obtained from the output of unit 18, it is possible to represent the difference in timing phase in the time domain. The fine-tuning process of the sampling phase is to reverse the linear rotation of the output vector generated by the unit 18 , and the slope of this linear phase can be obtained from the fractional part calculated by the integrator 13 .

Conversely, when the device 7 has to transmit, it uses the phase shift information obtained through the integrator 130 and transmits the clock according to the above principles for setting up the receive channel. The vector in the frequency domain at the input is corrected for a linear phase shift according to the fractional part of the phase shift detected by the integrator 130, and then the output samples of unit 19 are phase shifted in the time domain according to the integer part to be adjusted for the local clock. Note that the phase shift introduced into the transmit channel is larger than the phase shift introduced into the receive channel, so the processing time necessary to transmit the frame is taken into account.

The advantage of this solution of fine-tuning the phase shift in the frequency domain is that DFDM-type multicarrier modulation is preferred when various disturbances such as multiple echoes interfere with the wave propagation.

FIG. 3 shows a synchronization device 20 according to an alternative embodiment of the device 7 . In this alternative embodiment, at the receive channel 8, the unit 18 and the phase shifter 15 are replaced by an interpolator which can correct the fractional part by interpolating in the time domain. Likewise, in the transmit channel, the unit 19 and the phase shifter 17 are replaced by an interpolator 22 which interpolates in the time domain and also corrects the fractional part.

Claims (17)

1. A method that makes it possible to synchronize the local clock of a device (WL2, WL3) with the clock of a wireless communication network to which said device (WL2, WL3) is connected, characterized in that, using frames transmitted according to the TDMA mode, the Said method comprises the following steps: ● Determining the network clock and device (WL2, WL3) received on the receive channel (8) Steps for timing phase shift between local clocks; ● by a first correction in the time domain for the integer part of the phase shift, and for A second correction for the fractional part of the remaining phase shift, according to which phase shift is determined, A step of correcting the local clock received on the receive channel (8). 2. The method according to claim 1, characterized in that, each frame assigned to each sending device of the wireless network corresponds to a check sliding window, and the determining step includes detecting when a device designated as a sender of the network clock ( Each of WL1) checks the step of the non-variant pattern present at the start of the sliding window, which pattern can provide an instant corresponding to a network clock pulse. 3. 2. A method according to claim 2, characterized in that the detection step is performed using a correlation number between a network clock pulse and a local clock pulse between the devices (WL2, WL3). 4. Method according to one of the claims 1 to 3, characterized in that the step of determining comprises the step of tracking the clock pulses of the network. 5. Method according to one of claims 1 to 4, characterized in that said correction is performed on the integer part by phase shifting the local clock pulses to subharmonics of the sampling period of the device (WL2, WL3). 6. Method according to one of claims 1 to 5, characterized in that said correction of the fractional part is performed in the frequency domain by rotating a vector representing the received samples. 7. According to the method described in one of claims 1 to 6, it is characterized in that, for the local clock that will be transmitted by the transmission channel, the third correction of the integer part and the correction of the fourth fractional part are performed on the phase shift, and a determination is made. Timing phase shift steps. 8. Method according to claim 7, characterized in that said fourth correction is performed in the frequency domain by interpolating a vector representing the transmitted samples. 9. The method as claimed in one of claims 7 to 8, characterized in that the fractional part is corrected in the time domain by means of interpolation. 10. The method as claimed in one of claims 7 to 9, characterized in that the phase shift introduced into the transmit channel is greater than the phase shift introduced into the receive channel. 11. A synchronization device adapted to perform any of the preceding claims according to synchronizing the local clock of a device (WL2, WL3) with the clock of a wireless communication network (50) to which said device (WL2, WL3) is connected. A method utilizing frames transmitted according to TDMA mode, characterized in that said means comprise: ● Used to determine the network clock and device (WL2, WL3) received on the receive channel (8) means (10, 12, 14, 13, 130) for timing phase shifts between the local clocks of ; - used to correct the device's local clock on the receive channel (8) according to the phase shift determined The first group of devices (11, 15, 18, 21), the first group of devices includes calibration in the time domain first means (11) for the integer part of the positive phase shift and for correcting the residual phase shift comprising Second means of the fractional part of the phase shift (15, 18, 21). 12. The device according to claim 11, characterized in that said determining means (10, 12, 14, 13, 130) comprise: a correlator (10) for the sampling period of the means (7) at the subharmonic The network (50) clock pulse is provided inside; and the local clock tracking unit (12, 14, 13) is used for locking the local clock to the network clock. 13. The device according to any one of claims 11 to 12, characterized in that said first set of correction means (11, 15, 18, 21) comprises: a first unit (11), by a delay corresponding to the integer part of said phase shift determined, It is used to perform timing phase shift on the receiving channel (8) that causes the phase shift of the local clock pulse; ● a first processing unit (15, 18, 21) for determining according to the received channel (8) The fractional part is phase shifted. 14. Arrangement according to one of claims 11 to 13, characterized in that said synchronizing means comprise a local unit for correcting said devices (WL2, WL3) on the transmission channel (9) according to said determined phase shift A second group of means (11, 17, 19, 22) for a clock, the second group of means comprising: third means (16) for correcting the integer part of the phase shift in the time domain; fourth means (17, 19, 22 ) to correct the fractional part of the phase shift including the residual phase shift. 15. The device according to claim 14, characterized in that said second set of correction devices (11, 17, 19, 22) comprises: - second means (16) for passing the integer part corresponding to the determined said phase shift Delay, phase-shifting the transmission channel (9) that causes the phase shift of the local clock pulse; a second processing unit (17, 19, 22) for determining The fractional part of is phase shifted. 16. The device according to claim 15, characterized in that the first processing unit (15, 18, 21) and the second processing unit (17, 19, 22) respectively comprise a unit (18) for calculating the Fourier transform and the unit (19) for computing the inverse Fourier transform, the processing unit (15, 18, 21), the processing unit (17, 19, 22) respectively comprising a phase shifter (15) which can rotate a vector representing a frame sample in the frequency domain , 17). 17. The device according to claim 15, characterized in that, the first processing unit (15, 18, 21) and the second processing unit (17, 19, 22) respectively comprise The interpolators (21, 22) of the device clock are phase shifted and can be delayed by the calculated delay on the transmit channel (9).

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